LM 2776
LM 2776
LM 2776
LM2776
SNVSA56B – MAY 2015 – REVISED FEBRUARY 2017
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Typical Application
Output Impedance vs Input Voltage
LM2776 IOUT = 100 mA
2.7 V to 5.5 V -VIN @ up to 200mA
VIN VOUT 5.0
TA = -40°C
4.5 TA = 25°C
2.2 PF EN C1+ 2.2 PF TA = 85°C
4.0
Output Impedance (:)
GND 1 PF 3.5
C1-
3.0
2.5
2.0
1.5
1.0
0.5
0.0
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
Input Voltage (V) D005
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM2776
SNVSA56B – MAY 2015 – REVISED FEBRUARY 2017 www.ti.com
Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 10
2 Applications ........................................................... 1 8 Application and Implementation ........................ 11
3 Description ............................................................. 1 8.1 Application Information............................................ 11
4 Revision History..................................................... 2 8.2 Typical Application - Voltage Inverter ..................... 11
5 Pin Configuration and Functions ......................... 3 9 Power Supply Recommendations...................... 15
6 Specifications......................................................... 4 10 Layout................................................................... 15
6.1 Absolute Maximum Ratings ...................................... 4 10.1 Layout Guidelines ................................................. 15
6.2 ESD Ratings.............................................................. 4 10.2 Layout Example .................................................... 15
6.3 Recommended Operating Conditions....................... 4 11 Device and Documentation Support ................. 16
6.4 Thermal Information .................................................. 4 11.1 Device Support...................................................... 16
6.5 Electrical Characteristics........................................... 5 11.2 Receiving Notification of Documentation Updates 16
6.6 Switching Characteristics .......................................... 5 11.3 Community Resources.......................................... 16
6.7 Typical Characteristics ............................................. 5 11.4 Trademarks ........................................................... 16
7 Detailed Description .............................................. 9 11.5 Electrostatic Discharge Caution ............................ 16
7.1 Overview ................................................................... 9 11.6 Glossary ................................................................ 16
7.2 Functional Block Diagram ......................................... 9 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................... 9 Information ........................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DBV Package
6-Pin SOT
Top View
1 6
2 LM2776 5
3 4
Pin Functions
PIN
TYPE DESCRIPTION
NUMBER NAME
1 VOUT Output/Power Negative voltage output.
2 GND Ground Power supply ground input.
3 VIN Input/Power Power supply positive voltage input.
Enable control pin, tie this pin high (EN = 1) for normal operation, and to GND (EN
4 EN Input
= 0) for shutdown.
5 C1+ Power Connect this pin to the positive terminal of the charge-pump capacitor.
6 C1- Power Connect this pin to the negative terminal of the charge-pump capacitor.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2)
MIN MAX UNIT
Supply voltage (VIN to GND, or GND to VOUT) 6 V
EN (GND − 0.3) (VIN + 0.3) V
VOUT continuous output current 250 mA
Operating junction temperature, TJMax (3) 125 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) The maximum allowable power dissipation is calculated by using PDMax = (TJMax − TA) / RθJA, where TJMax is the maximum junction
temperature, TA is the ambient temperature, and RθJA is the junction-to-ambient thermal resistance of the specified package.
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
0.14 0.035
TA = -40°C
0.12 TA = 25°C 0.030
TA = 85°C
0.10 0.025
Ripple (V)
Ripple (V)
0.08 0.020
0.06 0.015
0.04 0.010
TA = -40°C
0.02 0.005 TA = 25°C
TA = 85°C
0.00 0.000
0.0001 0.001 0.01 0.1 1 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
Output Current (A) D001
Input Voltage (V) D002
VIN = 5.5 V IOUT = 100 mA
Figure 1. Output Ripple vs Output Current Figure 2. Output Ripple vs Input Voltage
0.00008
Current (A)
Current (A)
0.000001
0.00006
0.0000005
0.00004
0 TA = -40°C
0.00002
TA = 25°C
TA = 85°C
-0.0000005 0
2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
VIN (V) D003
VIN (V) D004
No load
Figure 3. Shutdown Current vs Input Voltage Figure 4. Quiescent Current vs Input Voltage
1000 100
TA = -40°C
500 TA = 25°C 90
300 TA = 85°C 80
200
Output Impedance (:)
70
100
Efficiency (%)
60
50
30 50
20
40
10
30
5
20 TA = -40°C
3
2 10 TA = 25°C
TA = 85°C
1 0
0.0001 0.001 0.010.02 0.05 0.1 0.2 0.5 1 10P 100P 1m 10m 100m
Output Current (A) D006
D005
IOUT (A) D005
D006
D007
VIN = 5.5 V VIN = 5.5 V
70 -4.9
Efficiency (%)
60
VOUT (V)
-5.0
50
-5.1
40
30 -5.2
20 TA = -40°C
TA = 25°C -5.3
10
TA = 85°C
0 -5.4
10P 100P 1m 10m 100m 10P 100P 1m 10m 100m
IOUT (A) D005
D006
D007
IOUT (A) D009
VIN = 3.6 V VIN = 5.5 V
Frequency (MHz)
-2.9 2.00
VOUT (V)
-3.0
1.98
-3.1
-3.2 1.96
-3.3 1.94
-3.4
1.92
-3.5
-3.6 1.90
10P 100P 1m 10m 100m 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
IOUT (A) VIN (V) D011
D010
VIN = 3.6 V IOUT = 150 mA
Figure 9. Output Voltage vs Output Current Figure 10. Frequency vs Input Voltage
Figure 11. Unloaded Output Voltage Ripple Figure 12. Loaded Output Voltage Ripple
Figure 15. Line Step 5.5 V to 5 V Figure 16. Load Step 10 mA to 100 mA
VIN = 5.5 V
7 Detailed Description
7.1 Overview
The LM2776 CMOS charge-pump voltage converter inverts a positive voltage in the range of 2.7 V to 5.5 V to
the corresponding negative voltage of −2.7 V to −5.5 V. The LM2776 uses three low-cost capacitors to provide
up to 200 mA of output current.
LM2776
Current
VIN
Limit
VOUT
EN
GND
Reference
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
VS+
Boost or Battery +
VS-
2.2 PF
LM2776
VIN VOUT
1 PF 2.2 PF
PP / PC EN C1+
GND C1-
COUT
GND
S3 S4
C1- VOUT
OSC.
2 MHz
PFM COMP
VIN
Figure 19. Voltage Inverting Principle
The output characteristics of this circuit can be approximated by an ideal voltage source in series with a
resistance. The voltage source equals − (VIN). The output resistance ROUT is a function of the ON resistance of
the internal MOSFET switches, the oscillator frequency, the capacitance and ESR of C1 and C2. Because the
switching current charging and discharging C1 is approximately twice as the output current, the effect of the ESR
of the pumping capacitor C1 is multiplied by four in the output resistance. The output capacitor C2 is charging and
discharging at a current approximately equal to the output current, therefore, its ESR only counts once in the
output resistance. A good approximation of ROUT is:
ROUT = (2 × RSW) + [1 / (ƒSW × C)] + (4 × ESRC1) + ESRCOUT
where
• RSW is the sum of the ON resistance of the internal MOSFET switches shown in Figure 19. (1)
High-capacitance, low-ESR ceramic capacitors reduce the output resistance.
8.2.2.1 Efficiency
Charge-pump efficiency is defined as
Efficiency = [(VOUT × IOUT) / {VIN × (IIN + IQ)}]
where
• IQ (VIN) is the quiescent power loss of the device. (2)
The peak-to-peak output voltage ripple is determined by the oscillator frequency, the capacitance and ESR of the
output capacitor COUT:
VRIPPLE = [(2 × ILOAD) / (ƒSW × COUT)] + (2 × ILOAD × ESRCOUT) (4)
In typical applications, a 1-µF low-ESR ceramic output capacitor is recommended. Different output capacitance
values can be used to reduce ripple shrink the solution size, and/or cut the cost of the solution. But changing the
output capacitor may also require changing the flying capacitor and/or input capacitor to maintain good overall
circuit performance.
NOTE
In high-current applications, TI recommends a 10-µF, 10-V low-ESR ceramic output
capacitor. If a small output capacitor is used, the output ripple can become large during
the transition between PFM mode and constant switching. To prevent toggling, a 2-µF
capacitance is recommended. For example, a 10- µF, 10-V output capacitor in a 0402
case size typically only has 2-µF capacitance when biased to 5 V.
High ESR in the output capacitor increases output voltage ripple. If a ceramic capacitor is used at the output, this
is usually not a concern because the ESR of a ceramic capacitor is typically very low and has only a minimal
impact on ripple magnitudes. If a different capacitor type with higher ESR is used (tantalum, for example), the
ESR could result in high ripple. To eliminate this effect, the net output ESR can be significantly reduced by
placing a low-ESR ceramic capacitor in parallel with the primary output capacitor. The low ESR of the ceramic
capacitor is in parallel with the higher ESR, resulting in a low net ESR based on the principles of parallel
resistance reduction.
3.5
10 Layout
LM2776
To Load
VOUT C1-
COUT C1
To GND Plane GND C1+
CIN
VIN EN
To Supply
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
www.ti.com 10-Dec-2020
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
LM2776DBVR ACTIVE SOT-23 DBV 6 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 2776
LM2776DBVT ACTIVE SOT-23 DBV 6 250 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 2776
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Apr-2020
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Apr-2020
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0006A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
C
3.0
2.6 0.1 C
1.75
B A 1.45 MAX
1.45
PIN 1
INDEX AREA
1
6
2X 0.95
3.05
2.75
1.9 5
2
4
3
0.50
6X
0.25
0.15
0.2 C A B (1.1) TYP
0.00
0.25
GAGE PLANE 0.22
TYP
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
4214840/C 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Body dimensions do not include mold flash or protrusion. Mold flash and protrusion shall not exceed 0.25 per side.
4. Leads 1,2,3 may be wider than leads 4,5,6 for package orientation.
5. Refernce JEDEC MO-178.
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EXAMPLE BOARD LAYOUT
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2 5
2X (0.95)
3 4
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
4214840/C 06/2021
NOTES: (continued)
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0006A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
6X (1.1)
1
6X (0.6)
6
SYMM
2 5
2X(0.95)
3 4
(R0.05) TYP
(2.6)
4214840/C 06/2021
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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