*PLEASE REFER MY VIDEOS BEFORE READING NOTES FOR BETTER

UNDERSTANDING.

* FOR ALL BLOCK DIAGRAMS- WRITE THE EXPLANATION WHICH YOU

UNDERSTOOD FROM THE VIDEOS.

Combinational Circuit

Combinational circuit is a circuit in which we combine the different gates in the

circuit, for example encoder, decoder, multiplexer and demultiplexer. Some of the

characteristics of combinational circuits are following −

● The output of combinational circuit at any instant of time, depends

only on the levels present at input terminals.

● The combinational circuit do not use any memory. The previous state

of input does not have any effect on the present state of the circuit.

● A combinational circuit can have an n number of inputs and m number

of outputs.

What is an Adder?
An adder is a digital logic circuit in electronics that is extensively used for

the addition of numbers.

Half Adder
● The input variables designate the augend and addend bits; the output variables
produce the sum and carry. We assign symbols x and y to the two inputs and S (for
sum) and C (for carry) to the outputs.

The truth table and logic diagram is as follows:

*You can use Kmap also to find equations of sum and carry.
Full Adder
● A full adder is a combinational circuit that forms the arithmetic sum of three bits. It
consists of three inputs and two outputs.
● Two of the input variables, denoted by x and y , represent the two significant bits to
be added. The third input, z , represents the carry from the previous lower significant
position.
● The two outputs are designated by the symbols S for sum and C for carry.

Truth Table

K -Map for finding equations:

Logic Diagram:

Implementation of full adder using two half adders:

Binary Adder

● A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output
carry from each full adder connected to the input carry of the next full adder in the
chain.

Working:
● The augend bits of A and the addend bits of B are designated by subscript numbers
from right to left, with subscript 0 denoting the least significant bit. The carries are
connected in a chain through the full adders. The input carry to the adder is C0, and it
ripples through the full adders to the output carry C4. The S outputs generate the
required sum bits.

Example

● The bits are added with full adders, starting from the least significant position
(subscript 0), to form the sum bit and carry bit.
● The input carry C0 in the least significant position must be 0. The value of Ci+1 in a
given significant position is the output carry of the full adder.
● This value is transferred into the input carry of the full adder that adds the bits one
higher significant position to the left.
● The sum bits are thus generated starting from the rightmost position and are
available as soon as the corresponding previous carry bit is generated. All the carries
must be generated for the correct sum bits to appear at the outputs.
Block Diagram

*Carry Propagation and Carry lookahead generator - Refer book if required

Half Subtractor
● Half subtractor is a combination circuit with two inputs and two outputs
which is difference and borrow. It produces the difference between the
two binary bits at the input and also produces an output (Borrow) to
indicate if a 1 has been borrowed. In the subtraction (A-B), A is called a
Minuend bit and B is called as Subtrahend bit.

Truth Table

Equations can be found using K-map:

D= A EX-OR B
Borrow = A’B
Full Subtractor
● A full subtractor is a combinational circuit that performs subtraction of
two bits, one is minuend and other is subtrahend, taking into account
borrow of the previous adjacent lower minuend bit. This circuit has
three inputs and two outputs.

K-Map
Logic Diagram

*You can use the diagram I have given in video also

Binary Subtractor

● The subtraction of unsigned binary numbers can be done most

conveniently by means of complements.
● A - B can be done by taking the 2’s complement of B and adding it to A .
● The 2’s complement can be obtained by taking the 1’s complement and
adding 1 to the least significant pair of bits.
● The 1’s complement can be implemented with inverters, and a 1 can be
added to the sum through the input carry.

Explanation of the circuit:

● The addition and subtraction operations can be combined into one

circuit with one common binary adder by including an exclusive-OR
gate with each full adder.

● Mode M=0 —> Adder ; M=1—> Subtractor

Overflow Condition

❖ When two numbers with n digits each are added and the sum is a
number occupying n + 1 digits, we say that an overflow occurred.
❖ This is true for binary or decimal numbers, signed or unsigned.
❖ Overflow is a problem in digital computers because the number of bits
that hold the number is finite and a result that contains n + 1 bits cannot
be accommodated by an n -bit word.
❖ The detection of an overflow after the addition of two binary numbers
depends on whether the numbers are considered to be signed or
unsigned.
❖ When two unsigned numbers are added, an overflow is detected from
the end carry out of the most significant position.
❖ In the case of signed numbers, two details are important: the leftmost bit
always represents the sign, and negative numbers are in
2’s-complement form. When two signed numbers are added, the sign bit
is treated as part of the number and the end carry does not indicate an
overflow.

Example addition:

Since the sum of the two numbers is +150, it exceeds the capacity of an
eight-bit register.

● If the two carries are applied to an exclusive-OR gate, an overflow is

detected when the output of the gate is equal to 1.
Decimal Adder
BCD Adder
● BCD stands for binary coded decimal. It is used to perform the addition
of BCD numbers. A BCD digit can have any of ten possible four-bit
representations. Suppose, we have two 4-bit numbers A and B. The
value of A and B can vary from 0(0000 in binary) to 9(1001 in binary)
because we are considering decimal numbers.

● In examining the contents of the table, it becomes apparent that when

the binary sum is equal to or less than 1001, the corresponding BCD
number is identical, and therefore no conversion is needed.
● When the binary sum is greater than 1001, we obtain an invalid BCD
representation. The addition of binary 6 (0110) to the binary sum
converts it to the correct BCD representation and also produces an
output carry as required.
Block Diagram

Working:
● The two decimal digits, together with the input carry, are first added in
the top four-bit adder to produce the binary sum.
● When the output carry is equal to 0, nothing is added to the binary sum.
● When it is equal to 1, binary 0110 is added to the binary sum through
the bottom four-bit adder.
● The output carry generated from the bottom adder can be ignored,
since it supplies information already available at the output carry
terminal.
Magnitude Comparator
● A magnitude comparator is a combinational circuit that compares two
numbers A and B and determines their relative magnitudes. The
outcome of the comparison is specified by three binary variables that
indicate whether A > B, A = B, or A < B.

Algorithm:

● To determine whether A is greater or less than B , we inspect the

relative magnitudes of pairs of significant digits, starting from the most
significant position.
● If the two digits of a pair are equal, we compare the next lower
significant pair of digits. The comparison continues until a pair of
unequal digits is reached.
● If the corresponding digit of A is 1 and that of B is 0, we conclude that A
> B.
● If the corresponding digit of A is 0 and that of B is 1, we have A < B.
Equations:
Circuit:
Decoders:
● A decoder is a combinational circuit that converts binary information
from n input lines to a maximum of 2n unique output lines.
● If the n -bit coded information has unused combinations, the decoder
may have fewer than 2n outputs.
● The decoders presented here are called n -to- m -line decoders.

Example 3 to 8 line decoder

● The three inputs are decoded into eight outputs, each representing one
of the minterms of the three input variables.
● The three inverters provide the complement of the inputs, and each one
of the eight AND gates generates one of the minterms.
● A particular application of this decoder is binary-to-octal conversion.
● The input variables represent a binary number, and the outputs
represent the eight digits of a number in the octal number system

Circuit Diagram:
 ● For each possible input combination, there are seven outputs that are
equal to 0 and only one that is equal to 1. The output whose value is
equal to 1 represents the minterm equivalent of the binary number
currently available in the input lines

Use of Enable inputs:

Example: 2 to 4 line with enable input

● The circuit operates with complemented outputs and a complement

enable input.
● The decoder is enabled when E is equal to 0 (i.e., active-low enable).
● As indicated by the truth table, only one output can be equal to 0 at any
given time; all other outputs are equal to 1.
● The output whose value is equal to 0 represents the minterm selected
by inputs A and B .
● The circuit is disabled when E is equal to 1, regardless of the values of
the other two inputs.
● When the circuit is disabled, none of the outputs are equal to 0 and
none of the minterms are selected.
Combinational Logic Implementation
● From the truth table of the full adder (see Table in full adder ), we obtain
the functions for the combinational circuit in sum-of-minterms form:

Implementation of full adder with decoder

Encoders:
● An encoder is a digital circuit that performs the inverse operation of a
decoder. An encoder has 2 n (or fewer) input lines and n output lines.
● The output lines, as an aggregate, generate the binary code
corresponding to the input value. An example of an encoder is the
octal-to-binary encoder whose truth table is given below:

The boolean functions are as follows:

Error in encoder:
● If two inputs are active simultaneously, the output produces an
undefined combination. For example, if D3 and D6 are 1 simultaneously,
the output of the encoder will be 111 because all three outputs are equal
to 1.

Solution for this: Priority encoder

● A priority encoder is an encoder circuit that includes the priority function.
The operation of the priority encoder is such that if two or more inputs
are equal to 1 at the same time, the input having the highest priority will
take precedence.
Truth table is follows:

Working:
● The higher the subscript number, the higher the priority of the input.
Input D3 has the highest priority, so, regardless of the values of the
other inputs, when this input is 1, the output for xy is 11.
● The output is 10 if D2 = 1, provided that D3 = 0, regardless of the
values of the other two lower priority inputs.

K-Map:
Final equations and logic diagram:
Multiplexers:
● A multiplexer is a combinational circuit that selects binary information
from one of many input lines and directs it to a single output line.
● The selection of a particular input line is controlled by a set of selection
lines.
● There are 2n input lines and n selection lines whose bit combinations
determine which input is selected.

2:1 Mux

● It connects one of two 1-bit sources to a common destination.

● The circuit has two data input lines, one output line, and one selection
line S .
● When S = 0, the upper AND gate is enabled and I 0 has a path to the
output.
● When S = 1, the lower AND gate is enabled and I 1 has a path to the
output.
● The multiplexer acts like an electronic switch that selects one of two
sources.

4:1 Line Multiplexer

Truth table
From Truth table, we can directly write the Boolean function for output, Y as

Block Diagram:

Logic Diagram

Boolean Function Implementation using MUX

F (A, B, C, D) = (1, 3, 4, 11, 12, 13, 14, 15)

● This function is implemented with a multiplexer with three selection

inputs.A must be connected to selection input S 2 so that A , B, and C
correspond to selection inputs S2, S1, and S0, respectively.The values
 for the data inputs are determined from the truth table listed in the
figure.
● The corresponding data line number is determined from the binary
combination of ABC . For example, the table shows that when ABC =
101, F = D, so the input variable D is applied to data input 5.
Demultiplexer
● The data distributor, known more commonly as the demultiplexer or
“Demux” for short, is the exact opposite of the Multiplexer we saw in
the previous tutorial.
● The demultiplexer takes one single input data line and then switches
it to any one of a number of individual output lines one at a time. The
demultiplexer converts a serial data signal at the input to a parallel
data at its output lines as shown below.

1-to-4 Channel De-multiplexer