Chapter 3: Combinational logic

 Learning Outcomes
 At the end of the lecture, students should recall;

 Adders
 Main objectives of circuit design:
 Sub tractors
(i) Reduce Cost
 Comparators
 reduce number of gates (for SSI circuits)
 Multiplexers
 reduce IC packages (for complex circuits)
(ii) increase speed
 De multiplexers
(iii) design simplicity (reuse blocks where possible  Encoders
 Decoders
 Binary BCD – 7-Segments

 Finally, we should know the over all functions of combinational logic circuit.
Cont.

Introduction:

 The digital system consists of two types of Logic circuits, namely

 Combinational Logic Circuits (Circuits without a memory): In this type of logic circuits outputs depend only
on the current inputs.
 Logic gate is the most basic building block of combinational logic.

 Sequential Logic Circuits (Circuits with memory): In this type of logic circuits outputs depend on the current
inputs and previous inputs. These circuits employ storage elements and logic gates.
 A combinational logic circuit performs an operation assigned logically by a Boolean expression or truth
Cont.
 A combinational circuits consists of input variables ,logic gates, and output variables.

 Both the input and output signals are of two possible states ,logic 1 and 0.

 For n number of input variables to a combinational circuit ,possible combinations of binary inputs states are
possible.

 For each possible combination ,there is one and only one possible output combination.

 A combinational logic circuit can be described by mBoolean functions and each output can be expressed in terms
of n input variables.
Cont.
 Design Procedure:
 Any combinational circuit can be designed by the following steps of design procedure.

1) The problem is stated.

2) Identify(specify) the number of input and number of required output variables.

3) The input and output variables are assigned letter symbols.

4) Construct of a truth table to meet input-output requirements.

5) Writing Boolean expressions for various output variables in terms of input variables.

6) The simplified Boolean expression is obtained by any method of minimization, Boolean algebraic
method ,K-map method.

7) A logic diagram is realized from the simplified Boolean expression using logic gates.
Cont.

 Combinational Logic Circuit:

Combinational Logic Circuit

Arithmetic & Logic Functions Data Transmission Code Converters

 Multiplexers
 Adders  De multiplexers
Binary BCD-7- Segment
 Sub tractors  Encoders
 Comparators  Decoders

 Q1.what mean by combinational Logic ? & what mean by combinational Logic Circuits?

 Q2.how can we implementing Combinational Logic? & what mean by universal property of NAND &NOR -gates
Cont…
 Adders

 Digital computers perform a variety of information processing tasks. Among the basic functions encountered
are the various arithmetic operations (addition).

 Q1.what is the advantages of Adders ?

Cont…
 Arithmetic circuits -Basic Building Blocks:

 The combinational logic building blocks that can be used to perform addition and subtraction operations on
binary numbers.

 Half-Adder:

 A half –adder is a combinational circuit that can be used to add two bits.it has two inputs that represent the
two bits to be added and two outputs ,with one producing the Sum output and the other producing the Carry.

A Sum
Half-Adder
B Carry

Block schematic of Half -Adder

Cont…
 The truth table of a half-adder, showing all possible input combinations and the corresponding outputs are shown
below.

K-map simplification for carry and sum:

Cont…
 The Boolean expressions for the SUM and CARRY outputs are given by the equations,

 The first one representing the SUM output is that of an EX-OR gate, the second one representing the CARRY
output is that of an AND gate.

 The logic diagram of the half adder is,

Logic Implementation of Half-adder

Cont…
Full -Adder :

 A full adder is a combinational circuit that forms the arithmetic sum of three input bits. and it consists of 3
inputs,and 2 outputs, .

 Two of the input variables, represent the significant bits to be added. The third input represents the carry from
previous lower significant position. The block diagram of full adder is given by,

Block schematic of full-adder

 The full adder circuit overcomes the limitation of the half-adder, which can be used to add two bits only.
Cont…
 As there are three input variables, eight different input combinations are possible. The truth table is shown
below,

Truth Table:

 To derive the simplified Boolean expression from the truth table, the Karnaugh map ( K-map) method is
adopted as,
Cont…
 K-map method:

 The Boolean expressions for the SUM and CARRY outputs are given by the equations,
Cont…
 From Boolean expression analysis becomes as follows:

Implementation of full adder with two half-adders and an OR gate

Cont…
 Subtractor
 Digital computers perform a variety of information processing tasks. Among the basic functions encountered are
the various arithmetic operations (Subtraction).

Binary Arithmetic
2.Subtraction:The rules of subtractions are:

 Q2.what is advantages of Subtractors?

Cont…
 Half -Subtractor:
 A Half-Subtractor is a combinational circuit that can be used to subtract one binary digit from another to produce
a Difference output and a Borrow output.

 The Borrow output here specifies whether a ‗1‘ has been borrowed to perform the subtraction.

Block Schematic of Half-Subtractor

 The truth table of Half-Subtractor, showing all possible input combinations and the corresponding outputs are
shown below.
Cont…
 Truth table:

K-map simplification for half subtraction

 The Boolean expressions for the Difference and Borrow

outputs are given by the equations,

Cont…
 The first one representing the Difference (D) output is that of an exclusive-OR gate, the expression for the Borrow
output (Bout) is that of an AND gate with input A complemented before it is fed to the gate.

 The logic diagram of the half adder is,

Logic Implementation of Half-Subtractor

Cont…
Comparing a half-subtractorwith a half-adder,

 we find that the expressions for the SUM and Differenceoutputs are just the same. The expression for Borrowin
the case of the half-subtractor is also similar to what we have for CARRY in the case of the half-adder.

 If the input A, i.e.., the minuend is complemented, an AND gate can be used to implement the Borrowoutput.

 Full Subtractor:

 A full subtractorperforms subtraction operation on two bits, a minuend and a subtrahend, and also takes into
consideration whether a ‗1‘ has already been borrowed by the previous adjacent lower minuendbitor not.

 As a result, there are three bits to be handled at the input of a full subtractor, namely the two bits to be subtracted
and a borrow bit designated as .
Cont…
 There are two outputs, namely the Difference output D and the Borrow output Bo. The Borrow output bit tells
whether the minuend bit needs to borrow a ‗1‘ from the next possible higher minuend bit.

Block Schematic of Full-Subtractor

Cont…
 The truth table for full-subtractor is,

 K-map simplification for full-subtractor:

Cont…
 The Boolean expressions for the Difference and Borrow outputs are given by the equations,

Difference, D = A’B’+ A’B + AB’ + ABBin

Borrow, Bout = A’B+ A’+ B

 The logic diagram for the above functions is shown as,

Implementation of full subtractors in sum of product

Cont.
 The logic diagram of the full-subtractor can also be implemented with two half subtractors and one OR gate.

 The difference,Doutput from the second half subtractoris the exclusive-OR of and the output of the first half-
subtractor, giving

 Difference,D= (A ⊕B) [x y = x‘y+ xy‘]

Bin (A‘B+AB‘)

(A‘B+AB‘) + (A‘B+AB‘)‘ [(x‘y+xy‘)‘= (xy+x‘y‘)]

(A‘B+AB‘) + (AB+A‘B‘)

A‘B+ AB‘ + AB + A‘B‘

Difference,DA‘B+ AB‘ + AB + A‘B‘

The Borrow output is shown below,

Cont.
and the borrow output is shown below:
 Borrow, = A’B+ Bin (A’B+AB’)’ [(x’y+xy’)‘= (xy+x’y’)]
A‘B+ Bin (AB+A‘B‘)
A‘B+ ABBin+ A‘B‘Bin
A‘B (+1) + AB+ A‘B‘ [+1= 1]
A‘B+ A‘B+ AB+ A‘B‘
A‘B+ B(A+A‘) + A‘B‘ [A+A‘= 1]
A‘B+ B+ A‘B‘
A‘B (+1) + B+ A‘B‘ [+1= 1]
A‘B+ A‘B+ B+ A‘B‘
A‘B+ B+ A‘ (B +B‘)

Borrow, A‘B+ B+ A‘.

Cont.
 Therefore, we can implement full-subtractor using two half-subtractors and OR gate as,
Cont…
 Binary Adder (Parallel Adder):

 The 4-bit binary adder using full adder circuits is capable of adding numbers resulting in a 4-bit sum and a carry
output as shown in figure below. two 4-bit .

4-bit binary parallel Adder

 Since all the bits of augend and addend are fed into the adder circuits simultaneously and the additions in each
position are taking place at the same time, this circuit is known as parallel adder.
Cont…
 Let the 4-bit words to be added be represented by,

A3A2A1A0= 1111 and B3B2B1B0= 0011.

Significant places 4 3 2 1
Input carry 1 1 1 0
Augend word A 1 1 1 1
Addend word B 0 0 1 1
10 0 1 0 Sum
output Carry

 The bits are added with full adders, starting from the least significant position, to form the sum it and carry bit.

 The input carry in the least significant position must be 0.

 The carry output of the lower order stage is connected to the carry input of the next higher order stage. Hence
Cont…

 In the least significant stage, , and (which is 0) are added resulting in sum and carry .

 This carry becomes the carry input to the second stage. Similarly in the second stage, A1, B1 and C1 are added
resulting in sum S1 and carry are added resulting in sum and carry ,

 in the third stage, , and are added resulting in sum and , which is the output carry.

 Thus the circuit results in a sum () and a carry output ().

 Parallel adders can be placed in to two categories based on the way in which the internal carries from
stage to stage are handled.

1. Ripple carry adder

2. Look-ahead carry adder
Cont…
 Externally, both types of adders are the same in terms of inputs and outputs.

 The difference is the speed at which they can add numbers.

 The look-ahead carry adder is much faster than ripple carry adder.

 Though the parallel binary adder is said to generate its output immediately after the inputs are applied, its speed of
operation is limited by the carry propagation delay through all stages.

 However, there are several methods to reduce this delay. One of the methods of speeding up this process is look-
ahead carry adder which eliminates the ripple-carry delay.
Cont.
 Ripple Carry Adder:

 In ripple carry adder, the second full adder (FA2) needs to wait for the input carry (), coming from the output
carry () from first adder (FA1).

 Assume one adder has a delay of 8 ns. 4 adders will contribute to 32 ns delay in adding up the 4 bits number .
Cont.
 Look-Ahead Carry Adder :

 The objective of the adder is to reduce the adder’s delay in performing the addition. This is because, the input
carry and output carry is dependent on the input’s value of the adder itself.

 No propagation delay from one adder to the other.

Cont.
 The method of speeding up this process by eliminating inter stage carry delay is called look ahead-carry addition.

 This method utilizes logic gates to look at the lower order bits of the augend and addend to see if a higher-order
carry is to be generated. It uses two functions: carry generate and carry propagate.

Full-Adder circuit
Cont.
 Consider the circuit of the full-adder shown above. Here we define two functions: carry generate () and carry
propagate () as,

 Carry generate, = Ai ⊕Bi

 Carry propagate, = Ai ⊕Bi

the output sum and carry can be expressed as,
 =
 =⊕

 (carry generate), it produces a carry 1 when both and are 1, regardless of the input carry .

 Pi(carry propagate) because it is the term associated with the propagation of the carry from to .

 The Boolean functions for the carry outputs of each stage and substitute for each its value from the previous
equation:
• = input carry
Cont.

=+

= + = + (+ )

= +

++

= + = + (+ +)

=+ ++

 Since the Boolean function for each output carry is expressed in sum of products, each function can be
implemented with one level of AND gates followed by an ORgate.

 The three Boolean functions for C1, C2 and C3 are implemented in the carry look-ahead generator as shown
below.

 Note that C3 does not have to wait for C2 and C1to propagate; in fact C3 is propagated at the same time as C1 and
Cont.
 Carry Look a head generator logic diagram:

Logic diagram of Carry Look-ahead Generator

Cont.
 Using a Look-ahead Generator we can easily construct a 4-bit parallel adder with a Look-ahead carry scheme.
Each sum output requires two exclusive-OR gates.

 The output of the first exclusive-OR gate generates the Pi variable, and the AND gate generates the Gi variable.

 The carries are propagated through the carry look-ahead generator and applied as inputs to the second exclusive-
OR gate.

 All output carries are generated after a delay through two levels of gates.

 Thus, outputs S1 through S3 have equal propagation delay times.

Cont.
 Here is 4- bit adder with Carry Look –ahead:

4-Bit Adder with Carry Look-ahead

Cont.
Binary Subtractor (Parallel Subtractor):

 The subtraction of unsigned binary numbers can be done most conveniently by means of complements.

 The subtraction A-B can be done by taking the 2‘scomplement of B and adding it to A.

 The 2‘s complement can be obtained by taking the 1‘s complement and adding 1 to the least significant pair of bits.

 The 1‘s complement can be implemented with inverters and a 1 can be added to the sum through the input carry.

 The circuit for subtracting A-B consists of an adder with invertersplaced between each data input B and the
corresponding input of the full adder.

 The input carry must be equal to 1when performing subtraction.

 The operation thus performed becomes A, plus the 1‘s complement of B, plus1. This is equal to A plus the 2‘s
complement of B.
Cont.

 Please try to do the analysis for 4 –bit parallel Subtractor

Cont.
 Comparators :

 A magnitude comparator is a combinational circuit that compares two given numbers (A and B) and determines
whether one is equal to, less than or greater than the other. The output is in the form of three binary variables
representing the conditions A = B, A>B and A<B, if A and B are the two numbers being compared.

 Comparator is a device that compares two digital quantities to determine the relationship of those quantities.

 Comparison is made in terms of:

 Equal to ‘=’
 Less than ‘<’
 Greater than ‘>’

 The function of a comparator is to compare either the input bit is the same as the reference bit or not.

 It can be a 1-bit, 2-bit or 4-bit comparator.

Cont.
 Here is block diagram of magnitude comparator

Block diagram of magnitude comparator

 For comparison of two n-bit numbers, the classical method to achieve the Boolean expressions requires a truth
table of entries and becomes too lengthy and cumbersome.
Cont.
 1 bit comparator
 Design a combinational logic circuit that compares two 1-bit numbers
A B A AB A
0 0 1 0 0
0 1 0 0 1
1 0 0 1 0
1 1 1 0 0

comparator :
 1 -bit comparator 2 variables 4 rows
 2 -bit comparators 4 variables 16 rows
 n- bit comparators 2n variables rows
Cont.
 2-bit Magnitude Comparator:
 The truth table of 2-bit comparator is given in table below—Truth table:
Cont.
 K-map Simplification:
Cont.

 Logic Diagram:
Cont.
 Logic Diagram:

2- bit Magnitude Comparator

Exercise :-Design a combinational logic circuit that compares two 4-bit numbers (A&B)
Cont.
 Multiplexers

 A Multiplexers (MUX) is a combinational logic circuitsthat has several inputs and only one output.

 Multiplexer means transmitting a large number of information units over a small number of channels or lines.

 MUXdirects one of the inputs to its output line by using a control bit word (selection line) to its select lines.

 Generally ,Multiplexer means many to oneand Multiplexer contains the followings:

o data inputs

o selection inputs

o a singleoutput

 Selection input determines the input that should be connected to the output.

 The multiplexersometime is called data selector.

 The multiplexer acts like an electronic switch that selects one from different input lines .
Cont.
 Multiplexer as multi-position or rotary switch
 The basic operation is controlled by a selector
lines

Logic Symbol for multiplexer

 Multiplexer are also called as Data Selector or router because it accepts several data inputs and allows only
one of them to get through to the output at a time.
 As multiplexer selects one out of many, it is often called as to 1 line converter.
Cont.
 Types of multiplexer

Logic symbols of 2 to 1 and 4 to 1 multiplexers Logic symbols of 8 to 1 and 16 to 1 multiplexers

Cont.
 2 to 1 multiplexer

Logic symbol, function table of 2 to 1

Logic diagram of 2 to 1 Multiplexer
Multiplexer

 The 2 to 1 multiplexer can be implemented using two AND gates and one OR. The Not gate provides
complemented and un-complemented form of S0 i.e. select line. The interconnections are made to AND gate to
provide the necessary product term.
Cont.

 4 to 1 multiplexer
 The second type of multiplexer is 4 to 1 multiplexer.

 For 4 to 1 multiplexer, two bit binary code on select inputs (S1S0) allows the data from selected input (either from
D0,D1,D2,D3) to pass to the output.

 The output Y receives D0 only when S1=0 and S0=0. Similarly, output Y receives D1 only when S1S0=01. Output
Y receives D2 only when S1S0=10. Output Y receives D3 only when S1S0=11.

 Logic symbol, Function table and Boolean

expression for 4- to -1 multiplexer
Cont.
 From the function table, the Boolean Expression can be written in SOP form. Each row of the function table
provides the product term.

 Referring to the Boolean expression, it is possible to draw the logic circuit consisting of a OR gate with 4 inputs.
Each product term is represented by three input AND gate.

 One of the input of AND gate is the respective data input. The Select lines S1 and S0 along with inverter provide
select input either in un-complemented or complemented form. The data inputs and select lines are connected to
the AND gates as per the requirement of the product term to generate the desired output.
Cont.

 The first AND gate receives D0, S1’ and S0’ as inputs. Similarly rest of the AND gates receives the appropriate
inputs as per the product term.
Cont.

 In many situations, an enable or gating input is added to the multiplexer. The multiplexer will be enables
operative only when the Enable input is active. In this case Enable is active high.

 When E=0, Multiplexer function is disabled.

 To enable multiplexer, E must be set to ‘1’ as shown in fig below.

Multiplexer with Enable input

Cont.
 Cascading multiplexer
 As number of inputs to the multiplexers is limited say up to 16. To meet the larger input needs of multiplexers,
smaller multiplexers can cascaded together for further expansion.

 This method of expansion of multiplexers is also known as tree multiplexing. Higher order multiplexers can be
constructed by using lower order multiplexers as shown fig below:

 Construction of 4 to 1 multiplexer using two 2- to 1 -multiplexer.

Cont.
 Construction of 8 -to -1 multiplexer

 Construction of 8 -to -1 multiplexer using two 4x1 and one 2x1 multiplexer
Cont.
 Applications of multiplexers

 Multiplexer or data selectors are combinational circuits which transfer data from many sources to single output
under the control of data select lines.

 A list of popular applications is given below.

1. Data routing 5. Parallel to serial converter

2. Data bussing 6. Cable TV signal distribution
3. Switch setting comparator 7. Telephone network
4. Multiplexer as a function generator 8. Sharing printer /resources

 #Q1.Discuss briefly how the above list of the popular application is Multiplexer applications?

 How can we do implementation of minterm Boolean expression?

Cont.
 DE multiplexer

 DE multiplexer has a single input and n output lines. DE multiplexer can be visualized as reverse multi-position
switch.

 The select lines permit input data from single line to be switched to any one of the many output lines as shown in
fig below.

 DE multiplex means one into many.

 A DE multiplexer reverses the multiplexing operation.
 =n
 It also has ‘m’ select lines for selecting the desired output for the input data

Multi-position switch as DE multiplexer

Cont.
 The mathematical relation between select lines and ‘n’output are:
 =n

Logic symbol of basic de multiplexer

 As a DE multiplexer takes data from one input line and distributes over a output line, hence it is often referred to
as 1 to line converter. 1. 1 to 2 DE multiplexer
2. 1 to 4 DE multiplexer,
 There are four basic types DE multiplexers:
3. 1 to 8 DE multiplexer and
4. 1 to 16 DE multiplexer
Cont.
 Types of DE multiplexer

Types of DE multiplexer with Logic Symbol

Cont.
 A 1-to -2 DE multiplexer

Logic symbol and function table of a 1 to 2 DE multiplexer

 As shown in fig above, in 1 to 2 DE multiplexer, with S0=0 the Y0 output of DE multiplexer receive the input
data.

 Similarly when S0 becomes ‘1’, the Y1 output of DE multiplexer receives the input data.

 Thus the Select or control line selects the desired output to which the input data is transferred or distributed.
Hence, DE multiplexer is also known as data distributor.
Cont.
 To distribute the input data D to Y0, the select input So should be 0 and Y1 will receive data input D when So=1.
The Boolean expressions for the outputs are

 The implementation of 1 to 2 DE multiplexer requires two 2 input AND gate and a NOT gate as shown in fig.
below. The product term for the output decides the interconnections between the gates data input and select lines.

Logic diagram for 1 to 2 DE

multiplexer
Cont.
 A 1 to 4 DE multiplexer

Logic symbol and function table of a 1 to 4 DE

multiplexer
 Fig. in shown above indicates the logic symbol and function table of 1 to 4 DE multiplexer. In 1 to 4 DE
multiplexer, the input data can be distributed to 1 of the 4 outputs.

 Selection of the output is decided by the binary word applied to the select lines. With S1S0=00, the Y0 output of
DE multiplexer receive the input data. For S1S0=01, the output Y1 receives the input data.
Cont.
 With S1S0=10, the input data is distributed to Y2 and when S1S0=11, the output Y3 receives the input data.

 The Boolean expressions for the outputs are:

Logic diagram for 1 to 4 DE multiplexer

 The implementation of 1 to 4 DE multiplexer requires four 3 input AND gates and two NOT gates as shown in
the above fig.

 The product term for the output decides the interconnections between the gates data input and select lines.
Cont.
 Applications of DE multiplexers

 Digital DE multiplexers are combinational devices controlled by a selector address that routes input data to one
of many outputs of the DE multiplexers.

 DE multiplexer can be used as a decoder.

 These can be used in following applications.

1. Data DE multiplexing
2. Clock DE multiplexing
3. Memory addressing
4. Four phase clock generator
5. Function generation using DMUX
6. Switch encoding
7. Serial to parallel converter
Cont.
Encoders

 An encoder is a digital circuit that performs the inverse operation of a decoder.

 An encoder has (or fewer) input lines and output lines.

 The encoder can be implemented with OR gate whose inputs are determined directly from the truth table
Cont.
 Output is equal to 1 when the input digit is 4, 5, 6 or 7.

 Output is equal to 1 when the input digit is 2, 3, 6 or 7.

 Output is equal to 1 when the input digit is 1, 3, 5 or 7.

 We need three OR gates.

Cont.
 Decoder

 A decoder is a combinational circuit that converts binary information from n inputs lines to a maximum of
unique output lines. If the n-bit decoded information has unused or don’t care combinations.

 The decoder output will have fewer than Outputs.

 The decoders presented here are called n-to-m line decoders, where their purpose is to generate the (or fewer)
minterms of n input variables.

 The name de-coder is also used in conjunction with some code converters such as a BCD –to Seven Segment
decoder.

 As an example ,consider the 3-to -8 linedecoder circuit of fig.shown below. Three inputs are decoded into eight
outputs, each output representing one of the minterms of the 3-input variables. The three inverters provide the
complement of the inputs, and each one of the eight AND gates generates one of the minterms.

 A particular application of this decoder would be a binary –to-octal conversion.

Cont.
 Truth Table of a 3-to -8 line Decoder

Inputs Outputs
X Y Z
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

 However, a 3-to -8 line decoder can be used for decoding any 3 bit code to provide eight outputs, one for each elements of the
code.

 The output line whose value is equal to 1 represents the minterm equivalent of the binary number presently available in the
Cont.

 The input variables may represent a binary number, and the outputs will then represent the eight digits in the
octal number system.
 A 3-line to-8 line decoder

Logic Implementation of A 3-to -8 line Decoder

Cont.
Combinational logic implementation

 A decoder provides the minterms of ninput variables. Since any Boolean function can be expressed in sum of
minterms canonical form, one can use a decoder to generate the minterms and an externalORgate to form the
sum.

 In this way ,any combinational circuit with n inputs and m outputs can be implemented with an n-to - line decoder
and m OR gates.

 The procedure for implementing a combinational circuit by means of a decoder and OR gates requires that the
Boolean functions for the circuit be expressed in sum of minterms.

 This form can be easily obtained from the truth table or by expanding the functions to their sum of minterms.

 A decoder is chosen that generates all the minterms of the n input variables.

 The inputs of each OR gate are selected from the decoder outputs according to the minterm list in each function.
Cont.
 Example :-Implement a full adder circuit with a decoder and two OR gates. From the truth table of the full
adder ,we obtain the functions for this combinational circuit in sum of minterms:

 Since there are three inputs and a total of eight minterms ,we need a 3-to -8 line decoder. The implementation is
shown in fig below. The decoder generates the eight minterms of X,Y,Z.

Implementation of a Full Adder with a Decoder

Cont.
 Code Converter :
 The Gray Code is unweighted and is not an arithmetic code: that is ,there are no specific weights assigned to the
bit positions.

 The important feature of the Gray Code is that it exhibits only a single bit change from one code word to the next
in sequence.

 This property is important in many applications ,such as shaft position encoders, where error susceptibility
increases with the number of bit changes between adjacent numbers in a sequence.
Cont.

 To convert a binary number to a Gray Code number, the following rules apply.

1. The most significant digit (Lefit Most Bit) in the Gray Code is the same as the Corresponding digit in the binary
number.

2. Going from left to right ,add each adjacent pair of binary digits to get the next Gray code digit, regardless
carries.

For instance -let us convert the binary number 1010 to Gray Code.

Step 1:-the left most Gray digit is the same as the left most binary .

1 0 1 0 Binary

1 Gray
Cont.
 Step 2:- Add the left most binary digits to the adjacent one.

1 + 0 1 0 Binary

1 1 Gray

 Step 3:Add the next adjacent pair

1 0 + 1 0 Binary

1 1 1 Gray

 Step 4:-Add the last adjacent pair.

1 1 1 + 0 Binary
 The conversion is now completes and the Gray Code is 1111
1 1 1 1 Gray
Cont.

 Steps to design the converter

1. Design a converter by the following procedures:

a. Write down the truth table of both input and output converter.

b. Apply K-map to look for the minimized logic output bits.

c. Implement the logic gates by using Circuit Maker.

 Example:

 For Binary to Gray Code Converter ,binary bits are inputs and gray code bits are output.so first write the truth
table for binary bits and gray code.

 Then K-map for all bits of gray code ,find the simplified expression for each bit of gray code.

 Then design the logical circuit.

Cont.
 Truth Table:
Binary-Inputs Gray Code -Outputs
Decimal A B C D Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 1
3 0 0 1 1 0 0 1 0

4 0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
5
0 1 1 0 0 1 0 1
6
0 1 1 1 0 1 0 0
7
1 0 0 0 1 1 0 0
8
1 0 0 1 1 1 0 1
9
1 0 1 0 1 1 1 1
10
1 0 1 1 1 1 1 0
11
1 1 0 0 1 0 1 0
12 1 1 0 1 1 0 1 1
13 1 1 1 0 1 0 0 1
14 1 1 1 1 1 0 0 0
15
Cont.
 K-map for each bit of Gray Code
 For practical consideration code conversions are made for each bit.

For the K-map can draw as follows. For the K-map can draw as follows.
Cont.

For the K-map can draw as follows. For the K-map can draw as follows.
Cont.
 The over all logic circuit implementation becomes as follows:

Design the converter for:-

1. Binary to BCD
2. BCD to Gray
3. BCD to Binary
4. BCD to Excess
5. Gray to Binary

Figure: For Binary –to –Gray Code

Cont.

 Gray to Binary Converter

K-map For
Cont.
 K-map For K-map For
Cont.
 K-map For

Logic Circuit Implementation For Gray to Binary Converter

Cont.
 BCD-to -7 Segment Converter /Decoder
Cont.
 Quiz :

1. Write the basic logics gates and explain their operation principle?(2%)

2. Why we use logic simplification in digital logic design ?(3%)

3. From the given minterm notation determine the corresponding Boolean expression and try to simplify the
expression using simplification mechanism ?(5%)

F(X,Y,Z)=Σ(1,4,5,6,7)