BIM203 Logic Design

Combinational Functions
 Overview
▪ Combinational Functions
• Functions and functional blocks
• Rudimentary logic functions
• Decoding using Decoders
▪ Implementing Combinational Functions
with Decoders
• Encoding using Encoders
• Selecting using Multiplexers
▪ Implementing Combinational Functions
with Multiplexers
BIM203 Logic Design Combinational Functions 2
 Functions and Functional Blocks
▪ The functions considered are those found to be
very useful in design
▪ Corresponding to each of the functions is a
combinational circuit implementation called a
functional block.
▪ In the past, functional blocks were packaged as
small-scale-integrated (SSI), medium-scale
integrated (MSI), and large-scale-integrated
(LSI) circuits.
▪ Today, they are often simply implemented within
a very-large-scale-integrated (VLSI) circuit.
BIM203 Logic Design Combinational Functions 3
 Rudimentary Logic Functions
▪ Functions of a single variable X
TABLE 4-1
▪ Can be used on the
Functions of One Variable
inputs to functional
blocks to implement X F=0 F=X F= X F=1

other than the block’s 0 0 0 1 1

intended function 1 0 1 0 1
V CC or V DD

1 F5 1 F5 1 X F5 X
(c)

0 F5 0 F5 0
X F5 X

(a) (b) (d)

BIM203 Logic Design Combinational Functions 4
 Multiple-bit Rudimentary Functions

▪ Multi-bit Examples:
A F3 A
3 2
1 F2 1 2 4 4 2:1 F(2:1)
F F
0 F1 0 1
0 (c)
A F0 A
(a) (b) 3
4 3,1:0 F(3), F(1:0)
▪ A wide line is used to represent F
a bus which is a vector signal (d)
▪ In (b) of the example, F = (F3, F2, F1, F0) is a bus.
▪ The bus can be split into individual bits as shown in (b)
▪ Sets of bits can be split from the bus as shown in (c)
for bits 2 and 1 of F.
▪ The sets of bits need not be continuous as shown in (d) for bits 3, 1, and
0 of F.
BIM203 Logic Design Combinational Functions 5
 Enabling Function
▪ Enabling permits an input signal to pass
through to an output
▪ Disabling blocks an input signal from passing
through to an output, replacing it with a fixed
value
▪ The value on the output when it is disable can
be Hi-Z (as for three-state buffers and
transmission gates), 0 , or 1 ENX F

▪ When disabled, 0 output (a)

▪ When disabled, 1 output
X
F
▪ See Enabling App in text EN

BIM203 Logic Design Combinational Functions (b) 6

 Decoding
▪ Decoding - the conversion of an n-bit input
code to an m-bit output code with
n  m  2n such that each valid code word
produces a unique output code
▪ Circuits that perform decoding are called
decoders
▪ Here, functional blocks for decoding are
• called n-to-m line decoders, where m  2n, and
• generate 2n (or fewer) minterms for the n input
variables
BIM203 Logic Design Combinational Functions 7
 Decoder Examples
▪ 1-to-2-Line Decoder A D0 D1
D0 A
0 1 0
1 0 1 A D1 A
▪ 2-to-4-Line Decoder (a) (b)
A0
A1 A0 D0 D1 D2 D3
A1
0 0 1 0 0 0 D0 A1A0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1 D1 A1A0

(a)
D2 A1A0
▪ Note that the 2-4-line
made up of 2 1-to-2- D3 A1A0
line decoders and 4 AND gates.
(b)
BIM203 Logic Design Combinational Functions 8
 Decoder Expansion
▪ General procedure given in book for any decoder with
n inputs and 2n outputs.
▪ This procedure builds a decoder backward from the
outputs.
▪ The output AND gates are driven by two decoders with
their numbers of inputs either equal or differing by 1.
▪ These decoders are then designed using the same
procedure until 2-to-1-line decoders are reached.
▪ The procedure can be modified to apply to decoders
with the number of outputs ≠ 2n

BIM203 Logic Design Combinational Functions 9

 Decoder Expansion - Example 1
▪ 3-to-8-line decoder
• Number of output ANDs = 8
• Number of inputs to decoders driving output ANDs = 3
• Closest possible split to equal
▪ 2-to-4-line decoder
▪ 1-to-2-line decoder
• 2-to-4-line decoder
▪ Number of output ANDs = 4
▪ Number of inputs to decoders driving output ANDs = 2
▪ Closest possible split to equal
• Two 1-to-2-line decoders

▪ See next slide for result

BIM203 Logic Design Combinational Functions 10
 Decoder Expansion - Example 1
▪ Result

BIM203 Logic Design Combinational Functions 11

 Decoder Expansion - Example 2
▪ 7-to-128-line decoder
• Number of output ANDs = 128
• Number of inputs to decoders driving output ANDs
=7
• Closest possible split to equal
▪ 4-to-16-line decoder
▪ 3-to-8-line decoder
• 4-to-16-line decoder
▪ Number of output ANDs = 16
▪ Number of inputs to decoders driving output ANDs = 2
▪ Closest possible split to equal
• 2 2-to-4-line decoders
• Complete using known 3-8 and 2-to-4 line decoders
BIM203 Logic Design Combinational Functions 12
 Decoder with Enable
▪ In general, attach m-enabling circuits to the outputs
▪ See truth table below for function
• Note use of X’s to denote both 0 and 1
• Combination containing two X’s represent four binary combinations
▪ Alternatively, can be viewed as distributing value of signal
EN
EN to 1 of 4 outputs
A 1

▪ In this case, called a

A 0
demultiplexer D 0

EN A 1 A 0 D0 D1 D2 D3 D1

0 X X 0 0 0 0
1 0 0 1 0 0 0 D2
1 0 1 0 1 0 0
1 1 0 0 0 1 0
D3
1 1 1 0 0 0 1

(a) (b)
BIM203 Logic Design Combinational Functions 13
 Combinational Logic Implementation
- Decoder and OR Gates
▪ Implement m functions of n variables with:
• Sum-of-minterms expressions
• One n-to-2n-line decoder
• m OR gates, one for each output
▪ Approach 1:
• Find the truth table for the functions
• Make a connection to the corresponding OR from
the corresponding decoder output wherever a 1
appears in the truth table
▪ Approach 2
• Find the minterms for each output function
• OR the minterms together 14
BIM203 Logic Design Combinational Functions
 Decoder and OR Gates Example
▪ Implement the following set of odd parity functions of
(A7, A6, A5, A4)
P1 = A7 + A5 + A4 A7 0 P1
P2 = A7 + A6 + A4 A6 1
2
+
P4 = A7 A6 A5 + A5 3
A 4
▪ Finding sum of 4 5 P2
6
minterms expressions 7
8
P1 = Sm(1,2,5,6,8,11,12,15) 9
P2 = Sm(1,3,4,6,8,10,13,15)
10
11
P4
P4 = Sm(2,3,4,5,8,9,14,15) 12
13
▪ Find circuit 14
15
▪ Is this a good idea?
BIM203 Logic Design Combinational Functions 15
 Encoding
▪ Encoding - the opposite of decoding - the conversion
of an m-bit input code to a n-bit output code with n 
m  2n such that each valid code word produces a
unique output code
▪ Circuits that perform encoding are called encoders
▪ An encoder has 2n (or fewer) input lines and n output
lines which generate the binary code corresponding
to the input values
▪ Typically, an encoder converts a code containing
exactly one bit that is 1 to a binary code corres-
ponding to the position in which the 1 appears.
BIM203 Logic Design Combinational Functions 16
 Encoder Example
▪ A decimal-to-BCD encoder
• Inputs: 10 bits corresponding to decimal
digits 0 through 9, (D0, …, D9)
• Outputs: 4 bits with BCD codes
• Function: If input bit Di is a 1, then the
output (A3, A2, A1, A0) is the BCD code for i,
▪ The truth table could be formed, but
alternatively, the equations for each of the
four outputs can be obtained directly.

BIM203 Logic Design Combinational Functions 17

 Encoder Example (continued)
▪ Input Di is a term in equation Aj if bit Aj is 1
in the binary value for i.
▪ Equations:
A3 = D8 + D9
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D7 + D9
▪ F1 = D6 + D7 can be extracted from A2 and A1
Is there any cost saving?
BIM203 Logic Design Combinational Functions 18
 Priority Encoder
▪ If more than one input value is 1, then the
encoder just designed does not work.
▪ One encoder that can accept all possible
combinations of input values and produce
a meaningful result is a priority encoder.
▪ Among the 1s that appear, it selects the
most significant input position (or the
least significant input position) containing
a 1 and responds with the corresponding
binary code for that position.
BIM203 Logic Design Combinational Functions 19
 Priority Encoder Example
▪ Priority encoder with 5 inputs (D4, D3, D2, D1, D0) - highest priority to
most significant 1 present - Code outputs A2, A1, A0 and V where V
indicates at least one 1 present.
No. of Min- Inputs Outputs
terms/Row D4 D3 D2 D1 D0 A2 A1 A0 V
1 0 0 0 0 0 X X X 0
1 0 0 0 0 1 0 0 0 1
2 0 0 0 1 X 0 0 1 1
4 0 0 1 X X 0 1 0 1
8 0 1 X X X 0 1 1 1
16 1 X X X X 1 0 0 1
▪ Xs in input part of table represent 0 or 1; thus table entries correspond to
product terms instead of minterms. The column on the left shows that all
32 minterms are present in the product terms in the table

BIM203 Logic Design Combinational Functions 20

 Priority Encoder Example (continued)

▪ Could use a K-map to get equations, but

can be read directly from table and
manually optimized if careful:
A2 = D4
A1 = D4 D3 + D4 D3D2 = D4F1, F1 = (D3 + D2)
A0 = D4 D3 + D4 D3 D2 D1 = D4 (D3 + D2D1)
V = D4 + F1 + D1 + D0

BIM203 Logic Design Combinational Functions 21

 Selecting
▪ Selecting of data or information is a critical
function in digital systems and computers
▪ Circuits that perform selecting have:
• A set of information inputs from which the selection
is made
• A single output
• A set of control lines for making the selection
▪ Logic circuits that perform selecting are called
multiplexers
▪ Selecting can also be done by three-state logic
or transmission gates
BIM203 Logic Design Combinational Functions 22
 Multiplexers
▪ A multiplexer selects information from an
input line and directs the information to
an output line
▪ A typical multiplexer has n control inputs
(Sn - 1, … S0) called selection inputs, 2n
information inputs (I2n - 1, … I0), and one
output Y
▪ A multiplexer can be designed to have m
information inputs with m < 2n as well as
n selection inputs
BIM203 Logic Design Combinational Functions 23
 2-to-1-Line Multiplexer
▪ Since 2 = 21, n = 1
▪ The single selection variable S has two values:
• S = 0 selects input I0
• S = 1 selects input I1
▪ The equation:
Y = S I0 + SI1
Enabling
▪ The circuit: Decoder Circuits

I0
Y
S
I1

BIM203 Logic Design Combinational Functions 24

 2-to-1-Line Multiplexer (continued)
▪ Note the regions of the multiplexer circuit shown:
• 1-to-2-line Decoder
• 2 Enabling circuits
• 2-input OR gate
▪ To obtain a basis for multiplexer expansion, we
combine the Enabling circuits and OR gate into a 2  2
AND-OR circuit:
• 1-to-2-line decoder
• 2  2 AND-OR
▪ In general, for an 2n-to-1-line multiplexer:
• n-to-2n-line decoder
• 2n  2 AND-OR

BIM203 Logic Design Combinational Functions 25

 Example: 4-to-1-line Multiplexer
▪ 2-to-22-line decoder
▪ 22  2 AND-OR
Decoder
S1

4 3 2 AND-OR
S0
Decoder
S1

S0
I0

Y
I1
Y

I2

I3

BIM203 Logic Design Combinational Functions 26

 Multiplexer Width Expansion
▪ Select “vectors of bits” instead of “bits”
▪ Use multiple copies of 2n  2 AND-OR in
parallel
▪ Example:
4-to-1-line
quad multi-
plexer

BIM203 Logic Design Combinational Functions 27

 Other Selection Implementations
▪ Three-state logic in place of AND-OR
S0
I0

I1
S1
Y
I2

I3

(b)

▪ Gate input cost = 14 compared to 22 (or

18) for gate implementation
BIM203 Logic Design Combinational Functions 28
 Combinational Logic Implementation
- Multiplexer Approach 1
▪ Implement m functions of n variables with:
• Sum-of-minterms expressions
• An m-wide 2n-to-1-line multiplexer
▪ Design:
• Find the truth table for the functions.
• In the order they appear in the truth table:
▪ Apply the function input variables to the multiplexer
inputs Sn - 1, … , S0
▪ Label the outputs of the multiplexer with the output
variables
• Value-fix the information inputs to the multiplexer
using the values from the truth table (for don’t
cares, apply either 0 or 1)
BIM203 Logic Design Combinational Functions 29
 Example: Gray to Binary Code
▪ Design a circuit to Gray Binary
ABC xyz
convert a 3-bit Gray 000 000
code to a binary code 100 001
110 010
▪ The formulation gives 010 011
the truth table on the 011 100
right 111 101
101 110
▪ It is obvious from this 001 111
table that X = C and the
Y and Z are more complex

BIM203 Logic Design Combinational Functions 30

 Gray to Binary (continued)
▪ Rearrange the table so Gray Binary
that the input combinations ABC xyz
000 000
are in counting order 001 111
010 011
▪ Functions y and z can 011 100
100 001
be implemented using 101 110
a dual 8-to-1-line 110 010
multiplexer by: 111 101
• connecting A, B, and C to the multiplexer select inputs
• placing y and z on the two multiplexer outputs
• connecting their respective truth table values to the inputs
BIM203 Logic Design Combinational Functions 31
 Gray to Binary (continued)
0 D00 0 D10
1 D01 1 D11
1 D02 1 D12
0 D03 0 D13
0 D04 1 D14
Out Y Out Z
1 D05 0 D15
1 D06 0 D16
0 D07 1 D17
A S2 A S2 8-to-1
8-to-1
B S1 B S1
MUX S0 MUX
C S0 C

▪ Note that the multiplexer with fixed inputs is identical to a

ROM with 3-bit addresses and 2-bit data!

BIM203 Logic Design Combinational Functions 32

 Combinational Logic Implementation
- Multiplexer Approach 2
▪ Implement any m functions of n + 1 variables by using:
• An m-wide 2n-to-1-line multiplexer
• A single inverter
▪ Design:
• Find the truth table for the functions.
• Based on the values of the first n variables, separate the truth
table rows into pairs
• For each pair and output, define a rudimentary function of the
final variable (0, 1, X, X)
• Using the first n variables as the index, value-fix the
information inputs to the multiplexer with the corresponding
rudimentary functions
• Use the inverter to generate the rudimentary function X

BIM203 Logic Design Combinational Functions 33

 Example: Gray to Binary Code
▪ Design a circuit to Gray Binary
ABC xyz
convert a 3-bit Gray 000 000
code to a binary code 100 001
110 010
▪ The formulation gives 010 011
the truth table on the 011 100
right 111 101
101 110
▪ It is obvious from this 001 111
table that X = C and the
Y and Z are more complex

BIM203 Logic Design Combinational Functions 34

 Gray to Binary (continued)
▪ Rearrange the table so that the input combinations are in
counting order, pair rows, and find rudimentary functions
Gray Binary Rudimentary Rudimentary
ABC xyz Functions of Functions of
C for y C for z
000 000
F=C F=C
001 111
010 011
F=C F=C
011 100
100 001
F=C F=C
101 110
110 010
F=C F=C
111 101
BIM203 Logic Design Combinational Functions 35
 Gray to Binary (continued)
▪ Assign the variables and functions to the multiplexer inputs:
C D00 C D10
C D01 C D11
C C
C D02 Out Y C D12 Out Z
C D03 C D13

A S1 8-to-1 A S1 8-to-1
B S0 MUX B S0 MUX
▪ Note that this approach (Approach 2) reduces the cost by
almost half compared to Approach 1.
▪ This result is no longer ROM-like
▪ Extending, a function of more than n variables is decomposed
into several sub-functions defined on a subset of the variables.
The multiplexer then selects among these sub-functions.
BIM203 Logic Design Combinational Functions 36
 Terms of Use
▪ All (or portions) of this material © 2008 by Pearson
Education, Inc.
▪ Permission is given to incorporate this material or
adaptations thereof into classroom presentations and
handouts to instructors in courses adopting the latest
edition of Logic and Computer Design Fundamentals as
the course textbook.
▪ These materials or adaptations thereof are not to be
sold or otherwise offered for consideration.
▪ This Terms of Use slide or page is to be included within
the original materials or any adaptations thereof.

BIM203 Logic Design Combinational Functions 37