DDCArv Ch6
DDCArv Ch6
DDCArv Ch6
Computer Architecture
Sarah Harris & David Harris
Chapter 6:
Architecture
Chapter 6 :: Topics
• Introduction
• Assembly Language
• Programming
• Machine Language
• Addressing Modes
• Lights, Camera, Action:
Compiling, Assembly, & Loading
• Odds & Ends
Instructions
Instructions: Addition
• sub: mnemonic
• b, c: source operands
• a: destination operand
Operands
Operands
• Operand location: physical location
in computer
– Registers
– Memory
– Constants (also called immediates)
Memory Operands
Operands: Memory
• Too much data to fit in only 32 registers
• Store more data in memory
• Memory is large, but slow
• Commonly used variables kept in
registers
RISC-V is byte-addressable
00000004 C D 1 9 A 6 5 B Word 4
00000003 4 0 F 3 0 7 8 8 Word 3
00000002 0 1 E E 2 8 4 2 Word 2
00000001 F 2 F 1 A C 0 7 Word 1
00000000 A B C D E F 7 8 Word 0
width = 4 bytes
00000004 C D 1 9 A 6 5 B Word 4
00000003 4 0 F 3 0 7 8 8 Word 3
00000002 0 1 E E 2 8 4 2 Word 2
00000001 F 2 F 1 A C 0 7 Word 1
00000000 A B C D E F 7 8 Word 0
13 12 11 10 00000010 C D 1 9 A 6 5 B Word 4
F E D C 0000000C 4 0 F 3 0 7 8 8 Word 3
B A 9 8 00000008 0 1 E E 2 8 4 2 Word 2
7 6 5 4 00000004 F 2 F 1 A C 0 7 Word 1
3 2 1 0 00000000 A B C D E F 7 8 Word 0
MSB LSB
width = 4 bytes
32 Digital Design & Computer Architecture Architecture
Reading Byte-Addressable Memory
• The address of a memory word must now be
multiplied by 4. For example,
– the address of memory word 2 is 2 × 4 = 8
– the address of memory word 10 is 10 × 4 = 40
(0x28)
13 12 11 10 00000010 C D 1 9 A 6 5 B Word 4
F E D C 0000000C 4 0 F 3 0 7 8 8 Word 3
B A 9 8 00000008 0 1 E E 2 8 4 2 Word 2
7 6 5 4 00000004 F 2 F 1 A C 0 7 Word 1
3 2 1 0 00000000 A B C D E F 7 8 Word 0
MSB LSB
width = 4 bytes
34 Digital Design & Computer Architecture Architecture
Writing Byte-Addressable Memory
• Example: store the value held in t7 into memory address
0x10 (16)
– if t7 holds the value 0xAABBCCDD, then after the sw completes,
word 4 (at address 0x10) in memory will contain that value
RISC-V assembly code
sw t7, 0x10(zero) # write t7 into address 16
13 12 11 10 00000010 A
C A
D B
1 B
9 C
A C
6 D
5 D
B Word 4
F E D C 0000000C 4 0 F 3 0 7 8 8 Word 3
B A 9 8 00000008 0 1 E E 2 8 4 2 Word 2
7 6 5 4 00000004 F 2 F 1 A C 0 7 Word 1
3 2 1 0 00000000 A B C D E F 7 8 Word 0
MSB LSB
width = 4 bytes
35 Digital Design & Computer Architecture Architecture
Chapter 6: Architecture
Generating Constants
Generating 12-Bit Constants
• 12-bit signed constants (immediates) using
addi:
C Code RISC-V assembly code
// int is a 32-bit signed word # s0 = a, s1 = b
int a = -372; addi s0, zero, -372
int b = a + 6; addi s1, s0, 6
Logical / Shift
Instructions
Programming
• High-level languages:
– e.g., C, Java, Python
– Written at higher level of abstraction
• High-level constructs: loops, conditional
statements, arrays, function calls
• First, introduce instructions that support
these:
– Logical operations
– Shift instructions
– Multiplication & division
– Branches & Jumps
41 Digital Design & Computer Architecture Architecture
Ada Lovelace, 1815-1852
• Wrote the first
computer program
• Her program calculated
the Bernoulli numbers
on Charles Babbage’s
Analytical Engine
• She was the daughter
of the poet Lord Byron
Multiplication and
Division
Multiplication
32 × 32 multiplication → 64 bit result
mul s3, s1, s2
s3 = lower 32 bits of result
mulh s4, s1, s2
s4 = upper 32 bits of result, treats operands as signed
{s4, s3} = s1 x s2
Example: s1 = 0x40000000 = 230; s2 = 0x80000000 = -231
s1 x s2 = -261 = 0xE0000000 00000000
s4 = 0xE0000000; s3 = 0x00000000
target: # label
add s1, s1, s0 # s1 = 4 + 4 = 8
target:
add s1, s1, s0 # s1 = 1 + 4 = 5
target:
add s1, s1, s0 # s1 = 1 + 4 = 5
Conditional
Statements & Loops
Conditional Statements & Loops
• Conditional Statements
– if statements
– if/else statements
• Loops
– while loops
– for loops
L1:
f = f – i; sub s0, s0, s3
else L1:
f = f – i; sub s0, s0, s3
done:
Arrays
Arrays
• Access large amounts of similar data
• Index: access each element
• Size: number of elements
123B4790 array[4]
123B478C array[3]
123B4788 array[2]
123B4784 array[1]
123B4780 array[0]
Main Memory
int array[5];
123B4790 array[4]
array[0] = array[0] * 2; 123B478C array[3]
array[1] = array[1] * 2; 123B4788 array[2]
123B4784 array[1]
123B4780 array[0]
# RISC-V assembly code
# s0 = array base address Main Memory
loop:
bge s1, t2, done # if not then done
slli t0, s1, 2 # t0 = i * 4 (byte offset)
add t0, t0, s0 # address of array[i]
lw t1, 0(t0) # t1 = array[i]
slli t1, t1, 3 # t1 = array[i] * 8
sw t1, 0(t0) # array[i] = array[i] * 8
addi s1, s1, 1 # i = i + 1
j loop # repeat
done:
Function Calls
Function Calls
• Caller: calling function (in this case, main)
• Callee: called function (in this case, sum)
C Code
void main()
{
int y;
y = sum(42, 7);
...
}
void simple() {
return; 0x0000051c simple: jr ra # return
}
void means that simple doesn’t return a value
jal simple:
ra = PC + 4 (0x00000304)
jumps to simple label (PC = 0x0000051c)
jr ra:
PC = ra (0x00000304)
The Stack
The Stack
• Memory used to temporarily
save variables
• Like stack of dishes, last-in-
first-out (LIFO) queue
• Expands: uses more memory
when more space needed
• Contracts: uses less memory
when the space is no longer
needed
Preserved Nonpreserved
Callee-Saved Caller-Saved
s0-s11 t0-t6
sp a0-a7
ra
stack above sp stack below sp
f2's stack
BEF7FEF4 BEF7FEF4 BEF7FEF4 s4 sp
• Callee
– Save registers that might be disturbed (s0-s11)
– Perform function
– Put result in a0
– Restore registers
– Return: jr ra
Recursive Functions
Recursive Function Example
• Function that calls itself
• When converting to assembly code:
– In the first pass, treat recursive calls as if it’s calling a
different function and ignore overwritten registers.
– Then save/restore registers on stack as needed.
jr ra # return
else else:
return (n*factorial(n−1)); addi a0, a0, -1 # n = n − 1
} jal factorial # recursive call
stack frames
FE4 stack frames FE4 a0 (2) FE4 a0 (2)
n=2
FE0 FE0 ra (0x8528) sp FE0 ra (0x8528) sp a0 = 2 x 1
Machine Language
Machine Language
• Binary representation of instructions
• Computers only understand 1’s and 0’s
• 32-bit instructions
– Simplicity favors regularity: 32-bit data &
instructions
• 4 Types of Instruction Formats:
– R-Type
– I-Type
– S/B-Type
– U/J-Type
111 Digital Design & Computer Architecture Architecture
R-Type
• Register-type
• 3 register operands:
– rs1, rs2: source registers
– rd: destination register
• Other fields:
– op: the operation code or opcode
– funct7,funct3:
the function (7 bits and 3-bits, respectively)
with opcode, tells computer what operation to perform
R-Type
31:25 24:20 19:15 14:12 11:7 6:0
funct7 rs2 rs1 funct3 rd op
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
Machine Language:
More Formats
I-Type
• Immediate-type
• 3 operands:
– rs1: register source operand
– rd: register destination operand
– imm: 12-bit two’s complement immediate
• Other fields:
– op: the opcode
– Simplicity favors regularity: all instructions have opcode
– funct3: the function (3-bit function code)
– with opcode, tells computer what operation to perform
I-Type
31:20 19:15 14:12 11:7 6:0
imm11:0 rs1 funct3 rd op
12 bits 5 bits 3 bits 5 bits 7 bits
S-Type
31:25 24:20 19:15 14:12 11:7 6:0
imm11:5 rs2 rs1 funct3 imm4:0 op
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
B-Type
31:25 24:20 19:15 14:12 11:7 6:0
imm12,10:5 rs2 rs1 funct3 imm4:1,11 op
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
imm12:0 = 16 0 0 0 0 0 0 0 0 1 0 0 0 0
bit number 12 11 10 9 8 7 6 5 4 3 2 1 0
U-Type
31:12 11:7 6:0
imm31:12 rd op
20 bits 5 bits 7 bits
J-Type
31:12 11:7 6:0
imm20,10:1,11,19:12 rd op
20 bits 5 bits 7 bits
• Note: jalr is I-type, not j-type, to specify rs1
125 Digital Design & Computer Architecture Architecture
J-Type Example
# Address RISC-V Assembly
0x0000540C jal ra, func1
0x00005410 add s1, s2, s3
... ...
0xABC04 – 0x540C =
0x000ABC04 func1: add s4, s5, s8
0XA67F8
... ...
func1 is 0xA67F8 bytes past jal
imm = 0xA67F8 0 1 0 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0
bit number 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Immediate Encodings
Constants / Immediates
• lw and sw use constants or immediates
• immediately available from instruction
• 12-bit two’s complement number
• addi: add immediate
• Is subtract immediate (subi) necessary?
Immediate Bits
imm11 imm11:1 imm0 I, S
imm12 imm11:1 0 B
imm31:21 imm20:12 0 U
imm20 imm20:12 imm11:1 0 J
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 31 31 31 30:25 24:21 20 I
instruction bit
31 31 31 31 30:25 11:8 7 S
31 31 31 30 29:25, 11 10:7 0 B
31 30:20 19:12 0 0 0 0 U
31 31 19:12 20 21:16 15:12 0 J
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Immediate Bits
133 Digital Design & Computer Architecture Architecture
Chapter 6: Architecture
Reading
Machine Language &
Addressing Operands
Instruction Fields & Formats
Instruction op funct3 Funct7 Type
add 0110011 (51) 000 (0) 0000000 (0) R-Type
sub 0110011 (51) 000 (0) 0100000 (32) R-Type
and 0110011 (51) 111 (7) 0000000 (0) R-Type
or 0110011 (51) 110 (6) 0000000 (0) R-Type
addi 0010011 (19) 000 (0) - I-Type
beq 1100011 (99) 000 (0) - B-Type
bne 1100011 (99) 001 (1) - B-Type
lw 0000011 (3) 010 (2) - I-Type
sw 0100011 (35) 010 (2) - S-Type
jal 1101111 (111) - - J-Type
jalr 1100111 (103) 000 (0) - I-Type
lui 0110111 (55) - - U-Type
See Appendix B for other instruction encodings
135 Digital Design & Computer Architecture Architecture
Interpreting Machine Code
• Write in binary
• Start with op: tells how to parse rest
• Extract fields
• op, funct3, and funct7 fields tell operation
• Ex: 0x41FE83B3 and 0xFDA58393
Compiling,
Assembling, & Loading
Programs
The Power of the Stored Program
• 32-bit instructions & data stored in memory
• Sequence of instructions: only difference
between two applications
• To run a new program:
– No rewiring required
– Simply store new program in memory
• Program Execution:
– Processor fetches (reads) instructions from memory
in sequence
– Processor performs the specified operation
Address Instructions
0000083C F F A 9 A 3 8 3
00000838 F F 2 3 0 9 1 3
00000834 4 0 7 3 0 2 B 3 Program Counter
00000830 0 1 4 9 8 9 3 3 PC (PC): keeps track of
current instruction
Main Memory
Compiler
Assembly Code
Assembler
Object Files
Object File
Library Files
Linker
Executable
Loader
Memory
Dynamic Data
0x10001000 Heap
0x10000FFC
Global Data gp
0x10000000
Text
0x00008000
Exception
Handlers
0x00000000 pc
void main() {
f = 2;
g = 3;
y = func(f,g);
return;
}
Endianness
Big-Endian & Little-Endian Memory
• How to number bytes within a word?
• Little-endian: byte numbers start at the little (least
significant) end
• Big-endian: byte numbers start at the big (most significant)
end
• Word address is the same for big- or little-endian
Big-Endian Little-Endian
Byte Word Byte
Address Address Address
C D E F C F E D C
8 9 A B 8 B A 9 8
4 5 6 7 4 7 6 5 4
0 1 2 3 0 3 2 1 0
MSB LSB MSB LSB
C D E F C F E D C
8 9 A B 8 B A 9 8
4 5 6 7 4 7 6 5 4
0 1 2 3 0 3 2 1 0
MSB LSB MSB LSB
• Big-endian: s0 = 0x00000045
• Little-endian: s0 = 0x00000067
Big-Endian Little-Endian
Word
Byte Address 0 1 2 3 Address 3 2 1 0 Byte Address
Data Value 23 45 67 89 0 23 45 67 89 Data Value
MSB LSB MSB LSB
158 Digital Design & Computer Architecture Architecture
Chapter 6: Architecture
blt s1, s2
s1 = -231; s2 = 230
taken
bltu s1, s2
s1 = 231; s2 = 230
not taken
Compressed
Instructions
Compressed Instructions
• 16-bit RISC-V instructions
• Replace common integer and floating-point
instructions with 16-bit versions.
• Most RISC-V compilers/processors can use a
mix of 32-bit and 16-bit instructions (and
use 16-bit instructions whenever possible).
• Uses prefix: c.
• Examples:
– add → c.add
– lw → c.lw
– addi → c.addi
168 Digital Design & Computer Architecture Architecture
Compressed Instructions Example
C Code RISC-V assembly code
int i; # s0 = scores base address, s1 = i
int scores[200];
c.li s1, 0 # i = 0
addi t2, zero, 200 # t2 = 200
Floating-Point
Instructions
RISC-V Floating-Point Extensions
• RISC-V offers three floating point extensions:
• RVF: single-precision (32-bit)
• 8 exponent bits, 23 fraction bits
• RVD: double-precision (64-bit)
• 11 exponent bits, 52 fraction bits
• RVQ: quad-precision (128-bit)
• 15 exponent bits, 112 fraction bits
Exceptions
Exceptions
• Unscheduled function call to exception handler
• Caused by:
– Hardware, also called an interrupt, e.g., keyboard
– Software, also called traps, e.g., undefined instruction
• When exception occurs, the processor:
– Records the cause of the exception
– Jumps to exception handler
– Returns to the program
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