archi12Assembleur2

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Assembly Language
• Instructions: commands in a computer’s
language
– Assembly language: human-readable format of
instructions
– Machine language: computer-readable format
(1’s and 0’s)
Architecture • RISC-V architecture:
– Developed by Krste Asanovic, David Patterson
and their colleagues at UC Berkeley in 2010.
– First widely accepted open-source computer
architecture
Once you’ve learned one architecture, it’s easier to learn others
2 Digital Design & Computer Architecture Architecture
Architecture Design Principles

Underlying design principles, as articulated by
Hennessy and Patterson:
1.Simplicity favors regularity

2.Make the common case fast
3.Smaller is faster
Instructions
4.Good design demands good compromises
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Instructions: Addition Instructions: Subtraction

Similar to addition - only mnemonic changes
C Code RISC-V assembly code C Code RISC-V assembly code

a = b + c; add a, b, c a = b - c; sub a, b, c
• add: mnemonic indicates operation to perform • sub: mnemonic

• b, c: source operands (on which the operation is • b, c: source operands
performed) • a: destination operand
• a: destination operand (to which the result is
written)
5 Digital Design & Computer Architecture Architecture 6 Digital Design & Computer Architecture Architecture
Design Principle 1 Multiple Instructions

Simplicity favors regularity More complex code is handled by multiple
RISC-V instructions.
• Consistent instruction format
C Code RISC-V assembly code
• Same number of operands (two sources a = b + c - d; add t, b, c # t = b + c
and one destination) sub a, t, d # a = t - d
• Easier to encode and handle in hardware
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Design Principle 2
Make the common case fast
• RISC-V includes only simple, commonly used
instructions
• Hardware to decode and execute instructions can
be simple, small, and fast
• More complex instructions (that are less common)
Operands
performed using multiple simple instructions
• RISC-V is a reduced instruction set computer (RISC),
with a small number of simple instructions
• Other architectures, such as Intel’s x86, are complex
instruction set computers (CISC)
Operands Operands: Registers

• Operand location: physical location • RISC-V has 32 32-bit registers
in computer • Registers are faster than memory
– Registers • RISC-V called “32-bit architecture”
– Memory because it operates on 32-bit data
– Constants (also called immediates)
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Design Principle 3 RISC-V Register Set

Name Register Number Usage
Smaller is Faster zero x0 Constant value 0
ra x1 Return address
• RISC-V includes only a small number
sp x2 Stack pointer
of registers gp x3 Global pointer
tp x4 Thread pointer
t0-
t0-2 x5-7 Temporaries
s0/fp
s0/fp x8 Saved register / Frame pointer
s1 x9 Saved register
a0-
a0-1 x10-11 Function arguments / return values
a2-
a2-7 x12-17 Function arguments
s2-
s2-11 x18-27 Saved registers
t3-
t3-6 x28-31 Temporaries
RISC-V Instruction Set Operands: Registers

Name Register Number sens
add,sub add Rd, Rs1, Rs2 Rd = registre destination Operations
• Registers:
mul,div Rs = Regitre source arithmetic – Can use either name (i.e., ra, zero) or x0, x1,
rem etc.
addi add Rd, Rs, Imm Imm = constante entiere – Using name is preferred
lw lw Rd, Imm(Radd) Radd = registre adresse Lect. mem
• Registers used for specific purposes:
sw sw Rd, Imm(Radd) Imm 12 bits [-2048, 2048] Ecrit. mem
• zero always holds the constant value 0.
lui lui Rd, ImmL immL sur 20 bits (haut) chargement
and,or and Rd, Rs1, Rs2 Operations • the saved registers, s0-s11, used to hold
xor logic variables
sll,srl sll Rd, Rs1, Rs2 decallages • the temporary registers, t0-t6, used to
beq,bne beq Rs1,Rs2, Imm Imm = etiquette (offset) Branchem- hold intermediate values during a larger
blt,bge branchement =pc+imm ent 12 bits computation
J , Jal J ImmL ImmL=immediat long Jump 20bits • Discuss others later
jra Jra Reg Jump Reg
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Instructions with Registers Instructions with Constants

• Revisit add instruction • addi instruction

# s0 = a, s1 = b, s2 = c # s0 = a, s1 = b
a = b + c; add s0, s1, s2 a = b + 6; addi s0, s1, 6
# indicates a single-line comment
Operands: Memory
• Too much data to fit in only 32 registers
• Store more data in memory
• Memory is large, but slow
Memory Operands • Commonly used variables kept in

registers
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Memory Byte-Addressable Memory

• First, we’ll discuss word-addressable • Each data byte has a unique address
memory • Load/store words or single bytes: load byte (lb)
• Then we’ll discuss byte-addressable and store byte (sb)
memory • 32-bit word = 4 bytes, so word address increments
by 4
Byte Address Word Address Data Word Number
RISC-V is byte-addressable 13 12 11 10 00000010 C D 1 9 A 6 5 B Word 4

F E D C 0000000C 4 0 F 3 0 7 8 8 Word 3
B A 9 8 00000008 0 1 E E 2 8 4 2 Word 2
7 6 5 4 00000004 F 2 F 1 A C 0 7 Word 1
3 2 1 0 00000000 A B C D E F 7 8 Word 0
MSB LSB
width = 4 bytes
Reading Byte-Addressable Memory Reading Byte-Addressable Memory

• The address of a memory word must now be • Example: Load a word of data at memory
multiplied by 4. For example, address 8 into s3.
– the address of memory word 2 is 2 × 4 = 8 • s3 holds the value 0x1EE2842 after load
– the address of memory word 10 is 10 × 4 = 40 RISC-V assembly code
(0x28) lw s3, 8(zero) # read word at address 8 into s3
Byte Address Word Address Data Word Number
• RISC-V is byte-addressed, not word-

addressed 13 12 11 10 00000010 C D 1 9 A 6 5 B Word 4
F E D C 0000000C 4 0 F 3 0 7 8 8 Word 3
B A 9 8 00000008 0 1 E E 2 8 4 2 Word 2
7 6 5 4 00000004 F 2 F 1 A C 0 7 Word 1
3 2 1 0 00000000 A B C D E F 7 8 Word 0
MSB LSB
width = 4 bytes
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Writing Byte-Addressable Memory

• Example: store the value held in t7 into memory address
0x10 (16)
– if t7 holds the value 0xAABBCCDD, then after the sw completes,
word 4 (at address 0x10) in memory will contain that value
RISC-V assembly code
sw t7, 0x10(zero)
Byte Address
# write t7 into address 16
Word Address Data Word Number

Generating Constants
13 12 11 10 00000010 A
C A
D B
1 B
9 C
A C
6 D
5DB Word 4
F E D C 0000000C 4 0 F 3 0 7 8 8 Word 3
B A 9 8 00000008 0 1 E E 2 8 4 2 Word 2
7 6 5 4 00000004 F 2 F 1 A C 0 7 Word 1
3 2 1 0 00000000 A B C D E F 7 8 Word 0
MSB LSB
width = 4 bytes
Generating 12-Bit Constants Generating 32-bit Constants

• 12-bit signed constants (immediates) using • Use load upper immediate (lui) and addi
addi: • lui: puts an immediate in the upper 20 bits
C Code RISC-V assembly code of destination register and 0’s in lower 12
// int is a 32-bit signed word # s0 = a, s1 = b
int a = -372; addi s0, zero, -372
bits
int b = a + 6; addi s1, s0, 6
# s0 = a
int a = 0xFEDC8765; lui s0, 0xFEDC8
addi s0, s0, 0x765
Any immediate that needs more than 12 bits
cannot use this method. Remember that addi sign-extends its 12-bit
immediate
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Logical Instructions
• and, or, xor
– and: useful for masking bits
• Masking all but the least significant byte of a value:
0xF234012F AND 0x000000FF = 0x0000002F
Logical / Shift – or: useful for combining bit fields

• Combine 0xF2340000 with 0x000012BC:
0xF2340000 OR 0x000012BC = 0xF23412BC
Instructions – xor: useful for inverting bits:
• A XOR -1 = NOT A (remember that -1 = 0xFFFFFFFF)
Logical Instructions: Example 1 Shift Instructions

Shift amount is in (lower 5 bits of) a register
• sll: shift left logical
– Example: sll t0, t1, t2 # t0 = t1 << t2
• srl: shift right logical
– Example: srl t0, t1, t2 # t0 = t1 >> t2
• sra: shift right arithmetic
– Example: sra t0, t1, t2 # t0 = t1 >>> t2
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Immediate Shift Instructions

Shift amount is an immediate between 0 to 31
• slli: shift left logical immediate

– Example: slli t0, t1, 23 # t0 = t1 << 23
• srli: shift right logical immediate
– Example: srli t0, t1, 18 # t0 = t1 >> 18
Multiplication and
• srai: shift right arithmetic immediate
– Example: srai t0, t1, 5 # t0 = t1 >>> 5 Division
Multiplication Division
32 × 32 mulKplicaKon → 64 bit result 32-bit division → 32-bit quotient & remainder
mul s3, s1, s2 – div s3, s1, s2 # s3 = s1/s2

s3 = lower 32 bits of result – rem s4, s1, s2 # s4 = s1%s2
mulh s4, s1, s2
s4 = upper 32 bits of result, treats operands as signed
{s4, s3} = s1 x s2
Example: s1 = 0x00000011 = 17; s2 = 0x00000003 = 3
s1 / s2 = 5
Example: s1 = 0x40000000 = 230; s2 = 0x80000000 = -231
s1 % s2 = 2
s1 x s2 = -261 = 0xE0000000 00000000 s3 = 0x00000005; s4 = 0x00000002
s4 = 0xE0000000; s3 = 0x00000000
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Branching
• Execute instructions out of sequence
• Types of branches:
– Conditional
• branch if equal (beq)
Branches & Jumps •

•
•
branch if not equal (bne)
branch if less than (blt)
branch if greater than or equal (bge)
– Unconditional
• jump (j) We’ll talk
• jump register (jr) about these
• jump and link (jal) when discuss
• jump and link register (jalr) function calls
Conditional Branching The Branch Not Taken (bne)

# RISC-V assembly # RISC-V assembly
addi s0, zero, 4 # s0 = 0 + 4 = 4 addi s0, zero, 4 # s0 = 0 + 4 = 4
addi s1, zero, 1 # s1 = 0 + 1 = 1 addi s1, zero, 1 # s1 = 0 + 1 = 1
slli s1, s1, 2 # s1 = 1 << 2 = 4 slli s1, s1, 2 # s1 = 1 << 2 = 4
beq s0, s1, target # branch is taken bne s0, s1, target # branch not taken
addi s1, s1, 1 # not executed addi s1, s1, 1 # s1 = 4 + 1 = 5
sub s1, s1, s0 # not executed sub s1, s1, s0 # s1 = 5 – 4 = 1
target: # label target:

add s1, s1, s0 # s1 = 4 + 4 = 8 add s1, s1, s0 # s1 = 1 + 4 = 5
Labels indicate instruction location. They can’t be reserved words and

must be followed by a colon (:)
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Unconditional Branching (j)

# RISC-V assembly
j target # jump to target
srai s1, s1, 2 # not executed
addi s1, s1, 1 # not executed
sub
target:
s1, s1, s0 # not executed
Conditional
add s1, s1, s0 # s1 = 1 + 4 = 5
Statements & Loops
Conditional Statements & Loops If Statement

• Conditional Statements
– if statements # s0 = f, s1 = g, s2 = h
– if/else statements if (i == j)
# s3 = i, s4 = j
bne s3, s4, L1

• Loops f = g + h;
add s0, s1, s2
– while loops L1:
f = f – i;
– for loops sub s0, s0, s3
Assembly tests opposite case (i != j) of high-level code (i == j)
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If/Else Statement While Loops

# s0 = f, s1 = g, s2 = h // determines the power # s0 = pow, s1 = x
# s3 = i, s4 = j // of x such that 2x = 128
if (i == j) int pow = 1; addi s0, zero, 1
int x = 0; add s1, zero, zero
f = g + h; bne s3, s4, L1
addi t0, zero, 128
add s0, s1, s2 while (pow != 128) { while:
j done pow = pow * 2; beq s0, t0, done
else x = x + 1; slli s0, s0, 1
f = f – i; L1: } addi s1, s1, 1
sub s0, s0, s3 j while
done: done:
Assembly tests opposite case (pow == 128) of high-level code

( pow != 128)
Assembly tests opposite case (i != j) of high-level code (i == j)
For Loops For Loops

for (initialization; condition; loop operation)
statement C Code RISC-V assembly code
// add the numbers from 0 to 9 # s0 = i, s1 = sum
int sum = 0; addi s1, zero, 0
• initialization: executes before the loop begins int i; add s0, zero, zero
• condition: is tested at the beginning of each iteration addi t0, zero, 10
for (i=0; i!=10; i = i+1) { for:
• loop operation: executes at the end of each iteration sum = sum + i; beq s0, t0, done
} add s1, s1, s0
• statement: executes each time the condition is met addi s0, s0, 1
j for
done:
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Less Than Comparison Less Than Comparison: Version 2

// add the powers of 2 from 1 # s0 = i, s1 = sum
C Code RISC-V assembly code // to 100 addi s1, zero, 0
// add the powers of 2 from 1 # s0 = i, s1 = sum int sum = 0; addi s0, zero, 1
// to 100 addi s1, zero, 0 int i; addi t0, zero, 101
int sum = 0; addi s0, zero, 1 loop:
int i; addi t0, zero, 101 for (i=1; i < 101; i = i*2) { slt t2, s0, t0
loop: sum = sum + i; beq t2, zero, done
for (i=1; i < 101; i = i*2) { bge s0, t0, done } add s1, s1, s0
sum = sum + i; add s1, s1, s0 slli s0, s0, 1
} slli s0, s0, 1 j loop
j loop done:
done:
slt: set if less than instruction

slt t2, s0, t0 # if s0 < t0, t2 = 1
# otherwise t2 = 0
Arrays
• Access large amounts of similar data
• Index: access each element
• Size: number of elements
Arrays
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Arrays Accessing Arrays

// C Code Address Data
• 5-element array int array[5]; 123B4790 array[4]
array[0] = array[0] * 2;
• Base address = 0x123B4780 (address of first array[1] = array[1] * 2;
123B478C
123B4788
array[3]
array[2]
element, array[0]) 123B4784

123B4780
array[1]
array[0]
# RISC-V assembly code
• First step in accessing an array: load base # s0 = array base address
lui s0, 0x123B4
Main Memory
# 0x123B4 in upper 20 bits of s0

address into a register addi s0, s0, 0x780 # s0 = 0x123B4780
Address Data lw t1, 0(s0) # t1 = array[0]

slli t1, t1, 1 # t1 = t1 * 2
123B4790 array[4]
sw t1, 0(s0) # array[0] = t1
123B478C array[3]
123B4788 array[2]
123B4784 array[1] lw t1, 4(s0) # t1 = array[1]
123B4780 array[0] slli t1, t1, 1 # t1 = t1 * 2
sw t1, 4(s0) # array[1] = t1
Main Memory
Accessing Arrays Using For Loops Accessing Arrays Using For Loops
// C Code # RISC-V assembly code
int array[1000]; # s0 = array base address, s1 = i
int i; # initialization code
lui s0, 0x23B8F # s0 = 0x23B8F000
ori s0, s0, 0x400 # s0 = 0x23B8F400
for (i=0; i < 1000; i = i + 1)
addi s1, zero, 0 # i = 0
array[i] = array[i] * 8;
addi t2, zero, 1000 # t2 = 1000

loop:
# s0 = array base address, s1 = i
bge s1, t2, done # if not then done
slli t0, s1, 2 # t0 = i * 4 (byte offset)
add t0, t0, s0 # address of array[i]
lw t1, 0(t0) # t1 = array[i]
slli t1, t1, 3 # t1 = array[i] * 8
sw t1, 0(t0) # array[i] = array[i] * 8
addi s1, s1, 1 # i = i + 1
j loop # repeat
done:
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ASCII Code Cast of Characters: ASCII Encodings

# Char # Char # Char # Char # Char # Char
• ASCII: American Standard Code for 20 space 30 0 40 @ 50 P 60 ` 70 p
Information Interchange 21 ! 31 1 41 A 51 Q 61 a 71 q
22 “ 32 2 42 B 52 R 62 b 72 r
• Each text character has unique byte 23
24
#
$
33
34
3
4
43
44
C
D
53
54
S
T
63
64
c
d
73
74
s
t
value 25 % 35 5 45 E 55 U 65 e 75 u
26 & 36 6 46 F 56 V 66 f 76 v
– For example, S = 0x53, a = 0x61, A = 0x41 27 ‘ 37 7 47 G 57 W 67 g 77 w
28 ( 38 8 48 H 58 X 68 h 78 x
– Lower-case and upper-case differ by 0x20 (32) 29 ) 39 9 49 I 59 Y 69 i 79 y
2A * 3A : 4A J 5A Z 6A j 7A z
2B + 3B ; 4B K 5B [ 6B k 7B {
2C , 3C < 4C L 5C \ 6C l 7C |
2D - 3D = 4D M 5D ] 6D m 7D }
2E . 3E > 4E N 5E ^ 6E n 7E ~
2F / 3F ? 4F O 5F _ 6F o
Accessing Arrays of Characters Chapter 6: Architecture

// C Code
char str[80] = “CAT”;
int len = 0;
// compute length of string

while (str[len]) len++;

# s0 = array base address, s1 = len
Function Calls
addi s1, zero, 0 # len = 0
while: add t0, s0, s1 # address of str[len]
lw t1, 0(t0) # load str[len]
beq t1, zero, done # are we at the end of the string?
addi s1, s1, 1 # len++
j while # repeat while loop
done:
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Function Calls Simple Function Call

• Caller: calling function (in this case, main) int main() {
simple(); 0x00000300 main: jal simple # call
• Callee: called function (in this case, sum) a = b + c; 0x00000304 add s0, s1, s2
} ... ...
C Code
void main() void simple() {
{ return; 0x0000051c simple: jr ra # return
int y; }
y = sum(42, 7); void means that simple doesn’t return a value
...
}
jal simple:
int sum(int a, int b) ra = PC + 4 (0x00000304)
{ jumps to simple label (PC = 0x0000051c)
return (a + b);
} jr ra:
PC = ra (0x00000304)
Function Calling Conventions RISC-V Function Calling Conventions

• Caller: • Call Function: jump and link (jal func)
– passes arguments to callee • Return from function: jump register (jr ra)
– jumps to callee
• Arguments: a0 – a7
• Callee:
• Return value: a0
– performs the function
– returns result to caller
– returns to point of call
– must not overwrite registers or memory needed by
caller
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Input Arguments & Return Value Input Arguments & Return Value
int main() # s7 = y
main:
{
. . .
int y; addi a0, zero, 2 # argument 0 = 2
... addi a1, zero, 3 # argument 1 = 3
y = diffofsums(2, 3, 4, 5); // 4 arguments addi a2, zero, 4 # argument 2 = 4
addi a3, zero, 5 # argument 3 = 5
... jal diffofsums # call function
} add s7, a0, zero # y = returned value
. . .
int diffofsums(int f, int g, int h, int i) # s3 = result
{ diffofsums:
int result; add t0, a0, a1 # t0 = f + g
add t1, a2, a3 # t1 = h + i
result = (f + g) - (h + i);
sub s3, t0, t1 # result = (f + g) − (h + i)
return result; // return value add a0, s3, zero # put return value in a0
} jr ra # return to caller
Preserved Registers Chapter 6: Architecture
Preserved Nonpreserved
Callee-Saved Caller-Saved
s0-s11 t0-t6
sp a0-a7 Machine Language
ra
stack above sp stack below sp
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Machine Language R-Type

• Binary representation of instructions • Register-type
• 3 register operands:
• Computers only understand 1’s and 0’s – rs1, rs2: source registers
– rd: destination register
• 32-bit instructions • Other fields:
– Simplicity favors regularity: 32-bit data & – op: the operation code or opcode
instructions – funct7,funct3:
the function (7 bits and 3-bits, respectively)
• 4 Types of Instruction Formats: with opcode, tells computer what operation to perform
– R-Type
R-Type
– I-Type 31:25 24:20 19:15 14:12 11:7 6:0
– S/B-Type funct7 rs2 rs1 funct3 rd op

7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
– U/J-Type
R-Type Examples Chapter 6: Architecture
Assembly Field Values Machine Code
Machine Language:
funct7 rs2 rs1 funct3 rd op funct7 rs2 rs1 funct3 rd op
add s2, s3, s4
add x18,x19,x20 0 20 19 0 18 51 0000 000 10100 10011 000 10010 011 0011 (0x01498933)
sub t0, t1, t2 32 7 6 0 5 51 0100 000 00111 00110 000 00101 011 0011 (0x407302B3)
sub x5, x6, x7
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits 7 bits 5 bits 5 bits 3 bits 5 bits 7 bits
More Formats
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I-Type I-Type Examples

• Immediate-type
• 3 operands: imm11:0 rs1 funct3 rd op imm11:0 rs1 funct3 rd op
– rs1: register source operand addi
addi
s0, s1, 12
x8, x9, 12 12 9 0 8 19 0000 0000 1100 01001 000 01000 001 0011 (0x00C48413)
addi s2, t1, -14
– rd: register destination operand addi x18,x6, -14 -14 6 0 18 19 1111 1111 0010 00110 000 10010 001 0011 (0xFF230913)
lw t2, -6(s3) -6 19 2 7 3 1111 1111 1010 10011 010 00111 000 0011 (0xFFA9A383)
– imm: 12-bit two’s complement immediate lw
lh
x7, -6(x19)
s1, 27(zero) 27 0 1 9 3 0000 0001 1011 00000 001 01001 000 0011 (0x01B01483)
lh x9, 27(x0)
• Other fields: lb
lb
s4, 0x1F(s4)
x20,0x1F(x20)
0x1F 20 0 20 3 0000 0001 1111 10100 000 10100 000 0011 (0x01FA0A03)
12 bits 5 bits 3 bits 5 bits 7 bits 12 bits 5 bits 3 bits 5 bits 7 bits
– op: the opcode
– Simplicity favors regularity: all instructions have opcode
– funct3: the function (3-bit function code)
– with opcode, tells computer what operation to perform
I-Type
31:20 19:15 14:12 11:7 6:0
imm11:0 rs1 funct3 rd op
12 bits 5 bits 3 bits 5 bits 7 bits
S/B-Type S-Type
• Store-Type • Store-Type
• 3 operands:
• Branch-Type – rs1: base register
• Differ only in immediate encoding – rs2: value to be stored to memory
– imm: 12-bit two’s complement immediate
• Other fields:
– op: the opcode
– Simplicity favors regularity: all instructions have opcode
31:25 24:20 19:15 14:12 11:7 6:0
imm11:5 rs2 rs1 funct3 imm4:0 op S-Type – with opcode, tells computer what operation to perform
imm12,10:5 rs2 rs1 funct3 imm4:1,11 op B-Type
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits S-Type
31:25 24:20 19:15 14:12 11:7 6:0
imm11:5 rs2 rs1 funct3 imm4:0 op
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S-Type Examples B-Type

• Branch-Type (similar format to S-Type)
• 3 operands:
– rs1: register source 1
– rs2: register source 2
– imm12:1: 12-bit two’s complement immediate – address offset
imm11:5 rs2 rs1 funct3 imm4:0 op imm11:5 rs2 rs1 funct3 imm4:0 op
sw
sw
t2, -6(s3)
x7, -6(x19) 1111 111 7 19 2 11010 35 1111 111 00111 10011 010 11010 010 0011 (0xFE79AD23) • Other fields:
sh s4, 23(t0)
sh x20,23(x5) 0000 000 20 5 1 10111 35 0000 000 10100 00101 001 10111 010 0011 (0x01429BA3)
– op: the opcode
sb t5, 0x2D(zero) 0000 001 30 0 0 01101 35 0000 001 11110 00000 000 01101 010 0011 (0x03E006A3)
sb x30,0x2D(x0)
7 bits 5 bits 5 bits 3 bits 5 bits 7 bits 7 bits 5 bits 5 bits 3 bits 5 bits 7 bits – Simplicity favors regularity: all instructions have opcode
– with opcode, tells computer what operation to perform
B-Type
31:25 24:20 19:15 14:12 11:7 6:0
imm12,10:5 rs2 rs1 funct3 imm4:1,11 op
B-Type Example U/J-Type

• The 13-bit immediate encodes where to branch (relative • Upper-Immediate-Type
to the branch instruction)
• Immediate encoding is strange • Jump-Type
• Example: • Differ only in immediate encoding
# RISC-V Assembly
0x70 beq s0, t5, L1 1 31:12 11:7 6:0
0x74 add s1, s2, s3 2
0x78 sub s5, s6, s7
3
imm31:12 rd op U-Type
0x7C lw t0, 0(s1)
4
0x80 L1: addi s1, s1, -15 imm20,10:1,11,19:12 rd op J-Type
L1 is 4 instructions (i.e., 16 bytes) past beq
20 bits 5 bits 7 bits
imm12:0 = 16 0 0 0 0 0 0 0 0 1 0 0 0 0
bit number 12 11 10 9 8 7 6 5 4 3 2 1 0

imm12,10:5 rs2 rs1 funct3 imm4:1,11 op imm12,10:5 rs2 rs1 funct3 imm4:1,11 op
beq s0, t5, L1
beq x8, x30, 16
0000 000 30 8 0 1000 0 99 0000 000 11110 01000 000 1000 0 110 0011 (0x01E40863)
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U-Type U-Type Example

• Upper-immediate-Type • Upper-immediate-Type
• Used for load upper immediate (lui) • Used for load upper immediate (lui)
• 2 operands: • 2 operands:
– rd: destination register – rd: destination register
– imm31:12:upper 20 bits of a 32-bit immediate – imm31:12:upper 20 bits of a 32-bit immediate
• Other fields: • Other fields:
– op: the operation code or opcode – tells computer what – op: the operation code or opcode – tells computer what
operation to perform operation to perform
U-Type Assembly Field Values Machine Code

31:12 11:7 6:0 imm31:12 rd op imm31:12 rd op
lui s5, 0x8CDEF
imm31:12 rd op lui x21,0x8CDEF
0x8CDEF 21 55 1000 1100 1101 1110 1111 10101 011 0111 (0x8CDEFAB7)
J-Type J-Type Example

• Jump-Type # Address
0x0000540C
RISC-V Assembly
jal ra, func1
• Used for jump-and-link instruction (jal) 0x00005410

...
add s1, s2, s3
...
0xABC04 – 0x540C =
• 2 operands: 0x000ABC04 func1: add s4, s5, s8
0XA67F8
... ...
– rd: destination register
func1 is 0xA67F8 bytes past jal
– imm20,10:1,11,19:12: 20 bits (20:1) of a 21-bit immediate
imm = 0xA67F8
• Other fields: bit number
0
20
1 0 1 0
19 18 17 16
0 1 1 0
15 14 13 12
0 1 1 1
11 10 9 8
1 1 1 1
7 6 5 4
1 0 0 0
3 2 1 0
– op: the operation code or opcode – tells computer what
operation to perform Assembly Field Values Machine Code
imm20,10:1,11,19:12 rd op imm20,10:1,11,19:12 rd op
jal ra, func1 0111 1111 1000 1010 0110 (0x7F8A60EF)
J-Type jal x1, 0xA67F8
0111 1111 1000 1010 0110
20 bits
1
5 bits
111
7 bits 20 bits
00001
5 bits
110 1111
7 bits
31:12 11:7 6:0

imm20,10:1,11,19:12 rd op
• Note: jalr is I-type, not j-type, to specify rs1
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Review: Instruction Formats Design Principle 4

7 bits 5 bits 5 bits 3 bits 5 bits 7 bits Good design demands good compromises
funct7 rs2 rs1 funct3 rd op R-Type • Multiple instruction formats allow flexibility
imm11:0 rs1 funct3 rd op I-Type - add, sub: use 3 register operands
imm11:5 rs2 rs1 funct3 imm4:0 op S-Type - lw, sw, addi: use 2 register operands and a
constant
imm12,10:5 rs2 rs1 funct3 imm4:1,11 op B-Type
imm31:12 rd op U-Type • Number of instruction formats kept small
imm20,10:1,11,19:12 rd op J-Type - to adhere to design principles 1 and 3
20 bits 5 bits 7 bits (simplicity favors regularity and smaller is
faster).
Chapter 6: Architecture Constants / Immediates

• lw and sw use constants or immediates
• immediately available from instruction
• 12-bit two’s complement number
• addi: add immediate
Immediate Encodings • Is subtract immediate (subi) necessary?

# s0 = a, s1 = b
a = a + 4; addi s0, s0, 4
b = a – 12; addi s1, s0, -12
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Constants / Immediates Immediate Encodings

Instruction Bits
Immediate Bits funct7 4 3 2 1 0 rs1 funct3 rd R
imm11 imm11:1 imm0 I, S
11 10 9 8 7 6 5 4 3 2 1 0 rs1 funct3 rd I
11 10 9 8 7 6 5 rs2 rs1 funct3 4 3 2 1 0 S
imm12 imm11:1 0 B 12 10 9 8 7 6 5 rs2 rs1 funct3 4 3 2 1 11 B
imm31:21 imm20:12 0 U 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 rd U
imm20 imm20:12 imm11:1 0 J 20 10 9 8 7 6 5 4 3 2 1 11 19 18 17 16 15 14 13 12 rd J
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
• Immediate bits mostly occupy consistent instruction bits.

• Simplifies hardware to build the microprocessor
• Sign bit of signed immediate is in msb of instruction.
• Recall that rs2 of R-type can encode immediate shift amount.
Composition of 32-bit Immediates Chapter 6: Architecture

Instruction Bits
funct7 4 3 2 1 0 rs1 funct3 rd R
11 10 9 8 7 6 5 4 3 2 1 0 rs1 funct3 rd I
11 10 9 8 7 6 5 rs2 rs1 funct3 4 3 2 1 0 S
12 10 9 8 7 6 5 rs2 rs1 funct3 4 3 2 1 11 B
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
20 10 9 8 7 6 5 4 3 2 1 11 19 18 17 16 15 14 13 12
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7
rd
rd
U
J Reading
31 31 31 31 30:25 24:21 20 I
Machine Language &
instruction bit
31 31 31 31 30:25 11:8 7 S
31 31 31 30 29:25, 11 10:7 0 B
31
31
30:20
31
19:12
19:12
0 0
20 21:16
0
15:12
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 U
0 J Addressing Operands
Immediate Bits
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Instruction Fields & Formats Interpreting Machine Code

Instruction op funct3 Funct7 Type
• Write in binary
add 0110011 (51) 000 (0) 0000000 (0) R-Type
sub 0110011 (51) 000 (0) 0100000 (32) R-Type
• Start with op: tells how to parse rest
and 0110011 (51) 111 (7) 0000000 (0) R-Type • Extract fields
or 0110011 (51) 110 (6) 0000000 (0) R-Type • op, funct3, and funct7 fields tell operation
addi 0010011 (19) 000 (0) - I-Type • Ex: 0x41FE83B3 and 0xFDA58393
beq 1100011 (99) 000 (0) - B-Type
bne 1100011 (99) 001 (1) - B-Type
0x41FE83B3: 0100 0001 1111 1110 1000 0011 1011 0011
lw 0000011 (3) 010 (2) - I-Type op = 51, funct3 = 0: add or sub (R-type)
sw 0100011 (35) 010 (2) - S-Type funct7 = 0100000: sub
jal 1101111 (111) - - J-Type 0xFDA48393: 1111 1101 1010 0100 1000 0011 1001 0011
jalr 1100111 (103) 000 (0) - I-Type op = 19, funct3 = 0: addi (I-type)
lui 0110111 (55) - - U-Type
See Appendix B for other instruction encodings
Interpreting Machine Code Addressing Modes

• Write in binary How do we address the operands?
• Start with op: tells how to parse rest • Register Only
• Extract fields
• Immediate
• op, funct3, and funct7 fields tell operation
• Base Addressing
• Ex: 0x41FE83B3 and 0xFDA58393
• PC-Relative
Machine Code Field Values Assembly
funct7 rs2 rs1 funct3 rd op funct7 rs2 rs1 funct3 rd op
sub x7, x29,x31
(0x41FE83B3) 0100 000 11111 11101 000 00111 011 0011 32 31 29 0 7 51
sub t2, t4, t6
imm11:0 rs1 funct3 rd op imm11:0 rs1 funct3 rd op

addi x7, x9, -38
(0xFDA48393) 1111 1101 1010 01001 000 00111 001 0011 -38 9 0 7 19
addi t2, s1, -38
12 bits 5 bits 3 bits 5 bits 7 bits 12 bits 5 bits 3 bits 5 bits 7 bits
24
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Addressing Modes Addressing Modes

Register Only Base Addressing
• Operands found in registers • Loads and Stores
– Example: add s0, t2, t3 • Address of operand is:
– Example: sub t6, s1, 0 base address + immediate
Immediate – Example: lw s4, 72(zero)
• 12-bit signed immediate used as an operand • address = 0 + 72
– Example: addi s4, t5, -73
– Example: sw t2, -25(t1)
– Example: ori t3, t7, 0xFF
• address = t1 - 25
Addressing Modes Chapter 6: Architecture

PC-Relative Addressing: branches and jal
Example:
Address Instruction
0x354 L1: addi s1, s1, 1
0x358 sub t0, t1, s7
...
0xEB0
...
bne s8, s9, L1 Compiling,
The label is (0xEB0-0x354) = 0xB5C (2908) instructions before bne
imm12:0 = -2908
bit number
1
12
0 1 0 0
11 10 9 8
1 0 1 0
7 6 5 4
0 1 0 0
3 2 1 0 Assembling, & Loading
(bne x24, x25, L1)

imm12,10:5 rs2
bne s8, s9, L1 1100 101
7 bits
24
5 bits
rs1 funct3 imm4:1,11
25
5 bits
1
3 bits
0010 0
5 bits
op
99
7 bits
imm12,10:5 rs2
1100 101 11000 11001
7 bits 5 bits
rs1 funct3 imm4:1,11
5 bits
001
3 bits
op
0010 0 110 0011 (0xCB8C9263)
5 bits 7 bits
Programs
25
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The Power of the Stored Program The Stored Program

• 32-bit instructions & data stored in memory Assembly Code Machine Code
add s2, s3, s4 0x01498933
• Sequence of instructions: only difference sub t0, t1, t2 0x407302B3
between two applications addi s2, t1, -14 0xFF230913
lw t2, -6(s3) 0xFFA9A383
• To run a new program:
Address Instructions
– No rewiring required
– Simply store new program in memory
0000083C F F A 9 A 3 8 3
• Program Execution: 00000838 F F 2 3 0 9 1 3
– Processor fetches (reads) instructions from memory 00000834 4 0 7 3 0 2 B 3 Program Counter
in sequence 00000830 0 1 4 9 8 9 3 3 PC (PC): keeps track of
current instruction
– Processor performs the specified operation
Main Memory
How to Compile & Run a Program What is Stored in Memory?

High Level Code
• Instructions (also called text)
Compiler
• Data
Assembly Code – Global/static: allocated before program begins
Assembler – Dynamic: allocated within program
Object Files
Object File
Library Files
Linker
• How big is memory?
– At most 232 = 4 gigabytes (4 GB)
Executable
– From address 0x00000000 to 0xFFFFFFFF
Loader
Memory
26
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Example RISC-V Memory Map Example Program: C Code

Address Segment int f, g, y; // global variables
0xFFFFFFFC
Operating
System & I/O int func(int a, int b) {
0x80000004
0x80000000 Stack sp if (b < 0)
return (a + b);
Dynamic Data
else
0x10001000 Heap
return(a + func(a, b-1));
0x10000FFC }
Global Data gp
void main() {
0x10000000 f = 2;
g = 3;
Text y = func(f,g);
0x00008000 return;
}
Exception
Handlers
0x00000000 pc
Example Program: RISC-V Assembly Example Program: RISC-V Assembly

Address Machine Code RISC-V Assembly Code Maintain 4-word Address Machine Code RISC-V Assembly Code
alignment of sp (for gp = 0x11DE0
10144: ff010113 func: addi sp,sp,-16 10180: ff010113 main: addi sp,sp,-16
compatibility with
10148: 00112623 sw ra,12(sp) 10184: 00112623 sw ra,12(sp)
RV128I) even though
1014c: 00812423 sw s0,8(sp) only space for 2 words 10188: 00200713 li a4,2
10150: 00050413 mv s0,a0 needed. 1018c: c4e1a823 sw a4,-944(gp) # 11a30 <f>
10154: 00a58533 add a0,a1,a0 10190: 00300713 li a4,3
10158: 0005da63 bgez a1,1016c <func+0x28> 10194: c4e1aa23 sw a4,-940(gp) # 11a34 <g>
1015c: 00c12083 lw ra,12(sp) 10198: 00300593 li a1,3
10160: 00812403 lw s0,8(sp) 1019c: 00200513 li a0,2
10164: 01010113 addi sp,sp,16 101a0: fa5ff0ef jal ra,10144 <func>
10168: 00008067 ret Pseudoinstructions: 101a4: c4a1ac23 sw a0,-936(gp) # 11a38 <y>
1016c: fff58593 addi a1,a1,-1 mv: addi a0, s0, 0 101a8: 00c12083 lw ra,12(sp)
10170: 00040513 mv a0,s0 ret (return): jr ra 101ac: 01010113 addi sp,sp,16
10174: fd1ff0ef jal ra,10144 <func> 101b0: 00008067 ret
10178: 00850533 add a0,a0,s0
Put 2 and 3 in f and g (and argument registers) and call func. Then put
1017c: fe1ff06f j 1015c <func+0x18>
result in y and return.
27
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Example Program: Symbol Table Example Program in Memory

Address Memory
0xFFFFFFFC Operating 0x00008067
Address Size Symbol Name 0x80000000
0x7FFFFFF0
System & I/O
Stack sp = 0x7FFFFFF0 0x01010113
00010074 l d .text 00000000 .text Dynamic Data 0x00c12083
0xc4a1ac23
000115e0 l d .data 00000000 .data 0x00022DC4
0x00022DC0
Heap
0xfa5ff0ef
00010144 g F .text 0000003c func y
g
gp = 0x00011DE0
0x00200513
0x00300593
00010180 g F .text 00000034 main 0x00011A30 f
0xc4e1aa23
00011a30 g O .bss 00000004 f
0x000115E0
0x00300713 Address of main:
0xc4e1a823
00011a34 g O .bss 00000004 g 0x00008067
0x01010113
0x00200713
0x10180
0x00c12083
00011a38 g O .bss 00000004 y 0xc4a1ac23

0xfa5ff0ef
0x00112623
0x00200513
0x00300593
0x00010180 0xff010113 pc = 0x00010180
0xc4e1aa23
0x00300713
0xfe1ff06f
0xc4e1a823
0x00850533
• text segment: address 0x10074 0x00010180
0x00200713
0x00112623
0xff010113 pc = 0x00010180
0xfd1ff0ef
• data segment: address 0x115e0 0xfe1ff06f
0x00850533
0x00040513
0xfd1ff0ef 0xfff58593
• func function: address 0x10144 (size 0x3c bytes) 0x00040513
0xfff58593
0x00008067
0x00008067
• main function: address 0x10180 (size 0x34 bytes) 0x01010113
0x00812403
0x01010113
0x00c12083 0x00812403
• f: address 0x11a30 (size 0x4 bytes) 0x0005da63
0x00a58533 0x00c12083
0x00050413
• g: address 0x11a34 (size 0x4 bytes) 0x00812423

0x00112623
0x0005da63
0x00010144 0xff010113 0x00a58533
• y: address 0x11a38 (size 0x4 bytes) ...
... 0x00050413
...
0x00010074 0x00812423
Exception
Handlers
0x00112623
0x00010144 0xff010113
28

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12/4/2022

Once you’ve learned one architecture, it’s easier to learn others

2 Digital Design & Computer Architecture Architecture

Architecture Design Principles

1.Simplicity favors regularity

3 Digital Design & Computer Architecture Architecture

Instructions: Addition Instructions: Subtraction

C Code RISC-V assembly code C Code RISC-V assembly code

• add: mnemonic indicates operation to perform • sub: mnemonic

Design Principle 1 Multiple Instructions

• Easier to encode and handle in hardware

9 Digital Design & Computer Architecture Architecture

Operands Operands: Registers

Design Principle 3 RISC-V Register Set

RISC-V Instruction Set Operands: Registers

Instructions with Registers Instructions with Constants

C Code RISC-V assembly code C Code RISC-V assembly code

# indicates a single-line comment

Memory Operands • Commonly used variables kept in

20 Digital Design & Computer Architecture Architecture

Memory Byte-Addressable Memory

RISC-V is byte-addressable 13 12 11 10 00000010 C D 1 9 A 6 5 B Word 4

Reading Byte-Addressable Memory Reading Byte-Addressable Memory

• RISC-V is byte-addressed, not word-

Writing Byte-Addressable Memory

Word Address Data Word Number

Generating 12-Bit Constants Generating 32-bit Constants

Logical / Shift – or: useful for combining bit fields

30 Digital Design & Computer Architecture Architecture

Logical Instructions: Example 1 Shift Instructions

Immediate Shift Instructions

• slli: shift left logical immediate

33 Digital Design & Computer Architecture Architecture

mul s3, s1, s2 – div s3, s1, s2 # s3 = s1/s2

Branches & Jumps •

38 Digital Design & Computer Architecture Architecture

Conditional Branching The Branch Not Taken (bne)

target: # label target:

Labels indicate instruction location. They can’t be reserved words and

Unconditional Branching (j)

Statements & Loops

41 Digital Design & Computer Architecture Architecture

Conditional Statements & Loops If Statement

bne s3, s4, L1

Assembly tests opposite case (i != j) of high-level code (i == j)

If/Else Statement While Loops

C Code RISC-V assembly code C Code RISC-V assembly code

Assembly tests opposite case (pow == 128) of high-level code

For Loops For Loops

Less Than Comparison Less Than Comparison: Version 2

slt: set if less than instruction

52 Digital Design & Computer Architecture Architecture

Arrays Accessing Arrays

element, array[0]) 123B4784

# 0x123B4 in upper 20 bits of s0

Address Data lw t1, 0(s0) # t1 = array[0]

# RISC-V assembly code

ASCII Code Cast of Characters: ASCII Encodings

Accessing Arrays of Characters Chapter 6: Architecture