L-2/T-l/CSE Date: 24/12/2012

BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY, DHAKA

L-2/T-l B. Sc. Engineering Examinations 2011-2012

Sub: CSE 205 (Digital Logic Design)

Full Marks :210 Time: 3 Hours

The figures in the margin indicate full marks.
USE SEPARATE SCRIPTS FOR EACH SECTION

SECTION-A
There are FOUR questions in this section. Answer any THREE.

(12}
(4)

(d) Show the logic diagram and function table of an SR latch with NAND gates. (4)

2. (a) Develop a synchronous3-bit counter with a Gray code sequence using JK flip-flops.

(Hints: Gray code count sequence for a 2-bitcounter is: 00,01, 11, 10,00,01, ..... ) (18)
(b) Draw the logic diagram of a serial adder. Show the values of inputs and outputs of all
components (e.g., flip-flop, register) used in the design after every clock pulse while

adding the following two numbers 0101 and 0011. (6+6)

(c) Draw the logic diagram of a four-stage switch-tail ring counter. (5)

3. (a) Draw and explain a four bit binary count up ripple coUnter with T flip-flops. (12)
(b) Convert a D-flip-flop to a T-flip-flop. Use necessary gates. (4'li)

(c) Derive the characteristic table and the characteristic equation for a JK flip-flop. (4)
(d) Implement the following three Boolean functions with a PLA: (15)

PI =L(O, 1,2,4)
F2= L (0,5,6, 7)
. F3 = L(O, 3, 5, 7)
Contd P/2
 'S.'--"-
'"
~\.

=2=

.CSE205

4. (a) A specification is given below for a gated latch circuit with two inputsG and D and

an output Q. Assume fundamental mode operation. (6+6)

"Binary information present at the D input is transferred to the Q output when G is
equal to 1. The Q output will follo~ the D input as long as G = 1. When G goes to 0,
the information that was present at the D input at the time the transition occurred is
retained at the Q output".
Derive the primitive flow table and then obtain the reduced flow table.
(b) What is a race in fundamental mode circuits? Explain critical and non.;critical races

with example. (4+8)

(c) Write down the procedure to assign the output to unstable states in a flow table. (7)
(d) Write down the restricti~ns on the duration of input for pulse modeasyrtchronous

circuits. (4)

SECTION-B
There are FOUR questions in this section. Answer any THREE.

5. (a) Design a circuit that takes a 4.;bit number as input and produces the 2's complement of

the given number. (20)

(b) Using the two-level forms of logic (i) NOR-OR, and (ii) OR-NAND, implement the

following Boolean function F: (6+6)

F (A, B, C, D) = 2: (0, 4,8,9, 10, 11, 12, 14)
Assume that both the normal and complement inputs are available.

(c) Define prime implicants. (3)

6. (a) Design a 4-input priority encoder and show the gate level circuit diagram. (12)
(b) Design a 3-8 decoder using two 2-4 decoder circuits. (8)
(c) Implement the following function F using one 4xl multiplexer and basic gates: (15)
F (A, B, C, D) = L (1,3,4, 11, 12, 13, 14,15)

7. (a) Design a 4-bit incrementer circuit by using 4 half-adders. Note that the incrementer

circuit adds '1 to a binary number. (10)

(b) The Boolean expression for an X-OR gate isAB'+ A'B. With this as a starting point,
use DeMorgan's theorems and other rules or laws to find a simplified expression for an

X-NOR gate. (8)

Contd P/3

\
{. 0
 =3=

CSE205
Contd ... Q. No.7

(c) Analyze the following circuit and determine the output F as sum of minterms and

product to maxterms. . (9)

(d) Give an example of the non-associativity of the 3-input NOR operator. (8)

8. (a) Simplify the following Boolean function by using the tabul~tion method: (15)
F (A, B, C, D) = L (0, 1,2,8, 10, 11, 14, 15)

(b) Convert (41.6875)10 to binary. (5)

(c) Perform the subtraction with the following binary unsigned numbers using (i) 2's

complement, (ii) 1's complement: 11010-1101. (10)

.
(d) Prove that x(x + y) = x. (5)

---------------------------------------------

.(
 .~. "

L-2/T-lICSE
~. ~
Date: 19/05/2014
BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY, DHAKA
L-2/T-l B. Sc. Engineering Examinations 2012-2013
Sub: CSE 205 (Digital Logic Design)
Full Marks: 210 ' Time: 3 Hours
USE SEPARATE SCRIPTS FOR EACH SECTION

..._ __ _---_._ __ The figures in the margin indicate full marks .

_ -_ _--_. __ .--'---._ -..__ _-- _--- - _-_ ..
, _ --_ _--_._._-
.. ..

SECTION-'A
There are FOUR questions in this section. Answer any THREE.

1. (a) Derive the state diagram from the following sequential circuit. (15)

Q ~I

C
K1 Q -
11.

Clock
Figure for question lea)

(b) Explain the undefined cpndition in SR flip-flops. How is this problem solved in JK
flip-flops? , (4+4=8)
(c) Explain how Ripple-blanking input (RBI) and Ripple-blanking output (RBO) pins of
the BCD to 7-segment decoder (IC 7447) should be connected such that all but the LSB
should show blank for leading zeros. (6)
(d) What are the advantages and disadvantages of using Meal¥ Model and Moore Model
for sequential circuit design? (6)

2. (a) Design a synchronous counter with the following binary sequence 0, 1,3, 7, 6, 4 and
repeat. Use T flip-flops. (15)
(b) Draw the, state diagram in Moore model of a synchronous sequential circuit that
results in an output of 1 whenever the sequence 10011 occurs. The circuit is required to
recognize overlapping sequence. (8)
(c) Draw the logic diagram of a serial adder. Show the values of inputs and outputs of
all the registers used in your design alter every clock pulse while adding the following
two number~ 0101 and 0011. (8+4=12)
Contd .....•.... P/2
 <>-

=2= ",
CSE205

3. (a) (i) Design a modulo-6 3-bit Asynchronous (ripple) up counter with positive edge

triggered JK flip-flops. (8+4+3=15)

(ii) Show the Timing diagram for the above designed counter.
(iii) What are the problems of the above counter?

(b) Draw the circuit diagram of a 4-bit universal shift register using JI< flip-flops. (12)
(c) Convert a T flip-flop into a JK flip-flop and vice versa. (4+4=8)

4. (a) Using an implication table, reduce the following state table to a minimum number of

states and write the reduced state table. (17)

"

X
0 1
A E/O DIO ,
B All FlO
C CIO All
D BIO AlO

E DII CIO
F CIO DII
G ;
Hli Gil
H CII Bil

(b) Minimize the following function in both SOP and POS forms using Kamaugh map. . (12)

f(A, B, C, D)= Im(O, 4, 7, 9, 13)+d(5, 8, 15)

(c) What are the problems that may occur when redundant states are present in the, state
diagram? (6)

SECTION-B
There are FOUR questions in this section. Answer any THREE.

5.. (a) State and prove De Morgan's theorem using truth table. (10)
(b) Given the Boolean function F = xy + x)/ + y'z , implement it with (i) AND, OR and

NOT gates, (ii) only NAND gates. (5+5=10)

(c) (i) What are the differences between canonical form and standard form? (8+4+3=15)
(ii) Which form is preferable when implementing a Boolean function with gates?
/' Why?

(iii) Which form is obtained when reading a function from a truth table?

Contd P/3
 • '.1

=3=
~SE205

6. (a) Implement F= 2:(3,5, 7,10,11,13,14,15) using 16-to.-l MUX. (10)

(b) Can the function in 6(a) be implemented by using only one 4-to-l MUX? If yes,

show how; if not, explain why. (10) I

(c) You need a full adder for an experiment. But in lab you could not find a full adder,
. instead you found plenty of 3-to-8 decoders. Can any such decoder be used as a full

adder? Explain your' answer with truth table. ' (15)

7. (a) Starti~g with truth table, design a full subtractor. (20)

(b) Using 2's complement, subtract decimal-70 from decimal-50. - (9)

(c) Perform the following binary subtraction: (6)

11000011-10101010

8. (a) You are receiving BCD codes sent by a remote transmitter. The bits are A3A2AtAo;
Ao being the LSB. You intend to include a BEb (BCD-error-detector) in your receiver
that examines the received codes to see if it is a legal BCD code. Design a BED for your
receiver that will produce a HIGH for any received code that is not a valid BCD code.

For example, if you

. receive 1010, the output of BED will be high.
.
(15)
(b) The figure below represents a multiplier .thar takes two 2.bit binary numbers XIXO
and YIYO as inputs, and produces an output binary number P3P2PIPO that is equal to the
.
arithmetic 'product of the two input numbers. Design the logic circuit for the multiplier. (20)

-------------------1---~---~r-~----
,.'
L-2/T-lfCSE Date: 1510112015
BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY, DHAKA
GUT -1 B. Sc, Engineering Examinauons 2013-2014

Sub; CSE 205 (Digital Logic Design)

Full Marks: 210 Time: 3 Hours

The ligures in the margin indicate full marks.
USE SEPARATE SCRIPTS FOR EACH SECTION

SECTION~A
There are FOUR questwns in this section, Answer any THREE.

1. (a) SimplifY the following Bookan functions, using K-mar; (15)

(il F(A,B,C,D)= AB'C + A'B'D' + ABD + ACD' + AB'C' + A'BCD
(ii) f(A,B,C,D)=(O, 2, 5, 7, 8, 15) which has the don't-care conditions: d(A, B, C, D)
=(10,14).
(b) 'NOR gate and NAND gate are univ=al gate' - justify the claim. (5)

(c) What is plionly Encoder'? Design a four-input priority encoder with inputs 10, II, 12,

and 13, where, the priority order is U, 13, 11, 10. (10)

(d) Define Odd Ftmction. Even Function, Don't-care conditions. (5)

2. (a) Design a four bit binary adder using I-bit full-adder circuit. How can it be modified to

use as a four bit subtractor. (15)

(b) How to check overtlow in case of addition of two Binary o<ll1tbcrs 10 both signed and

unsigned representations. (5)

(c) An 8xl multiplexer has inputs A, D, C, D where, inputs A, Band C arc connected to

the selection inputs S2, 51 and SO, respectively. The data inputs 10 through 17 are as
follows: II = 12 = 0; 13 = 17 = I; 14 = 15 = D; and IO = 16 = D'. Determine the Boolean

function that the mllltiplexer implements. (15)

3. (a) Design a 3-bit synchronous binary up counter that counts 1-2-4-7-1- ... , where any
invalid state goes to the immediate next state in the sequence. Use J.K flip flop for your
design. Show the state table, ,tate diagram, funchon minimization (if neces"ary). and

circuit diagram of your design. (20)

(b) Design a serial subtractor that subtracts the content ofB from the content of A where the
content of A and B are ,lored in the individual shift regJsters. The result of the subtraction is

stored in the shift register representing A. (Both A and B arc 4-bit binary numbers). (10)

(0) ,~Vritethe differences between lateh and flip-flop (5)

Contd. . . Pi2
 =2'"

CSE 205

4. (a) What is the advantages of eLA over normal binary four bIt adder? Assume that th~
exclusive-OR gate has a propagation delay of 10 ns and that the AND or OR gates have a
propagation delay of 5 ns. What is the total propagation delay time in the four-bit eLA
adder? (10)
(b) Construct a 16 x 1 multiplexer with two 8 x 1 and one 2 x 1 multiplexers. (5)
(c) What problem may occur when redundant states arc present m the state diagram? (5)
(d) Usmg an implication table, reduce the following state table to a minimum number of
states and write the reduced state table, (15)
Next State Output
Present State , 0 ,1 , 0 , 1
A F B 0 0
B D C 0 0
C F E 0 0
D G A 1 0
E D C 0 0
F F B 1 1
G G H 0 1
H G A 1 0

SECTION-8
There are FOUR questions in this section. Answer any THREE.

5. (a) Simplify the following Boolean expressions 10 a minimum number of literals using
Boolean algebra: (5x2=10)
(i) AB + A (CD + CD') -t A'
(ii) (A + B)" (A' + B')'
(b) Given Dc Morgan's theorem for two variables: (A -'-B)' = A' + It, prove De Morgan's

theorem for three variables by successive substitution. (10)

(c) You are given two numbers: (J05.EJi6 and (J09.6875Jio (5x3=15)
(i) Convert the given numbers into binary
(ii) Subtract the later number from the fonner using binary arithmehc
(iii) Convert the result of the subtraction into octal

6, (a) How would you implement a one-bit by one-bit binary multiplier using basic gates~ (5)
(b) Implement the following Boolean function together with the don't care conditions
using only two-input NOR gates (complement oflitcrals are available as input): (15)
F(A,B, C.D) = £(0,],9,11) and d(A,B,C.D) =I(2,8,lO,14.15)

(c) Given function F = A'B -'-BC + .'Ie (5x3=15)

(i) Implement F using AND, OR and NOT gates
(ii) Minimize F ill SOP form using K-Map
(iii) Implement the minimilcd F using only NAND gates
Conld Pi3
f
=J=
CSE 205

7. (a) Design the circuit corresponding to the state diagram from Fig. for Q, 7(a), using l

flip-flops: (21)
(il Write the stale table
(ii) Find the input equations for the T flip-flops

(iii) Draw the cin:uit diagram

o

o(
k5~~o 1 \ •

~ 1~1
1( /
O&y1.
Figure for question 7(a)

(b) Convert (il aJK flip-flop into a T flip-flop and (Ii) a D flip-flop into a JK flip-flop. (4x2=8)

(c) Draw the block diagrams of Mealy and Moore finite state machines. (3x2=6)

8. (a) You have several 32 x 4 RO),i\s in luboratory. Each ROM can be enabled/disabled

using a 110 signal respectively. How would you implement a 128 x 4 ROM using the

available ROMs? You can use any additional circuitry if needed. (10)
(b) Derive the PLA program table for a combmational circuit that squares a 3-bit binary

number. Minimize the number of product terms. (25)

,
 L-2/T-1/CSE Date: 31/01/2016
BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY, DHAKA
L-2/T-l B. Sc. Engineering Examinations 2014-2015

Sub: CSE 205 (Digital Logic Design)

Full Marks: 210 Time: 3 Hours

USE SEPARATE SCRIPTS FOR EACH SECTION
The figures in the margin indicate full marks.

SECTION -A
There are FOUR questions in this section. Answer any THREE.

1. (a) Find all the prime implicants for the following Boolean function and determine
which are essential:
(11)
F(A, B, C, n)= 2:(0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15)

(b) Implement the function F (w, x, y, z) = w' x' + w' x'z + w'yz' using two-level forms of

logic by
(20)
(i) NOR gates only
(ii) AND-NOR,
(iii) NAND gates only, and
(iv) OR-NAND.

(c) A decimal number N is represented in a weighted binary code as 0011 0100 1010
1100. Write the decimal digits of N, if the following weights are used for the weighted
binary code: 6,3, 1, 1.
(4)

2. (a) Show the truth table for the following function:

(8)
F(x,y,z)= (x+ y+z)(x+ y+z')(x+ y' +z)(x' + y+z)

(b) Design a full adder with a decoder and basic logic gates. (12)
(c) Simplify the following function using Boolean algebra
(7)
F (A, B, C) = A'BC + AB'C + ABC
(d) State and prove consensus theorem using Boolean algebra. (8)

3. (a) When is the tabulation method more preferable than the K-Map method for
simplifying a Boolean function?
(5)
(b) Convert (0.625)10 to binary. Show every step of your calculation. (4)
(c) Design a combinational circuit with 3 inputs: x, y, and z, and 3 outputs: A, B, and C.
When the binary input is 0, 1, 2, or 3, the binary output is two greater than the input.

When the binary input is 4, 5, 6, or 7, the binary output is three less than the input. (18)
(d) Show the truth table for a three-state buffer. Construct a 2-to-l line MUX with
three-state buffers.
(3+5=8)
Contd P/2
 =2=

CSE 205

4. (a) Detennine the output functions A as the sum of minterms and the output function B

as the product of maxterms: (16)

o
1 4x 1
A
2 MUX.
3

o 0
1 4x 1
B
MUX

'.
I
__ . __
. Figure
...-.=o""""-"'-"'~"'-'---'
. :
for Question 4(a) ,.

(b) Design a 4-bit BCD add~r using 4-bit binary adders and basic logic gates. Use a .

block diagram to draw a binary adder. (15)

(c) An Octal to Binary Encoder may cause ambiguities if more than one inputs are

simultaneously set to 1. How can this ambiguity be resolved? (4)

SECTION -B
There are FOUR questions in this section. Answer any THREE.

5. (a) What do you understand by mechanical switch contact bounce? Describe how S'R'

latch can eliminate mechanical switch contact bounce. (10)

(b) Design a SR Flip-Flop using a D Flip-Flop and a 4 x 1 MUX. (10)
(c) A sequential circuit has two JK Flip-Flops A and B, two inputs x and y, and one

output z. The Flip-Flop input equations and circuit output equation are given below: (15)
JA = Bx+B'y' KA =B'xy'
JB =A'x KB = A+xy'
z = Ax);' + Bx'y'
Now draw the logic diagram of the circuit, tabulate the state table and derive the state
equations for A and B.

Contd P/3
•

=3=

CSE 205

6. (a) For the following primitive flow table shown III Fig. for Q. 6(a) answer the

following questions: (10+5+5=20)

(i) Find all compatible pairs by means of an implication table.
(ii) Find the maximal compatibles by means of a merger diagram.
(iii) Find a minimal set of compatibles that covers all the states and is closed.

-----,--.- ---.-...,.-....- ~_._-.~ - ----

.OO;:~OV<
. .
a @,O b ,-

b a ,-

g a ,.-

h a,-
Fig. for Q. 6 (a)

(b) Design a 3-bit synchronous Gray Code Counter. Use JK Flip-Flops for your design.
Show the state diagram, state table, function equations and the circuit diagram of your

design. (15)

7. (a) Investigate the transition table of Fig. for Q. 7(a) and determine all race conditions
and whether they are critical or noncritical. Determine also whether there are any

cycles. --~---- -_ .. -_ ..• _.~~-_._-_.- (10)

00 01 ]0
J"tY2
00 H) @ 11 10

01
e ,
00 10 10

11 01 00
:
(2) 0
10 , U.
..
: "':00.
.,.
'.'
e
.. "
0
.' .

---------_
'.

.. -

Contd P/4
 t-

•
=4=

CSE 205
Contd ... Q. NO.7

(b) Find a critical race-free state assignment for the reduced flow table shown in Fig. for

Q. 7(b) using Multiple-row method. (10)

\
(
A ;
I )

Fig. for Q. 7 (b)

(c) Write the difference between ROM and PLA. A combinational circuit is defined by

the following functions: (5+10=15)

F1(A, B, C)= I (0, 1,2,4)
F2(A, B, C)= I (0, 5, 6, 7)

Implement the circuit with a PLA having three inputs, four product terms and two
outputs.

8. (a) Design a 4-bit Ripple counter using D Flip-Flops and briefly explain its operation. (10)
(b) Design a 4-bit Johnson Counter. What is the disadvantage of Johnson Counter?

What is the difference between Johnson Counter and Ring Counter? (10)
(c) Design a 3-bit binary up counter that counts 1-2-5-7-1..., where any invalid state
goes to the immediate next valid state in the sequence. Use T Flip-Flops for your
design. Show the state diagram, state table, function equations, function minimization

(if necessary) and the circuit diagram of your design. (15)

L-2/T-1/CSE Date: 01/08/2016
BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY, DHAKA
L-2/T-l B. Sc. Engineering Examinations 2015-2016

Sub: CSE 205 (Digital Logic Design)

Full Marks: 210 Time: 3 Hours
The figures in the margin indicate full marks.
USE SEPARATE SCRIPTS FOR EACH SECTION

SECTION -A
There are FOUR questions in this Section. Answer any THREE questions.

1. (a) Design an one-input, one-output serial 2's complementer using D flip-flops. The

circuit accepts a string of bits from the input and generates the 2's complement at the
output. The circuit can be reset asynchronously to start and end the operation. The design

must include (15)

(i) State diagram
(ii) State table
(iii) Simplified logic equations
(iv) Logic diagram
(b) Draw the block diagram and explain the operation of a Master-Slave negative edge

triggered D flip-flop. (12)

(c) Draw the block diagram of Mealy and Moore state machines. (8)

2. (a) Write the excitation table for a SR latch constructed with NOR gates. (4)
(b) For the Programmable Logic Array (PLA) shown in Figure 1, find the function

expressions for Fl and F2 and show the PLA programming table. (13)

Figure 1

Contd P/2
 =2=

CSE 205
Contd ... Q. No.2
(c) Consider the sequential circuit shown in Figure 2. Let the current values of parameters

are as follows: CLK = 1, D = 1, Q = 1, Q = O.Now if the value ofD changes from 1 to 0

after the "Hold Time" ends and CLK remains unchanged at 1, what will be the values of

Q and Q? (6)

Q
eLK

'D

_________ .__ F_igure2

(d) You are given a state table of a synchronous sequential circuit in Figure 3. Find the

reduced state table using the implication table. (12)

Present Next State. ;., Output

State x=O x=1 x=O x=1
a d b 0 0
b e a 0 0
c g f 0 .1
d a d 1 0
e a d 1 0
f c b 0 0 ,
g a e 1 0
______________ F_ig1.1re
3

3. (a) You are given a 4 bit binary counter as shown in Figure 4. Show two ways to design a
Modulo-6 counter using the given binary counter and necessary basic gates. The Modulo-

6 counter repeatedly goes through 0, 1,2,3,4,5. (12)

C<lflltl -
Load
.1

il..corlltf

Clmr
eLK

Contd P/3
 =3=

CSE 205
Contd ... Q. No.3

(b) Draw the logic diagram of a two-bit register with two D flip-flops and two 4 x 1
multiplexers with mode selection inputs sl and sO. The register operates according to the

function table shown in Figure 5: (12)

sl sO Register Operation
0 0 No change
0 1 Complement the two output
1 0 Clear register to 0 (Synchronous with the clock)
1 1 Load parallel data
Figure 5
(c) A counter circuit is shown in Figure 6. VDD is assigned to Logic 1 and assume that the
current values of LSB Qo and MSB QI are equal to 0 and 1, respectively. Find the
direction (up or down) in which the circuit counts when the next clock pulse occurs.

What would have to be altered to make the circuit count in other direction? (7)

Qo QI
VDD

J Q J Q
I
C C
Clock
K K

Figure 6 f'"

(d) Write the advantages and disadvantages of serial and parallel adders. (4)

4. (a) What does it mean when an asynchronous sequential circuit is assumed to operate in

the fundamental mode? (4)

(b) Derive the primitive flow table for a negative-edge triggered T flip-flop. (12)
(c) An asynchronous sequential circuit is described by the following excitation function:

Y = X1X'2 + (XI + X'2)Y. (10)

Draw the logic diagram of the circuit and derive the transition table.
(d) What is static-I hazard? Give an example of static I-hazard in an asynchronous

sequential circuit. (5)

(e) Write down the procedure to assign the output to unstable states in the flow table. (4)

Contd .. ~ P/4
 =4=
CSE 205
SECTION -B
There are FOUR questions in this Section. Answer any THREE questions.

S. (a) Prove the following Boolean algebra theorem: (x + y )(~ + z )(y + z) = (x + y )(~ + z). (10)
(b) How many distinct Boolean functions are there of n Boolean variables? (5)
(c) Show that NAND gate is a universal logic gate. Also show that NAND operation

doesn't follow associative law. (5+5=10)

(d) Simplify the Boolean function using algebraic manipulation: (10)

f = ABC + ABC + ABC + ABC

6. (a) Implement the following Boolean function using only NOR gates: j = xy+ yz. Your

implementation should use as few NOR gates as possible. (6)

(b) Show that XOR operation is not distributive over AND operation. (7)
(c) Using K maps, find the simplified product of sums form of the following Boolean

function: j(w, x, y, z)= I(l,S,8,l2,14,IS), where don't care minterms are 3 and 11. (10)

(d) Design and implement the circuit diagram of a I-bit full subtractor circuit using 2 x 1

MUXs only. You can't use any other gates. (12)

7. (a) Consider a 3 x 8 decoder whose outputs are active low and which has one active high

enable signal. Implement the following functions using the above mentioned decoder: (13)
(i) f(a,b,c,d)=n(3,S,14) (ii) f(a,b,c,d)= I (1,6,8,13)

Note that you will need to implement both functions in a single circuit. You can use as
many decoders as you require keeping your implementation as efficient as possible. You
are allowed to use other basic gates as well.
(b) Using K maps, find the simplified sum of products form of the following Boolean

function: (12)
f(a,b,c,d,e,j)=I(1,2,3,S,7,11,13,17,19,23,29,31), where the don't care minterms are

6,20,24, 2S, 26, and 27.

(c) Why is the XOR operation called odd function? Convert the following Boolean

expression to a canonical maxterm form: a EJ b @ c 0 d. (10)

8. (a) What is the problem with the binary parallel adder circuit? Design and implement a 4-
bit carry look-ahead adder circuit. If the propagation delay is Ins for a NOT gate, and 2ns
for other basic gates, what is the propagation delay of your carry look-ahead adder circuit

to product its final output? (18)

(b) Consider the Boolean functionf(w, x, y, z)= n(2,4,S, 7,11,12,13). Implement the

function using a 4 x 2 MUX and other basic gates if necessary. (10)

(c) Simplify the Boolean function using algebraic manipulation: (A + BC)+ ijj. (7)
L-2/T-lICSE Date: 09/08/2017
BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY, DHAKA
L-2/T -1 B. Sc. Engineering Examinations 2016-2017

Sub: CSE 205 (Digital Logic Design)

Full Marks: 210 Time: 3 Hours

USE SEPARATE SCRIPTS FOR EACH SECTION
The figures in the margin indicate full marks.

SECTION -A
There are FOUR questions in this section. Answer any THREE.

1. (a) f(A,B,C,D,E)= I(0,1,2,8,9,15,17,21,24,25,27,31). Minimize the function fusing

Q-M method. Find essential prime implicants and prime implicants. (20)
(b)Design a negative logic 4 bit parity checker and generator. (6)
(c) Using NOR gate solve pl\ (qvr) 1\((Pl\q)-H). (5)
(d) What is the difference between r's and (r-1)'s complement? (r is the base) (4)

2. (a) Using 4 bit adders design a 3 bit multiplier whereas 3 bit variables are X(X1, X2, X3)

and Y(Y1, Y2, Y3). Explain the design. (15)

(b) Design a circuit which computes A-B and A+B when the circuit inputs are A and

B. A and B are of 4 bit BCD value. Explain the design. (15)

(c)For a carry look-ahead adder circuit what advantage do we get if we use it instead of
a 4 bit simple full adder? For "not" gate with 2 ns propagation delay and other basic

gates with 4 ns propagation delay what will be the total propagation delay? (5)

3. (a) "A lower order code will get priority" - Design and explain a priority encoder

with negative enable for 9 bits. (10)

(b) Using only 2 to 4 line decoder solve a function f(A,B,C,D)= 1t(3,5,9,15,12,4,1)
2x4 line decoder has active low enable and outputs are active low. (if gates are

required then use the minimum No. of gates) (10)

(c) How can be a decoder used as a demultiplexer? Explain with an example. (5)
(d) Design and explain a 2 bit magnitude comparator. (10)

4. (a) Using k-map solve j(x1 ,X2,X3 ,x4 ,xs) = I (0,2,4,5,6,7,8,10,14,17,18,21,29,31)+

dI (11,20,22). Find essential prime implicants. (Show the reduction steps). (15)

(b) Using only 4 to 1 line 2 bit multiplexers design j(w,x,y,z)=1t(2,4,5,7,11,12,13).

(if gates are required use the minimum number of gates) (12)
Contd P/2
 =2=
CSE 205
Contd ... Q. No.4

(c) Design a Binary to Excess-3 converter using the following logic circuit. (8)

A LOj~ e.
13 c;-r-~ y
C-
D

FEN
"l.1 't. 0

If x1xo = 00 A's value will go to Y

If x1xo = 01 Y will have B's value

If x1xo = 10 Y will have C's value

If x1xo = 11 Y will have D's value.

SECTION-B
There are FOUR questions in this section. Answer any THREE.

5. (a) A sequential circuit has two JK Flip-Flops A and B, two inputs x and y, and one

output z. The flip-flop input equations and circuit output equation are: (4+7+4=15)
JA =A.x+B.y

KA =A.B+x.y

JB =A.x

KB = A.B.x+ B.y
z = A.x.y + B.x.y
For the above mentioned circuit,
(i) Draw the logic diagram of the circuit.
(ii) Derive the state table.
(iii) Draw the state diagram.
(b) Design a clocked sequential circuit that recognizes the input sequence 1010,
including overlap such that for input x = 01010100011 0 100 10100 the con-esponding
output is z = 00001010000001000010. Design 1he circuit using T Flip-Fbps and basic

gates. (20)

Contd P/3

:~,: I .'. '._,

 =3=
CSE 205

6. (a) Draw the logic diagram of a 3-bit universal shift register with mode selection inputs

S2,s( and so. The register operates according to the following function table: (15) .

Mode Control Register

S2 SI So Operation

0 0 0 No change
0 0 1 Invert all bits
0 1 0 Set all bits to 0
0 1 1 Set all bits to 1
1 0 0 Parallel load
1 0 I Shift left
1 1 0 Shift right
1 1 1 .No change

(b) Design a JK Flip-Flop using a T Flip-Flop and basic gates. (10)

(c) Design a serial adder that computes the sum of two 4-bit binary numbers A and B
stored in individual shift registers. The result of the addition is stored in the shift
register representing A. Use sequential logic design procedure to design the serial

adder. (10)

7. (a) An asynchronous sequential circuit has two internal states and one output. The two

excitation functions and one outputfunction describing the circuit are, respectively, (15)

Z=X2 + Y1
Draw the logic diagram of the circuit and derive the transition table.

(b) Consider the following transition table:

XIX2
y 00 01 11 10

0 @) @ 1 @
1 0 CD CD CD
Design the circuit with NAND SR latches and gates.

(c) What is race condition? Explain different types of races with examples.
'~~
0..
(10)
r

Contd P/4
 •

=4=
CSE 205

4. (a) You are given the following state table of a synchronous sequential circuit. (12+3=15)

Present Next State Output

State x=O x =1 x=O x =1
a a c 0 0
b d a 1 0
c f f 0 0
d e b 1 0
e g g 1 0
f c c 0 0
g b h 1 0
h h c 0 0

(i) Find the reduced state table using an implication table.

(ii) Draw the equivalent minimized state diagram.

(b) Design a synchronous counter with the sequence given below: (10)
1~4~5~7~2~1
You need not take any measure for the unused states.
(c) A MOD-12 counter counts from 0000 to 1011. Design the MOD-12 ripple counter

with positive edge-triggered JK Flip-Flops and basic gates. (10)

~

}-':I
/ •.
"

L-2/T-lICSE Date: 26/10/2019

BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY, DHAKA
L-2/T- I B. Sc. Engineering Examinations 2018-2019

Sub: CSE 205 (Digital Logic Design)

Full Marks: 210 Time: 3 Hours

The figures in the margin indicate full marks
USE SEPARATE SCRIPTS FOR EACH SECTION

SECTION-A
There are FOUR questions in this section. Answer any THREE questions.

1. (a) Design a security lock using PLA which will be opened using the following

combinations. (12)

A(x,y,z)= I(I, 3, 5, 6)
B(x,y,z)= I(O, I, 6, 7)
C(x,y,z)= I(3, 5)
D(x,y,z)= I(I, 3, 4, 5, 7)
(b) Express f(A,B,C,D)= I(O, 4, 8, 9, 10, 11, 12, 14) with the two level forms of

logic "NAND-AND" and "OR-NAND". (6)

(c) Using K-Map minimize f(w,x,y,z)= I(I, 2, 3, 7, 10, 12, 14)+d(0, 6, 8, 13). Find

the Prime lmplicanls and Essential Prime lmplicants. Write down the responsible

minlerm for each Essential Prime lmplicanls. (12)

(d) Simplify the following expression to POS and SOP. (5)
A CD' + CD + AB' + ABCD

2. (a) Design a logic circuit which return the smaller value between two 4-bit binary

numbers A and B. Show the operation with input A = 7, B = 9. (12)

(b) Using 4-bit binary adder and XOR gate design a circuit which takes two 4-bit BCD
inputs A and B, and return A + 1 if input is 00, A' if input is 01, A' + I when input is 10

and A when input is 11. (13)

(c) Design a circuit with 4-bit binary adder which returns A x B. A and Bare 3-bit

binary numbers. (10)

3. (a) Design a logic circuit for f(w,x,y,z)= I(O, 2, 6, 7, 10, 11, 12, 14), with 2-4 line

decoder which has A, B as input lines, decoder is enabled by active low enables EN]'

and EN2' (use the minimum number of extra logic gates). (14)
(b) Design a 8 to 3 priority encoder with the priority order of data input is given as, 5,

0, 7, 4, 6, 3, 2, 1 (5 has the highest priority and 1 has the lowest priority). (13)
(c) Show that a decoder can be used as a demultiplexer. (8)
Contd PI2
 =2=
CSE 205

4. (a) What are the differences between an odd parity checker and odd parity generator? (8)
(b) Using 4xl line MUX design a logic circuit for f(w, x,y, z) = 0(0,2,5,6,7,8,9, 10),

where the MUX has selector bits So, Sf, input lines /0, hh h and enables EN!' is
active low and EN2 is active high. (If S2S1 = 00, /0 is selected; if SISO = 01, /1 is

selected; S1S0= 10, /z is selected; so on.) (15)

(c) Design a I bit Full Subtractor using 4xl multiplexer (MUX).
The MUX has selector bits SoSI, input lines /0, hh h and active low Enable EN'. (If
S1S0= 00, /0 is selected; if SISo = 01,1 is selected; SISo = 10, /z is selected; SISo = II, h

is selected.) (12)

SECTION -B
TIl ere are FOUR questions in this section. Answer any THREE questions.

5. (a) Design a sequence recognizer that recognizes the sequence 1101 from an input
sequence. Note that the sequence is overlapping. Design the circuit using S-R f1ipflops

and draw the circuit diagram. (20)

(b) Draw the circuit diagram of a master-slave J-K flipflop using only NAND gates. (8)
(c) Design a BCD ripple down counter using D flip-flops. (7)

6. (a) Design a circuit for a digital lock using T latches. The lock has two input push-
button switches A, B and it outputs a single pulse (Zl) for each activation. The two
switches are interlocked mechanically so that simultaneous pulses are not possible. The

lock should have the following features: (20)

(i) The opening sequence is AABABA.
(ii) Three B pulses should give an absolute reset.
(iii) Any incorrect use of the A switch will cause an output (Z2) to ring a bell
to warn that the lock is being tampered.
(b) Design a serial parity generation circuit. The circuit receives a sequence of bits and
determines whether the sequence contains an even or odd number of ones. The circuit
output p should be ° for even parity, that is, if the sequence contains an even number

of ones, and I for odd parity. (8)

(c) Design a 4 bit Jhonson counter using a shift register and illustrate its operation

using a timing diagram. (7)

.1
i

Contd P/3
 =3=

CSE 205

7. (a) For the incompletely specified machine shown in Figure for question 7(a),
complete the implication table and determine the maximum compatibles and the
maximum incompatibles. Find the upper bound and the lower bound of the number of

states of the minimal machine. Give the state table of the minimal machine. (20)

PS NS, Z
x=o x=1
A E,O C,1
B DO, C, I
C
D
A,O
-
E,
F, I
°
E G, 1 F,O
F
G
B,
D,
°° E,O
.

(b) For the state-table, in Figure for question 7(b), of a completely specified circuit,
find the equivalent partitions and write the state-table of the minimal machine. Name

the states that are equivalent. (8)

PS NS, Z
I J K
A AO, B,I E,1
B B,O A,I F,I
C A,I .DO, E,O
I D F,O C,1 A,O
E A,O D,I E,1
I F B,O D,l F,l

! Figure for question 7(b)

(c) Discuss why the condition S = R = I leads to an unstablc condition for an SR latch. (7)

8. (a) Construct a primitive flow table for a fundamental mode circuit where the output, Z,

equal 0 when the hvo inputs, XI and X2, are equal. Z = I results when XI = 0 and X2

changes from 0 to I, and when XI = I and X2 changes from 1 to 0. No other input

change causes any output change. Determine the reduced flow table containing the

minimum number ofrows. (10+10)

Contd P/4
 =4=

CSE 205
Contd ... Q. NO.8

(b) For the given reduced flow table in the Figure for question 8(b), find a valid

assignment without any critical race and complete the modified flow table. (8)

IX2 00 01 11 10 I
a @IO dlO @/1 elO
b @IO e/- @IO dI-
e blO @/1 all @IO
d alO @)/O blO @)/1

Figure for question 8(b)

(c) Obtain the Mealy equivalent state table for the Moore machine of the following

state table: (7)

NS
PS Z
x=O x=1
A A B 0
B C B 0
C C D 1
D A D 0
L-2/T-1/CSE Date: 04/09/2021

BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY, DHAKA

L-2/T-1 B. Sc. Engineering Examinations 2019-2020

Sub: CSE 205 (Digital Logic Design)

Full Marks: 210 Time: 2 hours and 30 minutes
USE SEPARATE SCRIPTS FOR EACH SECTION
The figures in the margin indicate full marks.
SECTION – A
There are FOUR questions in this section. Answer any THREE.

1. (a) Design a D-flipflop using a T-flipflop and gates. (10)

(b) Design a sequence recognizer using T-flipflops that recognizes a 4-bit non-overlapping (25)
binary sequence, X from an input stream of bits where
Sequence, X = 4-bit binary representation of your roll number (mod 16)

2. (a) Distinguish between a ring counter and a Johnson counter. Design a 5-bit ring counter and (10)
a 5-bit Johnson Counter using shift registers and illustrate their operation using timing
diagram.
(b) A sequential circuit has two flip-flops A and B, two inputs x1 and x2, and one output z. The (25)
flip-flop input equations and circuit output equations are:
JA=yA.x1+yB.x2
KA=yA.yB+x1.x2
JB=yA.x1
KB=yA.yB.x1+yB.x2
z= yA.x1.x2+yB.x1.x2
For the above mentioned circuit:
(i) Draw the logic diagram of the circuit.
(ii) Derive the transition table, excitation table and state table.
(iii) Draw the state diagram.

3. (a) A MOD-12 counter counts from 0000 to 1011. Design the MOD-12 ripple counter with (10)
positive edge-triggered JK flip-flops and basic gates.
(b) For the incompletely specified machine shown below, derive the implication table and (25)
determine the maximal compatibles and the maximal incompatibles. Find the upper bound
and the lower bound of the minimal machine and determine the minimal machine.

PS NS, Z
x=0 x=1
A A, - B, 1
B G, - D, 0
C B, 1 B, -
D A, 1 B, -
E C, - A, -
F F, - C, -
G G, - G, -
L-2/T-1/CSE Date: 04/09/2021

4. (a) Design a circuit for the following functions using Programmable Logic Array (PLA). (10)

A(x, y, z)=∑(0,1,2,5,7)

B(x, y, z)=∑(0,1,3,6,7)
(b) Design a fundamental mode circuit to function as an electrical lock. The lock has two (25)
switch inputs X1 and X2. Design the circuit so that the lock open signal Z=1 is produced
only after the following conditions have been satisfied.
(i) Begin with X1 = X2 = 0;
(ii) While X2 = 0, X1 is turned on and then it is turned off;
(iii) Then while X1 remains off, X2 is turned on to open the lock i.e. Z=1;
(iv) For any deviation in the sequence of above transitions the lock remains closed
i.e. Z=0.
Determine the primitive flow table, reduced flow table, race-free state assignment, K-maps
and circuit diagram.
L-2/T-1/CSE Date: 04/09/2021

BANGLADESH UNIVERSITY OF ENGINEERING AND TECHNOLOGY, DHAKA

L-2/T-1 B. Sc. Engineering Examinations 2019-2020

Sub: CSE 205 (Digital Logic Design)

Full Marks: 210 Time: 2 hours and 30 minutes
USE SEPARATE SCRIPTS FOR EACH SECTION
The figures in the margin indicate full marks.
SECTION – B
There are FOUR questions in this section. Answer any THREE.

5. (a) A majority circuit is a combinational circuit whose output is equal to 1 if the input (18)
variables have more 1’s than 0’s. The output is 0 otherwise. Design a 3-input majority
circuit by finding the circuit’s truth table, simplified Boolean equation and a logic
diagram. Use only NAND gate(s) for your design.
(b) Which gates are called universal gates and why? (07)
(c) Demonstrate the validity of the following identities by means of truth tables: (10)
(i) DeMorgan’s theorem for three variables: (x + y + z) = xyz
(ii) The distributive law: x(y + z) = xy + xz

6. (a) Compare Tabulation method and Karnaugh map for minimizing Boolean functions (15)
based on their merits and demerits.
(b) Convert the following Boolean function from a sum-of-products form to a simplified (20)
product-of-sums form
F (w, x, y, z) = ∑(0, 1, 2, 5, 7, 11, 13)
Draw a logic circuit for the obtained simplified product-of-sums form.

7. (a) Using Tabulation method, simplify the following Boolean function by first finding the (28)
essential prime implicants:
F (A, B, C, D) = ∑(1, 3, 4, 5, 10, 11, 12, 13, 14)

(b) Show that the dual of the exclusive‐OR is equal to its complement. (07)

8. (a) Design a full-subtractor circuit with three inputs x, y, Bin and two outputs Diff and Bout. (18)
The circuit subtracts x – y – Bin, where Bin is the input borrow, Bout is the output
borrow, and Diff is the difference.
(b) Implement the following Boolean function with a 4 x 1 multiplexer and external (17)
gates.

F (A, B, C, D) = ∑(1, 2, 4, 10, 12, 13, 14, 15)

Connect inputs A and B to the selection lines. The input requirements for the four data
lines will be a function of variables C and D. These values are obtained by expressing
F as a function of C and D for each of the four cases when AB = 00, 01, 10, and 11.
These functions may have to be implemented with external gates.
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