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    Digital Paper1

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    Iyyakutti Ganapathi
    The document contains instructions and questions for an end-term examination in digital electronics. It includes multiple choice and descriptive questions covering topics such as logic gates, multiplexers, flip-flops, counters, encoders, decoders, and digital logic design. Students are instructed to answer 10 parts of Section A, 3 questions from Section B, 2 questions from Section C, and 1 question from Section D. The questions test knowledge of digital logic concepts and require minimizing logic expressions, designing circuits, and analyzing digital systems.

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    Digital Paper1

    Uploaded by

    Iyyakutti Ganapathi
    108 views5 pages
    The document contains instructions and questions for an end-term examination in digital electronics. It includes multiple choice and descriptive questions covering topics such as logic gates, multiplexers, flip-flops, counters, encoders, decoders, and digital logic design. Students are instructed to answer 10 parts of Section A, 3 questions from Section B, 2 questions from Section C, and 1 question from Section D. The questions test knowledge of digital logic concepts and require minimizing logic expressions, designing circuits, and analyzing digital systems.

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    The document contains instructions and questions for an end-term examination in digital electronics. It includes multiple choice and descriptive questions covering topics such as logic gates, multiplexers, flip-flops, counters, encoders, decoders, and digital logic design. Students are instructed to answer 10 parts of Section A, 3 questions from Section B, 2 questions from Section C, and 1 question from Section D. The questions test knowledge of digital logic concepts and require minimizing logic expressions, designing circuits, and analyzing digital systems.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    108 views5 pages

    Digital Paper1

    Uploaded by

    Iyyakutti Ganapathi
    The document contains instructions and questions for an end-term examination in digital electronics. It includes multiple choice and descriptive questions covering topics such as logic gates, multiplexers, flip-flops, counters, encoders, decoders, and digital logic design. Students are instructed to answer 10 parts of Section A, 3 questions from Section B, 2 questions from Section C, and 1 question from Section D. The questions test knowledge of digital logic concepts and require minimizing logic expressions, designing circuits, and analyzing digital systems.

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    SIR PADAMPAT SINGHANIA UNIVERSITY

    End-Term (Repeat) Examination December 2012 20


    Branch: ECE, CSE & EE Subject: Digital Electronics Time: 3 Hrs. Semester: III Subject ubject Code: EC 204 Max. Marks: 150 15

    Instruction for candidates: Answer any ten parts out of twelve parts in question 1 of Section-A, A, any three questions from Section Section-B, B, any two questions from SectionSection C and any one question from Section Section-D. Section - A [10x3 =30] Q1. (a) The Gates G1 and G2 have propagation delays of 10 ns and 20 ns respectively. If the input V Vi makes an abrupt change from logic 0 to 1 at t=t0 t=t then the output waveform V0 is

    (b) Data can be changed from special code to temporal code by using (i) Shift registers (ii) counters (iii) Combinational circuits (iv) A/D converters (c) The MUX shown below is 4x1 multiplexer. The output Z is

    (i)

    ABC

    (B) A+B+C

    (C) ABC

    (D) None of the above

    (d) The logic circuit shown below can be minimized to

    (e) De Morgans first theorem shows the equivalence of (i) OR gate and Exclusive OR gate. (ii) NOR gate and Bubbled AND gate. (iii) NOR gate and NAND gate. (iv) NAND gate and NOT gate (f) The device which changes from serial data to parallel data is (i) COUNTER (ii) MULTIPLEXER (iii) DEMULTIPLEXER (iv) FLIP-FLOP (g) Add (17010)10 and (- 2469 246910)10 using BCD. (h) Perform the following subtraction using 2s complement (0011.1001)2 (0001.1110 0001.1110)2 (i) Find the expression for output F

    (j) The following switching functions are to be implemented using a Decoder: f1 = m1, 2, 4, 8, 10, 14f 2 2= m2 , 5, 9, 11f 3 m 2, 4, 5, 6, 7 The minimum configuration of the decoder should be (i) 2 to 4 line. (ii) 3 to 8 line. (iii) 4 to 16 line. (iv) 5 to 32 line (k) A 4-bit bit synchronous counter uses flip flip-flops flops with propagation delay times of 15 ns each. The maximum possible time required for change of state will be (i) 15 ns. (ii) 30 ns. (iii) 45 ns. (iv) 60 ns (l) The output of a JK flip flop with asynchronous preset and clear inputs is 1. The output can be changed to 0 with one of the following conditions. (i) By applying plying J = 0, K = 0 and using clock. (ii) By applying ying J = 1, K = 0 and using clock. (iii) By applying ying J = 1, K = 1 and using clock. (iv) By applying a synchronous preset input Section - B [3x (6+6)= 36] Q2.(a) Give a Boolean expression for the following statements: (i) Y is a 1 only if A is a 1 and B is a 1 or if A is a 0 or B is a 0. (ii) ) Y is a 1 only if A, B and C are all 1s or if only one of the variables is a 0 (b) How J-K K flip flop can be converted into D and T flip flop. Draw circuit diagram. diagram Q3.(a) Simplify and draw the logic diagram for the given expression F =(A BC) + ABC + ABC + ABC + ABC. hat is the difference between latch and flip-flop? List out (b) What is a flip-flop? What the application of flip-flop. Q4.(a) ABCD-seven seven segment decoder/driver is connected to an LED display. Which segments are illuminated for each of the following input co codes? des? (i) DCBA = 0001 (ii) DCBA = 0111 (iii) ) DCBA = 0011(considering D as MSB & A as LSB) (b) Verify the following operations are commutative but not associative (i) NAND (ii) NOR Q5.(a) Prove

    (b) What is a de-multiplexer? multiplexer? Discuss the differences between a de-multiplexer de and a decoder with help of a suitable example.

    Section - C [2x 2x (9+9+9)= (9+9+9 54] Q6.(a) Minimize the following logic function using K K-maps maps and realize using NAND and NOR gates. F(A,B,C, ,D) =m(1,3,5,8,9,11,15) d (2,13). (b)Using Using Quine McCluskey method find the minimized output for the given expression (c) Define the carry propagate and carry generate as Pi = Ai + Bi Gi = AiBi respectively. Show that the output carry and the output sum of a full adder becomes

    Q7. (a) Design a 2 to 1 multiplexer by using the four variable function given by F(A,B,C,D) = m(0,1,3,4,8 8,9,15) (b) What are synchronous counters? Design a Mod-5 5 synchronous counter using J-K Flip-Flops (c) Differentiate between a prime implicant and a non prime implicant, and an essential prime implicant. Using K map find the prime implicants and essential prime implicants of f=m(0,1,2, m(0,1,2,3,6,7,13,15). Q8.(a) Simplify the given expression to its Sum of Products (SOP) form. Draw the logic circuit for the simplified SOP function Y=(A+B)(A+AB)C +A(B+C)+AB+ABC. (b) Explain the working of Master Slave Flip Flop. (c) A combinational circuit has 3 inputs A, B, C and output F. F is true for following input combinations A is False, B is True A is False, C is True A, B, C are False A, B, C are True (i) Write the Truth table for F. Use the convention True=1 and False = 0.

    (ii) Write the simplified expression for F in SOP form. (iii) Write the simplified expression for F in POS form. (iv)Draw logic circuit using minimum number of 2-input NAND gates. Section - D [1x (7.5+7.5+7.5+7.5)= 30] Q9. (a) Design S-R flip-flop using J-K flip-flop. (b) By using 2:4 decoders, design a 5:32 decoder. (c) Design a four bit priority encoder. (d) Explain the design procedure for a circuit to perform BCD addition. Q10.(a) Implement the following function using a 3 line to 8 line decoder. S (A, B, C) = m (1,2,4,7) C (A, B, C) = m ( 3,5,6,7) (b) A staircase light is controlled by two switches one at the top of the stairs and another at the bottom of stairs (i) Make a truth table for this system. (ii) Write the logic equation is SOP form. (iii) Realize the circuit using AND-OR gates. (c) Device a single error correcting code for 11 bit group 01101110101. Test the Hamming code sequence fo 11 bit message and correct it if necessary (101001011101011). Hint : use even parity. . (d) Design a logic circuit with 4 inputs A,B,C,D that will produce output 1 only whenever two adjacent input variables are 1s. A and D are also to be treated as adjacent. Implement it using universal gates.

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