Delhi Institute of Engineering &

Technology

Department of Computer Science & Engineering

LAB MANUAL

Subject Code: BCS - 352

Subject Name: Computer Organization & Architecture
 EXPERIMENT NO.1

Objective: To design the circuit of half adder.

IC USED: 7486(X-OR), 7408(AND).

THEORY: A half adder is a logical circuit that performs an additional operation on two binary digits.
The half adder produces a sum and a carry value which are both binary digits.

A half adder circuit has two inputs A and B and two outputs – S representing sum and C representing
carry.

S = A xor B i.e. (A’B + AB’)

C = A and B i.e. (A.B)

TRUTH TABLE:

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

SCHEMATIC DIAGRAM:
WAVEFORM:

RESULT: The output waveform of half adder is verified.

 EXPERIMENT NO.2

Objective: To design the circuit of full adder.

IC USED: 7486(X-OR), 7408(AND), 7432(OR).

THEORY: A full adder is a logical circuit that performs an additional operation on three binary digits.
The half adder produces a sum and a carry value which are both binary digits.

A full adder circuit has three inputs A,B and Cin and two outputs – S representing sum and Cout
representing carry.

S = A xor B xor C

C = A.B +C(A xor B)

TRUTH TABLE:

A B Cin S Cout

0 0 0 0 0
 0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

SCHEMATIC DIAGRAM:

WAVEFORM:

RESULT: The output waveform of full adder is verified.

 EXPERIMENT NO.3

Objective: To design the circuit of half subtractor.

IC USED: 7486(X-OR), 7408(AND), 7404(NOT).

THEORY: A half subtractor is a logical circuit that performs an subtraction operation on two binary
digits. The half subtractor produces a Difference and a borrow value which are both binary digits.

A half subtractor circuit has two inputs X, Y and two outputs – D representing difference and B
representing borrow.

D = A xor B i.e. (A’B + AB’)

B = A’B

TRUTH TABLE:

X Y D B

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

SCHEMATIC DIAGRAM:
WAVEFORM:

RESULT: The output waveform of half subtractor is verified.

 EXPERIMENT NO.4

Objective: To design the circuit of full subtractor.

IC USED: 7486(X-OR), 7408(AND), 7432(OR),7404(NOT).

THEORY: A full subtractor is a logical circuit that performs an subtraction operation on three binary
digits. The full subtractor produces a difference and a borrow value which are both binary digits.

A Full adder circuit has three inputs A,B and C and two outputs – DIFF representing difference and
BOR representing borrow.

S = A xor B xor C

C = A’.B +C(A xnor B)

TRUTH TABLE:

A B C DIF BOR
F
 0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

SCHEMATIC DIAGRAM:

WAVEFORM:
RESULT: The output waveform of full subtractor is verified.
 EXPERIMENT NO.5

Objective: To design an 8×1 Multiplexer.

IC USED: 7486(X-OR), 7408(AND), 7432(OR), 7404(NOT), 74151A (8×1 MUX).

THEORY: A multiplexer is a device that performs multiplexing i.e. it selects one of many analog or
digital input signals and forwards the selected input into a single line. A multiplexer of 2 n inputs has n
select lines, which are used to select which input line to be sent to the output.

A Boolean equation for 8×1 Multiplexer is

Z = A’.B’.C’ + A’.B’.C + A’.B.C’ + A’.B.C + A.B’.C’ + A.B’.C + A.B.C’ + A.B.C

TRUTH TABLE:

S0 S1 S2 Z

0 0 0 A

0 0 1 B

0 1 0 C

0 1 1 D

1 0 0 E

1 0 1 F

1 1 0 G

1 1 1 H

SCHEMATIC DIAGRAM:
WAVEFORM:

RESULT: The output waveform of 8×1 Multiplexer is verified.

 EXPERIMENT NO.6

Objective: To design a 4 bit combinational shifter.

IC USED: 74157(quad 2×1 MUX).

THEORY: An n-bit shift circuit has a single n-bit data input A, and a single n-bit output R and a
number of control inputs to determine the shift amount ( 0 to n-1).

In this case the possible shift operations are SHIFT LEFT and SHIFT RIGHT. This shifting depends
on selection line input S. If S = 0 then SHIFT RIGHT operation takes place , else SHIFT LEFT
operation takes place.

SCHEMATIC:
WAVEFORM:

RESULT: The circuit of 4-bit combinational shifter is designed and output is verified.
 EXPERIMENT NO.7

Objective: To design a BCD adder.

IC USED: 7483A (4-bit adder), 7408(AND), 7432(OR).

THEORY:

It is possible to perform addition in BCD by first adding in binary, and then converting to BCD
afterwards. Conversion of the simple sum of two digits can be done by adding 6 (that is, 16 – 10)
when the result has a value greater than 9.

For example:

1001 + 1000 = 10001 = 0001 0001

9 + 8 = 17 = 1 1

In BCD, there cannot exist a value greater than 9 (1001) per nibble. To correct this, 6 (0110) is added
to that sum to get the correct first two digits:

0001 0001 + 0000 0110 = 0001 0111

1 1+ 0 6= 1 7

This gives two nibbles, 0001 and 0111, which correspond to the digits "1" and "7". This yields "17"
in BCD, which is the correct result. This technique can be extended to adding multiple digits, by
adding in groups from right to left, propagating the second digit as a carry, always comparing the 5-
bit result of each digit-pair sum to 9.
SCHEMATIC:

WAVEFORM:

RESULT: BCD adder is designed and output is verified.

 EXPERIMENT NO.8

Objective: To design a 4-bit adder subtractor.

IC USED: 7483A (4-bit adder), 7486(X-OR).

THEORY:

It is a combinational circuit which can act as both a binary adder and a binary subtractor. It is
constructed using 4 full adders.Block diagram of the circuit is shown below:

In this case if sub is 0, then the circuit acts as an adder,else subtractor. Subtraction is done by adding
two’s compliment of B to A, which effectively results in A - B.

SCHEMATIC:
WAVEFORM:

RESULT: The circuit of a 4-Bit adder subtractor is designed and verified.

 EXPERIMENT NO.9

Objective: To design an ALU.

IC USED: 74153(4×1 MUX), 7432(OR), 7404(NOT), 7408(AND), 7486(XOR).

THEORY: In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic
and logical operations. The ALU is a fundamental building block of the central processing unit (CPU)
of a computer, and even the simplest microprocessors contain one for purposes such as maintaining
timers. The processors found inside modern CPUs and graphics processing units (GPUs)
accommodate very powerful and very complex ALUs; a single component may contain a number of
ALUs.

Mathematician John von Neumann proposed the ALU concept in 1945.

Below is a block diagram for an ALU:

SCHEMATIC:
WAVEFORM:

RESULT: The ALU is designed and its output is verified.

 EXPERIMENT-10

Objective: To design a 2:4 decoder

IC USED: 7404(NOT), 7408(AND).

THEORY: A decoder is a device which does the reverse of an encoder, undoing the encoding so that
the original information can be retrieved. The same method used to encode is usually just reversed in
order to decode.

In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit
that converts coded inputs into coded outputs, where the input and output codes are different.

Decoders have 2 inputs and 4 outputs. The binary input fed at input will be decoded to provide
either logical high or low on one of the 4 outputs, which is termed as octal equivalent for that binary
input. For a binary input 100, which is 4 in octal number system, the output pin called O4 will go
either high or low.

SCHEMATIC:

d1A
OFFTIME = .3uSDSTM1 1
ONTIME = .3uS CLK 3
DELAY = V
2
STARTVAL = 0 V
0
OPPVAL = 1 7408
0
0
U2B d2B
3 4 4
6
OFFTIME = .4uSDSTM2 7404 5
ONTIME = .4uS CLK V
DELAY = 7408
0
STARTVAL = 0
OPPVAL = 1
d3C
9
U2A 8
1 2 10
1 V
V 7404 7408
0

d4D
12
11
13
V
7408
1
1

WAVEFORM:
RESULT: 2:4 decoder is designed and its output is verified.