SYLLABUS

1. Design and implementation of Adders and Subtractors using logic gates.

2. Design and implementation of code converters using logic gates
(i) BCD to excess-3 code and vice versa
(ii) Binary to gray and vice-versa
3. Design and implementation of 4 bit binary Adder/ subtractor and BCD adder using
IC 7483
4. Design and implementation of 2 Bit Magnitude Comparator using logic gates 8 Bit
Magnitude Comparator using IC 7485
5. Design and implementation of 16 bit odd/even parity checker /generator using
IC74180.
6. Design and implementation of Multiplexer and De-multiplexer using logic gates and
study of IC74153 and IC 74139
7. Design and implementation of encoder and decoder using logic gates and study of
IC7445 and IC74147
8. Construction and verification of 4 bit Asynchronous (ripple) counter.
9. Construction and verification of 4 bit Asynchronous (ripple) counter.
10. Construction and verification of Mod 10 and Mod 12 counter.
11. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops.
12. Design of expts 1,6,8,10 using NI MultiSim Software.

1
 LIST OF EXPERIMENTS

1. Study of logic gates.

2. Design and implementation of adder
3. Design and implementation of subtractor using logic gates.
4. Design and implementation of code converters using logic gates.
5. Design and implementation of 4-bit binary adder/subtractor
6. Study and verify the performance of BCD adder using IC 7483.
7. Design and implementation of 2-bit magnitude comparator using logic gates and
IC7485
8. Design and implementation of multiplexer and demultiplexer using logic gates
and study of IC 74153 and IC 74139.
9. Design and implementation of encoder and decoder using logic gates and study of
IC 7442 and IC 74147.
10. Study and verify the performance of SR, JK and D flip-flops using logic gates.
11. Construct and verify the truth table of 4-bit Asynchronous (Ripple) counter.
12. Construct and verify the truth table of 4-bit Synchronous counter.
13. Design and implementation of 3-bit synchronous up/down counter.
14. Construct and verify the truth table of Asynchronous Mod-10/Mod-12 counter.
15. Construct and verify the truth table of Johnson counter
16. Implementation of SISO, SIPO, PISO and PIPO shift registers using flip-flops.

2
 INDEX

EXP. PAGE
DATE NAME OF THE EXPERIMENT MARKS SIGNATURE
NO NO

3
 Date:
STUDY OF LOGIC GATES
Expt. No.:

AIM:
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:
SL No. COMPONENT SPECIFICATION QTY
1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14
THEORY:

Circuit that takes the logical decision and the process are called logic gates. Each
gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.

AND GATE:
The AND gate performs a logical multiplication commonly known as AND
function. The output is high when both the inputs are high. The output is low level when
any one of the inputs is low.

OR GATE:
The OR gate performs a logical addition commonly known as OR function.
The output is high when any one of the inputs is high. The output is low level when both
the inputs are low.

4
NOT GATE:

The NOT gate is called an inverter. The output is high when the input is low.
The output is low when the input is high.

NAND GATE:

The NAND gate is a contraction of AND-NOT. The output is high when both
inputs are low and any one of the input is low .The output is low level when both inputs
are high.

NOR GATE:

The NOR gate is a contraction of OR-NOT. The output is high when both inputs
are low. The output is low when one or both inputs are high.

X-OR GATE:

The output is high when any one of the inputs is high. The output is low when
both the inputs are low and both the inputs are high.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

5
AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:

6
NOT GATE:

SYMBOL: PIN DIAGRAM:

X-OR GATE :

SYMBOL : PIN DIAGRAM :

7
2-INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

3-INPUT NAND GATE :

8
NOR GATE:

RESULT:

9
LOGIC DIAGRAM:

HALF ADDER
A 1A
1Y
B 1B
SUM = AB + AB
74LS86N

1A
1Y
1B CARRY = AB
74LS08D
TRUTH TABLE:

A B CARRY SUM
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

K-Map for SUM: K-Map for CARRY:

SUM = AB + AB CARRY = AB

10
 Date:
DESIGN OF HALF ADDER AND FULL ADDER
Expt. No.:

AIM:
To design and construct half adder, full adder, half subtractor and full subtractor
circuits and verify the truth table using logic gates.

APPARATUS REQUIRED:

Sl. No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. EX-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. IC TRAINER KIT - 1
5. PATCH CORDS - Adequate

THEORY:
HALF ADDER:
Half adder is a combinational circuit which consists of two binary input variables
called augend and addend and two binary output variables called sum and carry. In the
addition result, the lower significant bit is called as sum and the higher significant bit is
called as carry. The truth table of the half adder is given below, in that the sum becomes
logic ‘1’ when any one of the input is maximum and it is equal to logic ‘0’ when both
inputs are equal. The carry is equal to logic ‘1’ when both inputs are equal to logic ‘1’
unless it is equal to logic ‘0’.

FULL ADDER:
Full adder is a combinational circuit which consists of three binary input variables
called augends and addends and two binary output variables called sum and carry out. In
the addition result, the lower significant bit is called as sum and the higher significant bit
is called as carry out. The truth table of the full adder describes all the eight possible
input variations. The full adder results the outputs are equal to logic ‘0’ when all the
applied inputs are equal to logic ‘0’ and the outputs are equal to logic ‘1’ when all the
inputs are equal to logic ‘1’. The sum is equal to 1 when odd numbers of inputs are equal
to 1 from the applied three inputs. The carry out is equal to 1 if more than one applied
inputs are equal to 1.

11
LOGIC DIAGRAM:
FULL ADDER USING TWO HALF ADDER

U1A
74LS86D U1B
A 1 74LS86D
3 4
B 2 6 S
5
SUM = A B Cin

U2B
74LS08N
4
6
Cin 5

U3A
U2A 74LS32D
74LS08N 1 COUT
1 3
3 2
2
Cout = (A B) Cin + AB
Cin

TRUTH TABLE:

Inputs Outputs
A B Cin Cout S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

12
 K-Map for SUM:
K-Map for Cout:
BCin BCin
A 00 01 11 10 A 00 01 11 10
0 0 1 0 1 0 0 0 1 0

1 1 0 1 0 1 0 1 1 1

Sum (S) = ABCin + ABCin +ABCin + ABCin

Cout = BCin + ACin +ABCin + AB
= (AB + AB)Cin + (AB + AB)Cin
= (A + A) BCin + A (B + B)Cin + AB
= (A B) Cin + (A B) Cin
= ABCin + ABCin + ABCin + ABCin + AB
= (A B) Cin + (A B) Cin
= (AB + AB) Cin + ABCin + AB
SUM (S) = A B Cin
Cout = (A B)Cin + AB

PROCEEDURE:
(i) Verify the truth table of the given Logic Gates.
(ii) Connection to be made as per the circuit diagram.
(iii) All the possible input variations are to be given.
(iv) Observe the output and verify the truth table.

RESULT:

13
LOGIC DIAGRAM:

HALF SUBTRACTOR

TRUTH TABLE:

A B BORROW DIFFERENCE

0 0 0 0

0 1 1 1

1 0 0 1

1 1 0 0

K-Map for DIFFERENCE:

K-Map for BORROW:

DIFFERENCE = AB + AB

BORROW = AB

14
Date:
DESIGN OF HALF SUBTRACTOR AND FULL SUBTRACTOR
Expt. No.:

AIM:
To design and construct half adder, full adder, half subtractor and full subtractor
circuits and verify the truth table using logic gates.

APPARATUS REQUIRED:

Sl. No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. EX-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. NOT GATE IC7040 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - Adequate

THEORY:
HALF SUBTRACTOR:
Half subtractor is a combinational circuit which consists of two binary input
variables called minuend and subtrahend, and two binary output variables called
difference and borrow. In the two bit subtraction result, the lower significant bit is called
as difference and higher significant bit is called as borrow. The truth table of the
subtractor is given below in that the difference becomes logic ‘1’ when both inputs are
different each other and it is equal to logic ‘0’ when both inputs are equal. And borrow is
equal to logic ‘1’ when minuend is smaller than subtrahend.

FULL SUBTRACTOR:
Full subtractor is a combinational circuit which consists of three binary input
variables called minuend and subtrahend, and two binary output variables called
difference and borrow out. In the subtraction result, the lower significant bit is called as
difference and the higher significant bit is called as barrow out. The truth table of the full
subtractor describes all the eight possible input variations. The full subtractor results the
outputs are equal to logic ‘0’ when all the applied inputs are equal to logic ‘0’

15
LOGIC DIAGRAM:
FULL SUBTRACTOR USING TWO HALF SUBTRACTOR

U3A
74LS86D
A 1 U3B
3 4
B 2 6 DIFFERENCE
5
74LS04N 74LS86D
3 4

U2B
U1B
Bin 4
6
U1A 5
U2A U4A
74LS08N 74LS08N 1
1 2 1 3 BOUT
3 2
2
74LS04N 74LS32D

TRUTH TABLE

Inputs Outputs
A B Bin Bout D
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

16
 or most significant bit and any one of the least significant bit is equal to logic ‘1’, and the
outputs are equal to logic ‘1’ when all the inputs are equal to logic ‘1’ or any one of the
subtrahend is equal to logic ‘1’. The difference is equal to 1 when odd numbers of inputs
are equal to 1 from the applied three inputs. The barrow out is equal to 1 if any one of the
subtrahend or all the applied inputs are equal to logic ‘1’.

PROCEEDURE:
(i) Verify the truth table of the given Logic Gates.
(ii) Connection to be made as per the circuit diagram.
(iii) All the possible input variations are to be given.
(iv) Observe the output and verify the truth table.

K-Map for Difference: K-Map for Borrow (Bout):

BBin
A 00 01 11 10 BBin
0 0 1 0 1 A 00 01 11 10

1 1 0 1 0 0 0 1 1 1

1 0 0 1 0
Sum (S) = ABBin + ABBin +ABBin + ABCin

= (AB + AB)Bin + (AB + AB)Bin

BORROW (Bout) = AB + ABin + BBin
= (A B) Bin + (A B) Bin = AB + A (B + B)Bin + (A + A) BBin
= AB + ABBin + ABBin + ABBin + ABBin
= (A B) Bin + (A B) Bin
= AB + ABBin + ABBin + ABBin
SUM (S) = A B Bin = AB + ABBin + (AB + AB) Bin
= AB + (A B) Bin
(Bout) = AB + (A B) Bin

= (A B) Bin + (A B) Bin
RESULT:
SUM (S) = A B Bin

17
LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTOR

B3 G3 = B3
U1A
1
3
2 G2 = B3 + B2
B2
74LS86N

U1B
4
6
5 G1 = B1 + B2
B1
74LS86N

U1C
9
8
10 G0 = B0 + B1
B0
74LS86N

TRUTH TABLE:

Inputs (BINARY CODE) Outputs (GRAY CODE)

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

18
 Date:
DESIGN AND IMPLEMENTATION OF CODE CONVERTOR
Expt. No.:

AIM:
To design and implement 4-bit
(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:
BINARY CODES: A group of binary bits that used to represent the characters,
numbers and symbols is defined as binary codes. Binary codes are used in the digital
computer to represent, store and transmit various data.
BCD NUMBERS: BCD numbers are straight binary representation for decimal
numbers. The decimal numbers ate directly represented with the weightages of 8421 in
BCD code. This is popularly used in decimal addition, subtraction, etc. the BCD code
represents the decimal number 0 to 9 with the binary representation 0000 to 1001. In the
4-bit binary representation last six assignments are discarded for BCD number
representation.
EXCESS – 3 CODE: The 4-bit excess – 3 code is obtained by adding 3(0011)
with BCD code. 8421 and 2421 weighted codes provide the self-complement number of
excess – 3 code in the binary representation. The self-complement property of excess – 3
code helps to perform the arithmetic operation in digital system design.

19
LOGIC DIAGRAM:
GRAY TO BINARY CODE CONVERTOR

G3 G2 G1 G0
U1A
1
3
2 B0 = G3 + G2 + G1 + G0
74LS86N

U1B
4
6
5 B1 = G3 + G2 + G1
74LS86N

U1C
9
8 B2 = G3 + G2
10

74LS86N
B3 = G3

TRUTH TABLE:

Inputs (GRAY CODE) Outputs (BINARY CODE)

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 0 1 0 1 1
1 1 1 1 1 0 1 0

20
BINARY TO GRAY CODE CONVERTOR – K-MAP
K-map for G3: K-map for G2:

B1B0
B3B2 00 01 11 10 B1B0
B3B2 00 01 11 10
00 0 0 0 0
00 0 0 0 0
01 0 0 0 0
01 1 1 1 1
11 1 1 1 1 11 0 0 0 0
10 1 1 1 1
10 1 1 1 1
G3 = B3
G2 = B3B2 + B3B2 = B3+ B2
K-map for G1: K-map for G0:

B1B0 B1B0
B3B2 00 01 11 10 B3B2 00 01 11 10
00 0 0 1 1 00 0 1 0 1
01 1 1 0 0 01 0 1 0 1
11 1 1 0 0 11 0 1 0 1
10 0 0 1 1 10 0 1 0 1

G1 = B1B2 + B1B2 = B1+ B2 G0 = B1B0 + B1B0 = B1+ B0

GRAY TO BINARY CODE CONVERTOR – K-MAP

K-map for B3: K-map for B2:

G1G0 G1G0
G3G2 00 01 11 10 G3G2 00 01 11 10
00 0 0 0 0 00 0 0 0 0
01 0 0 0 0 01 1 1 1 1

11 1 11 0 0 0 0
1 1 1
10 1 1 1 1
10 1 1 1 1

G3 = B3 B2 = G3G2 + G3G2 = G3 + G2

21
GRAY CODE: This code is an un-weighted binary code. A gray code is often used in
the translation of an analog quantity, such as a shaft position in to digital form. The four
bit gray code can be used to represent the decimal number from 0 to 15. In this
representation the last and first entry of gray code consequently differs only in one bit
position (MSB bit). So this is also called reflective code.
CODE CONVERTERS: The presence of different codes in digital system for the same
discrete elements of binary information results the requirement of code conversion. Code
converter is a logic circuit that converts one type of binary code into another type of
binary code.

PROCEDURE:
1. Construct the truth table to convert one form of code to another form.
2. Verify the Boolean expression using K-map for the output variables.
3. Rig the circuit diagram for simplified Boolean expressions.
4. Verify the truth table.

GRAY TO BINARY CODE CONVERTOR – K-MAP

K-map for B1: K-map for B0:

G1G0 G1G0
G3G2 00 01 11 10 G3G2 00 01 11 10
00 0 0 1 1 00 0 1 0 1
01 1 1 0 0 01 1 0 1 0
11 0 0 1 1 11 0 1 0 1
10 1 1 0 0 10 1 0 1 0

B1 = G3 + G2 + G1 B0 = G3 + G2 + G1 + G0
BCD TO EXCESS-3 CODE CONVERTOR - K – MAP:
K-map for E3: K-map for E2:
B1B0 B1B0
B3B2 00 01 11 10 B3B2 00 01 11 10
00 0 0 0 0 00 0 1 1 1
01 0 1 1 1 01 1 0 0 0
11 X X X X 11 X X X X
10 1 1 X X 10 0 1 X X
E2 = B2 + (B1 + B0)
E3 = B3 + B2 (B1 + B0)

22
LOGIC DIAGRAM:
BCD TO EXCESS-3 CODE CONVERTOR

B3 B2 B1 B0

1
U2A U1B
2
3 4
6 4
U2B
5 6 E3 = B3 + B2 (B1 + B0)
74LS32N 74LS08N
5

74LS32N

U3A
1
2
3
E2 = B2 + (B1 + B0)
74LS86D

U3B U4A
4
6 1 2
5 E1 = B1 + B0
74LS86D 74LS04N

U4B
3 4
E0 = B0
74LS04N

TRUTH TABLE:

Inputs (BCD CODE) Outputs (EX-3 CODE)

B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0

23
LOGIC DIAGRAM:
EXCESS-3 TO BCD CODE CONVERTOR

E0 E1 E2 E3

4
U1B
6
5 B3 = E3 (E2 + E1E0)
U2A 74LS08N
1
U1A 1
3
3 2
2

74LS08N 74LS32N

U3A
1 2
U2B
74LS04N 4 U4A
6
5
U3B B2 = E2 + (E1 + E0)
3 4 74LS32N
74LS86N
74LS04N

U4B
4
6
5 B1 = E1 + E0
74LS86N

B0 = E0

TRUTH TABLE:

Inputs (EX-3 CODE) Outputs (BCD CODE)

E3 E2 E1 E0 B3 B2 B1 B0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1

24
BCD TO EXCESS-3 CODE CONVERTOR - K – MAP:

K-map for E1: K-map for E0:

B1B0 B1B0
B3B2 00 01 11 10 B3B2 00 01 11 10
00 1 0 1 0 00 1 0 0 1
01 1 0 1 0 01 1 0 0 1
11 X X X X 11 X X X X
10 1 0 X X 10 1 0 X X

E1 = B1 + B0 E0 = B0
EXCESS-3 TO BCD CODE CONVERTOR - K – MAP:
K-map for B3: K-map for B2:

E1E0 E1E0
E3E2 00 01 11 10 E3E2 00 01 11 10
00 X X 0 X 00 X X 0 X
01 0 0 0 0 01 0 0 1 0
11 1 X X X 11 0 X
X X
10 0 0 1 0
10 1 1 0 1
B3 = E3 (E2 + E1E0) B2 = E2 + (E1 + E0)

K-map for B1: K-map for B0:

E1E0
E3E2 00 01 11 10 E1E0
00 X X X E3E2 00 01 11 10
0
00 X X 0 X
01 0 1 0 1
01 1 0 0 1
11 0 X X X
11 1 X X X
10 0 1 0 1
10 1 0 0 1
B1 = E1 + E0
B0 = E0

RESULT:

25
BLOCK DIAGRAM - BINARY ADDER

B3 A3 B2 A2 B1 A1 B0 A0

FA FA FA FA C0

C4 S3 S2 S1 S0

PIN DIAGRAM OF IC 7483:

LOGIC DIAGRAM:
4-BIT BINARY ADDER

26
 Date:
DESIGN OF 4-BIT ADDER AND SUBTRACTOR
Expt. No.:

AIM:
To design and implement 4-bit adder and subtractor using IC 7483.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - Adequate

THEORY:

BINARY ADDER:
A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output
carry from each full adder connected to the input carry of next full adder in the chain. The
augend bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from
right to left, with subscript ‘0’ denoting the least significant bit. The carries are connected
in chain through the full adders. The input carry to the adder is C0 and it ripples through
the full adders to the output carry C4. The ‘S’ outputs generate the required sum bits.

BINARY SUBTRACTOR:
The subtraction of unsigned binary numbers can be done most conveniently by
means of complements. The subtraction A – B can be done by taking 2’s complement of
B and adding it to A. The 2’s complement can be obtained by taking 1’s complement and
adding 1 to the least significant pair of bits. The 1’s complements can be implemented
with inverters, and a 1 can be added to the sum through the input carry. The input carry
C0 must be equal to 1 when performing subtraction.

27
LOGIC DIAGRAM:
4-BIT BINARY SUBTRACTOR

LOGIC LOGIC DIAGRAM:

4-BIT BINARY ADDER/SUBTRACTOR

28
BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with one
common binary adder. This is done by including an exclusive – OR gate with each full-
adder. The mode input M controls the operation of the circuit. When M=0, the circuit is
an adder and when M=1, the circuit becomes a subtractor.

PROCEDURE:
1. Rig the circuit as per the circuit diagram.
2. Apply the given binary input data to the respective input pins
3. Verify the truth table.

TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

RESULT:

29
LOGIC DIAGRAM:
BCD ADDER

K-map for C:
Z2 Z1
Z8 Z4 00 01 11 10
00 0 0 0 0

01 0 0 0 0

11 1 1 1 1

10 0 0 1 1

30
 Date:
DESIGN OF BCD ADDER
Expt. No.:
AIM:
To design and implement BCD adder IC 7483.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. IC IC 7483 2
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7408 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - Adequate

THEORY:
BCD ADDER: BCD adder is a circuit that performs the addition of two BCD numbers in
parallel. BCD additions are performed in 4-bit binary form so there is a possibility of
increasing binary number greater than 9 that results wrong output. To avoid this, in BCD
addition correction logic I included as described below,
1. If the binary sum is equal or less than 9 with carry 0, then that binary sum is
correct BCD sum.
2. I the binary sum is equal or less than 9 with carry 1, then that binary sum is an
incorrect BCD sum. To get the correct BCD sum add 0110 with least significant
binary sum digits.
3. If the binary number is greater than 9, then that binary sum is an incorrect BCD
sum. To get the correct BCD sum add 0110 with binary sum digits.
BCD adder can be constructed with three blocks such as two binary adders and the
correction logic circuit. Initially in the BCD adders, the four bit binary numbers are added
using parallel binary adder and then, the binary output is checked to correct as BCD
number. The correction logic generates the correction code based on the binary output
values. When we get the incorrect binary output as per the condition described above, the
correction code is added with the binary output to get the correct BCD number through
second binary adder.

PROCEDURE:
1. Connections are made as per the circuit diagram.
2. Apply the logical Input data and verify the corresponding output.

31
TRUTH TABLE:

Binary sum BCD sum

Decimal
K Z8 Z4 Z2 Z1 C S8 S4 S2 S1
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 2
0 0 0 1 1 0 0 0 1 1 3
0 0 1 0 0 0 0 1 0 0 4
0 0 1 0 1 0 0 1 0 1 5
0 0 1 1 0 0 0 1 1 0 6
0 0 1 1 1 0 0 1 1 1 7
0 1 0 0 0 0 1 0 0 0 8
0 1 0 0 1 0 1 0 0 1 9
0 1 0 1 0 1 0 0 0 0 10
0 1 0 1 1 1 0 0 0 1 11
0 1 1 0 0 1 0 0 1 0 12
0 1 1 0 1 1 0 0 1 1 13
0 1 1 1 0 1 0 1 0 0 14
0 1 1 1 1 1 0 1 0 1 15
1 0 0 0 0 1 0 1 1 0 16
1 0 0 0 1 1 0 1 1 1 17
1 0 0 1 0 1 1 0 0 0 18
1 0 0 1 1 1 1 0 0 1 19

RESULT:

32
 Date: DESIGN AND IMPLEMENTATION OF MAGNITUDE
Expt. No.: COMPARATOR

AIM:
To design and implement
(i) 2 – bit magnitude comparator using basic gates.
(ii) 4 – bit magnitude comparator using IC 7485.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 / IC7411 2/1
2. X-OR GATE IC 7486 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. 4-BIT MAGNITUDE IC 7485 2
COMPARATOR
6. IC TRAINER KIT - 1
7. PATCH CORDS - 30

THEORY:

The comparison of two numbers is an operation that determines whether one

number is greater than, less than (or) equal to the other number. A magnitude comparator
is a combinational circuit that compares two numbers A and B and determines their
relative magnitude. The outcome of the comparator is specified by three binary variables
that indicate whether A>B, A=B (or) A<B.
A = A3 A2 A1 A0
B = B3 B2 B1 B0
The equality of the two numbers A and B is displayed in a combinational circuit
designated by the symbol (A=B).
This indicates A greater than B, then inspect the relative magnitude of pairs of
significant digits starting from most significant position. A is 0 and that of B is 0.

33
LOGIC DIAGRAM:
2 BIT MAGNITUDE COMPARATOR

A1 A0 B1 B0
1

0
U1A U1B U1C U1D
74LS04N 74LS04N 74LS04N 74LS04N

U3A

U4A
74LS11N
U2A
74LS32N U4B

74LS08N
74LS32N
U3B

74LS11N

U1E
U5A
U2B
74LS86N 74LS04N
U5B U1F
74LS08N

74LS86N 74LS04N
U3C

U4C
74LS11N
U6A
74LS32N U4D

74LS11N
U2C 74LS32N

74LS08N

34
 We have A<B, the sequential comparison can be expanded as
A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01
A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0
The same circuit can be used to compare the relative magnitude of two BCD
digits.
Where, A = B is expanded as,
A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)
   
x3 x2 x1 x0

2-BIT MAGNITUDE COMPARATOR – K-MAP

K-map for A>B: K-map for A=B:

B1B0 B1B0
A1 A0 00 01 11 10 A1 A0 00 01 11 10
00 0 0 0 0 00 1 0 0 0
01 1 0 0 0 01 0 1 0 0
11 1 1 0 1 11 0 0 1 0
10 1 1 0 0 10 0 0 0 1

A>B = B1 A1 + B1 B0 A0 + B0 A1 A0 A=B = (B0 A0) (B1 A1)

K-map for A<B:

B1B0
A1 A0 00 01 11 10
00 0 1 1 1
01 0 0 1 1
11 0 0 0 0
10 0 0 1 0

A<B = B1 A1 + A1 A0 B0 + B0 B1 A0

35
TRUTH TABLE – 2 - BIT MAGNITUDE COMPARATOR

INPUTS OUTPUTS
A B
A>B A=B A<B
A1 A0 B1 B0
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

PIN DIAGRAM OF IC 7485:

36
 LOGIC DIAGRAM:
4 BIT MAGNITUDE COMPARATOR

TRUTH TABLE:

Comparing Inputs Cascading Inputs OUPUTS

A3 B3 A2 B2 A1 B1 A0 B0 IA>B IA<B IA=B A>B A<B A=B
A3 > B3 X X X X X X 1 0 0
A3 < B3 X X X X X X 0 1 0
A3 = B3 A2 > B2 X X X X X 1 0 0
A3 = B3 A2 < B2 X X X X X 0 1 0
A3 = B3 A2 = B2 A1 > B1 X X X X 1 0 0
A3 = B3 A2 = B2 A1 < B1 X X X X 0 1 0
A3 = B3 A2 = B2 A1 = B1 A0 > B0 X X X 1 0 0
A3 = B3 A2 = B2 A1 = B1 A0 < B0 X X X 0 1 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 0 0 1 0 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 1 0 0 1 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 0 1 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 = B0 X X 1 0 0 1
A3 = B3 A2 = B2 A1 = B1 A0 = B0 1 1 0 0 0 0
A3 = B3 A2 = B2 A1 = B1 A0 = B0 0 0 0 1 1 0

37
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

38
Date: DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND
Expt. No.: DEMULTIPLEXER

AIM:
To design and implement multiplexer and de-multiplexer using logic gates and
study of IC 74153 and IC 74139.

APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. MULTIPLEXER IC IC 71LS153 1
5. DEMULTIPLEXER IC IC 74LS139 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 32

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational circuit that
selects binary information from one of many input lines and directs it to a single output
line. The selection of a particular input line is controlled by a set of selection lines.
Normally there are 2n input line and n selection lines whose bit combination determine
which input is selected.

DEMULTIPLEXER:
A demultiplexer is a circuit that receives information on a single line and
transmits this information on one of 2n possible output lines. The selection of specific
output line is controlled by the values of n selection lines. The single input variable Din
has a path to all four outputs, but the input information is directed to only one of the
output lines.

39
BLOCK DIAGRAM OF 4:1 MULTIPLEXER:
PIN DIAGRAM
U1
VCC 16
6 1C0 1Y 7
5 1C1
4 1C2
3 1C3
10 2C0 2Y 9
11 2C1
12 2C2
13 2C3
14 A
2 B
1 ~1G
15 ~2G
8 GND

74LS153N

FUNCTION TABLE:

Select Inputs Inputs (1 or 2) Output

S0 S1 E I0 I1 I2 I3 Y

X X 1 X X X X 0

0 0 0 0 X X X 0

0 0 0 1 X X X 1

1 0 0 X 0 X X 0

1 0 0 X 1 X X 1

0 1 0 X X 0 X 0

0 1 0 X X 1 X 1

1 1 0 X X X 0 0

1 1 0 X X X 1 1

40
 CIRCUIT DIAGRAM OF MULTIPLEXER:

S1 S0
1

3
U1A U1B D0 D1 D2 D3
2

74LS04N
74LS04N
U2A
1
2 12
13

74LS11N 1
U4A
3
2
U2B
3
4 6
74LS32D
5

74LS11N 9
U4C
8
10 Y
9
U2C 74LS32D
10 8
11

74LS11N 4
U4B
6
5

1
U3A 74LS32D
2 12
13

74LS11N

TRUTH TABLE:

Select Inputs Output

S0 S1 Y
0 0 D0
0 1 D1
1 0 D2
1 1 D3

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

41
LOGIC DIAGRAM OF DEMULTIPLEXER:

S1 S0

I/P
U1A U1B
74LS04D

74LS04D

U2A

D0
74LS11N

U2B

D1
74LS11N

U2C

D2
74LS11N

U3A

D3
74LS11N

TRUTH TABLE:

Inputs Outputs
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1

42
BLOCK DIAGRAM OF 1:4 DEMULTIPLEXER:
PIN DIAGRAM

U1
~1G VCC
1A ~2G
1B 2A
1Y0 2B
1Y1 2Y0
1Y2 2Y1
1Y3 2Y2
GND 2Y3
74LS139N
FUNCTION TABLE:

Inputs Outputs
E A B Y0 Y1 Y2 Y3
1 X X 1 1 1 1
0 0 0 0 1 1 1
0 1 0 1 0 1 1
0 0 1 1 1 0 1
0 1 1 1 1 1 0

PROCEDURE:
(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

43
 PIN DIAGRAM OF IC 7442: PIN DIAGRAM OF IC 74147:

BCD TO Decimal Decoder: 10 Line to 4 Line Priority Encoder:

U1
VCC 8
15 A O0 1
14 B O1 2
13 C O2 3
12 D O3 4
O4 5
O5 6
O6 7
O7 9
O8 10
16 GND O9 11

74LS42N

LOGIC DIAGRAM OF 8 – TO – 3 LINE ENCODER:

D7 D6 D5 D4 D3 D2 D1 D0

U1A
1
3
2 U1C
9
74LS32N 8
U1B 10 A = D1+ D3 + D5 + D7
4
6 74LS32N
5
74LS32N

U2A
1
3
2 U2C
9
74LS32N 8
U2B 10 B = D2+ D3 + D6 + D7
4
6 74LS32N
5
74LS32N

U3A
1
3
2 U3C
9
74LS32N 8
U3B 10 C = D4+ D5 + D6 + D7
4
6 74LS32N
5
74LS32N

44
Date: DESIGN AND IMPLEMENTATION OF ENCODER AND
Expt. No.: DECODER

AIM:
To design and implement encoder and decoder using logic gates and study of IC
7442 and IC 74147.
APPARATUS REQUIRED:
Sl.No. COMPONENT SPECIFICATION QTY.
1. 3 I/P NAND GATE IC 7410 2
2. OR GATE IC 7432 3
3. NOT GATE IC 7404
4. DECODER IC 7441 1
5. ENCODER IC 74147 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 27

THEORY:
ENCODER:
An encoder is a digital circuit that perform inverse operation of a decoder. An
encoder has 2n input lines and n output lines. In encoder the output lines generates the
binary code corresponding to the input value. In octal to binary encoder it has eight
inputs, one for each octal digit and three output that generate the corresponding binary
code. In encoder it is assumed that only one input has a value of one at any given time
otherwise the circuit is meaningless. It has an ambiguity that when all inputs are zero the
outputs are zero. The zero outputs can also be generated when D0 = 1.

DECODER:
Decoder is a multiple input multiple output combinational digital circuit that
converts n number of coded binary inputs in to 2n number of coded binary outputs. In the
decoder, the combination of input information lines define the logic output of any one
output line as logic high at a time and rest of the output lines are being fixed to logic 0.
When the combination of input binary information changes the logic 1 output line also be
changes. Usually decoder produces unique output corresponding to each input pattern.
Therefore, the n to 2n decoder is also called as simple minterm generator with each output
corresponding to exactly one minterm. The enable input used in the diagram acts as a
controller of decoder. To operate the decoder the enable input must set as active high.

45
TRUTH TABLE – 8 – TO –3 – line Encoder:
Inputs Outputs
D7 D6 D5 D4 D3 D2 D1 D0 C B A
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

LOGIC DIAGRAM OF 2-TO-4 LINE DECODER:

En B A

U3B
U3A 74LS04N
74LS04N

U1A
1
2
13
12 Y0 = B A
74LS11N

U1B
3
4
5
6 Y1 = B A
74LS11N

U1C
9
10
11
8 Y2 = B A
74LS11N

U2A
1
2 12
13 Y3 = B A
74LS11N

46
TRUTH TABLE OF 2-TO-4 LINE DECODER:

Enable INPUTS OUTPUTS

En B A Y0 Y1 Y2 Y3
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1

PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.

(iii) Observe the output and verify the truth table.

RESULT:

47
 LOGIC DIAGRAM OF SR FLIP-FLOP: TRUTH TABLE:

U1A INPUTS OUTPUTS

S 1
3 9 U1C
2
10
8 Q CLK S R Q Q
74LS00D 0 0 0 NC NC
74LS00D
0 0 1 NC NC

CLK 0 1 0 NC NC
0 1 1 NC NC
1 0 0 NC NC
12 U1D
U1B 1 0 1 0 1
4
6 13
11 Q
R 5 1 1 0 1 0
74LS00D
74LS00D 1 1 1 0/1 0/1

LOGIC DIAGRAM OF D FLIP-FLOP: TRUTH TABLE:

1
U2A
D 3 9
U2C
2 8
10 Q
U3A 74LS00D INPUTS OUTPUTS
74LS00D
CLK D Q Q
74LS04N
0 X NC NC
1 0 0 1
CLK 1 1 1 0
12
U2D
4
U2B 11
6 13 Q
5
74LS00D
74LS00D

48
Date:
STUDY OF FLIP-FLOPS
Expt. No.:

AIM:
To construct and verify the truth table of a given flip-flops.
1. SR flip-flop
2. D flip-flop
3. JK flip-flop

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

NAND GATE IC 7400 1
NOT GATE IC 7404 1
IC TRAINER KIT - 1
PATCH CORDS - 30

THEORY:

FLIP-FLOP:
Flip-Flop is an edge triggered synchronous sequential logic circuit that is capable
of storing single bit binary information. A flip-flop consists of two outputs one for
normally stored binary bit and another one for complement of stored binary bit. It can
maintain the stored binary state indefinitely until driven by another input signal to switch
other state.

SR FLIP-FLOP:
SR (Set-Reset) flip-flop is a clocked sequential circuit which is controlled by edge
triggered CLK control signal. The change of clock signal from either each edge of logic 0
to logic 1 changes or each edge of logic 1 to logic 0 changes updates the output for a
response of change in input signal. The circuit output is only respond to the CLK not for
the change in inputs S and R.

49
LOGIC DIAGRAM OF JK FLIP-FLOP:

U2A
1
U1C
J 2 12 9
13
10
8 Q
74LS10N 74LS00D

CLK

U2B 12 U1D
3 11 Q
K 4
5
6 13
74LS00D
74LS10N

TRUTH TABLE:

INPUTS OUTPUTS
STATES
CLK J K Q Q
0 0 0 NC NC No Change
0 0 1 NC NC No Change
0 1 0 NC NC No Change
0 1 1 NC NC No Change
1 0 0 NC NC No Change (Present State = Next State)
1 0 1 0 1 Reset
1 1 0 1 0 Set
Toggles (complement of present state is
1 1 1 Q Q
equal to next state)

50
D FLIP-FLOP:
D flip-flop is used to eliminate the undesirable conditions that are present in the
SR flip-flop. It define only the set and reset condition of SR flip-flop. The logic diagram
of D flip-flop which satisfies the above consideration. The D flip-flop has only two inputs
such as data input D and control input CLK. The input D is Connected directly to the SR
flip-flop S and connected with an inverter to R. When an input D = 1, the flip-flop
represent the set condition while an input D = 0, the flip-flop represent the reset
condition. When the control input CLK is applied to the D flip-flop the input is applied to
develop the output for the response of change in input. When the applied clock pulse
CLK is equal to logic 1 the input D is stored in the flip-flop and the output Q is equal to
the input D. When the applied clock pulse CLK is equal to logic 0 the input D does not
applied to the flip-flop that maintains the data that stored previously on it and the output
Q is also equal to previous state output.

JK FLIP-FLOP:
JK flip-flop is a refinement of SR flip-flop in which the indeterminate state of SR
flip-flop is defined. The inputs of JK flip-flop J and K are behave like inputs of SR flip-
flop S (set) and R (reset) respectively. The input J is used to set the flip-flop, while K is
used to reset the flip-flop. When both inputs are high the output complements the
previous output that obtained from flip-flop. The previous output is called as present state
input while the present output is called as next state of flip-flop.

PROCEDURE:
1. Connections are given as per the logic diagram.
2. Apply the input data and verify the truth table.

RESULT:

51
 LOGIC DIAGRAM OF 4-BIT ASCHNCRONOUS (RIPPLE) UP-COUNTER:

HIGH (1)
U1A U1B U2A U2B
14 1J 1Q 12 7 2J 2Q 9 14 1J 1Q 12 7 2J 2Q 9
1 1CLK 5 2CLK 1 1CLK 5 2CLK
3 1K ~1Q 13 10 2K ~2Q 8 3 1K ~1Q 13 10 2K ~2Q 8
2 6 2 6
CLK ~1CLR ~2CLR ~1CLR ~2CLR

74LS73N 74LS73N 74LS73N 74LS73N

Q1 Q2 Q3 Q4
CLR (1)

TRUTH TABLE: PIN DIAGRAM OF IC 7473

INPUT OUTPUTS 1 1CLK 1J 14

CLK Q4 Q3 Q2 Q1 2 ~1CLR ~1Q 13
0 0 0 0
3 1K 1Q 12
0 4 11
VCC GND
1 0 0 0 1 5 2CLK 2K 10
2 0 0 1 0 6 ~2CLR 2Q 9
3 0 0 1 1 7 2J ~2Q 8
4 0 1 0 0
5 0 1 0 1 74LS73N
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

52
Date: VERIFICATION OF 4 BIT ASYNCHRONOUS (RIPPLE)
Expt. No.: COUNTER

AIM:
To construct and verify 4 bit ripple counter.

APPARATUS REQUIRED:

Sl. No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7473 2
2. IC TRAINER KIT - 1
3. PATCH CORDS - 30

THEORY:

UP-COUNTER:
Asynchronous counters are the circuit that used to count the binary numbers in
prescribed sequence. In asynchronous counter the flip-flops are not triggered with
common clock pulse. Except the first (least significant) flip-flop others are triggered by
the output of previous flip-flop while the first one is triggered by the clock pulse. Hence
asynchronous counter is also called as ripple counter. When inputs set into logic high the
JK flip-flops are continuously present in the toggle condition which complements the
output continuously. This cause to prevent the circuit from triggering of two adjacent
flip-flops simultaneously.

DOWN-COUNTER:
Asynchronous down counter performs the reverse operation of up-counter which
counts the binary number by decreasing one when the flip-flops are activated by the clock
pulse. First flip-flop triggered by clock pulse the remaining flip-flips are triggered by the
inverted output of previous flip-flop. It is an only difference from up-counter.

53
 LOGIC DIAGRAM OF 4-BIT ASCHNCRONOUS (RIPPLE) DOWN-COUNTER:
Q1 Q2 Q3 Q4

HIGH (1)
U1A U1B U2A U2B
14 1J 1Q 12 7 2J 2Q 9 14 1J 1Q 12 7 2J 2Q 9
1 1CLK 5 2CLK 1 1CLK 5 2CLK
3 1K ~1Q 13 10 2K ~2Q 8 3 1K ~1Q 13 10 2K ~2Q 8
2 6 2 6
CLK ~1CLR ~2CLR ~1CLR ~2CLR

74LS73N 74LS73N 74LS73N 74LS73N

CLR (1)

TRUTH TABLE: PIN DIAGRAM OF IC 7473

INPUT OUTPUTS 1 1CLK 1J 14

CLK Q4 Q3 Q2 Q1 2 ~1CLR ~1Q 13
0 1 1 1 1
3 1K 1Q 12
4 VCC GND 11
1 1 1 1 0 5 2CLK 2K 10
2 1 1 0 1 6 ~2CLR 2Q 9
3 1 1 0 0 7 2J ~2Q 8
4 1 0 1 1
5 1 0 1 0 74LS73N
6 1 0 0 1
7 1 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
15 0 0 0 0

54
PROCEDURE:
1. Connections are given as per the logic diagram.
2. Apply the clock pulse and verify the truth table.

RESULT:

55
 LOGIC DIAGRAM OF 4-BIT SCHNCRONOUS UP-COUNTER:
HIGH (1)

1
U5A
3 4
U5B
2 6 9
U5C
5 8
U1A 74LS08N U1B U2A 10 U2B
74LS08N
14 1J 1Q 12 7 2J 2Q 9 14 1J 1Q 12 74LS08N 7 2J 2Q 9
1 1CLK 5 2CLK 1 1CLK 5 2CLK
3 1K ~1Q 13 10 2K ~2Q 8 3 1K ~1Q 13 10 2K ~2Q 8
2 ~1CLR 6 ~2CLR 2 ~1CLR 6 ~2CLR

74LS73N 74LS73N 74LS73N 74LS73N

CLR (1) Q1 Q2 Q3 Q4

CLK

TRUTH TABLE: PIN DIAGRAM OF IC 7473

INPUT OUTPUTS 1 1CLK 1J 14

CLK Q4 Q3 Q2 Q1 2 ~1CLR ~1Q 13
0 0 0 0 0 3 1K 1Q 12
4 VCC GND 11
1 0 0 0 1
5 2CLK 2K 10
2 0 0 1 0
6 ~2CLR 2Q 9
3 0 0 1 1 7 8
4 0 1 0 0
2J ~2Q
5 0 1 0 1
6 0 1 1 0
74LS73N
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1

56
Date:
VERIFICATION OF 4 BIT SYNCHRONOUS UP-COUNTER
Expt. No.:
AIM:
To construct and verify 4 bit Synchronous counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7473 2
2. IC TRAINER KIT - 1
3. PATCH CORDS - 30

THEORY:
UP COUNTER: Synchronous counter is a circuit in that all flip-flops are
triggered by the common clock pulse. The common clock pulse is applied to all the flip-
flops simultaneously to update the output for the change of input by triggering. In the
logic diagram of 4-bit synchronous up counter four flip-flops are connected in series with
common clock pulse. The logic high input is applied to LSB flip-flop (1). The AND
output of first stage flip-flop Q1 and input is used to drive the J and K inputs os flip- flop
(2). The J and K inputs of flip-flop (3) is driven by the AND output of flip-flops (1) and
(2). Similarly, J and K inputs of flip-flop (4) is driven by the AND output of (2) and (3).
The Jk flip-flop employed in the synchronous counter operates only in two conditions
such as no change condition and toggle condition.

PROCEDURE:
1. Connections are given as per the logic diagram.
2. Apply the clock pulse and verify the truth table.

RESULT:

57
 LOGIC DIAGRAM OF 4-BIT SCHNCRONOUS UP / DOWN COUNTER:
Q1 Q2 Q3 Q4
UP / DOWN U1A
U6A 1 U1C
3 9 U2A
1 2 2 8 1
10 3
74LS08N 2
HIGH (1) 74LS04D 74LS08N
74LS08N
U4A U4B U5A U5B
14 1J 1Q 12 7 2J 2Q 9 14 1J 1Q 12 U3C 7 2J 2Q 9
1 1CLK U3A 5 2CLK U3B 1 1CLK 9 5 2CLK
3 1K ~1Q 13 1 10 2K ~2Q 8 4 3 1K ~1Q 13 8 10 2K ~2Q 8
3 6 10
2 ~1CLR 2 6 ~2CLR 5 2 ~1CLR 6 ~2CLR
74LS32D
74LS32D 74LS32D
74LS73D 74LS73D 74LS73D 74LS73D

4
U2B
12
U1D 6
4
U1B 11 5
6 13
5 74LS08N
74LS08N
74LS08N
CLR

CLK
TRUTH TABLE:

Control Inputs OUTPUTS Control Inputs OUTPUTS

CLK UP/DOWN Q4 Q3 Q2 Q1 CLK UP/DOWN Q4 Q3 Q2 Q1
0 Initial state 0 0 0 0 17 1 0 0 0 1
1 0 1 1 1 1 18 1 0 0 1 0
2 0 1 1 1 0 19 1 0 0 1 1
3 0 1 1 0 1 20 1 0 1 0 0
4 0 1 1 0 0 21 1 0 1 0 1
5 0 1 0 1 1 22 1 0 1 1 0
6 0 1 0 1 0 23 1 0 1 1 1
7 0 1 0 0 1 24 1 1 0 0 0
8 0 1 0 0 0 25 1 1 0 0 1
9 0 0 1 1 1 26 1 1 0 1 0
10 0 0 1 1 0
27 1 1 0 1 1
11 0 0 1 0 1
28 1 1 1 0 0
12 0 0 1 0 0
29 1 1 1 0 1
13 0 0 0 1 1
30 1 1 1 1 0
14 0 0 0 1 0
31 1 1 1 1 1
15 0 0 0 0 1
32 1 0 0 0 0
16 0 0 0 0 0

58
Date: VERIFICATION OF 4 BIT SYNCHRONOUS UP/DOWN
Expt. No.: COUNTER

AIM:
To construct and verify 3 bit Synchronous UP / DOWN counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7473 2
2. IC TRAINER KIT - 1
3. PATCH CORDS - 30

THEORY:
SYNCHRONOUS UP/DOWN COUNTER: Up/Down counter is a circuit which
perform the logic count either up or down by increasing or decreasing a number by 1.
Synchronous Up/Down counter is a circuit which executes the counting operation either
up or down with a commonly clocked flip-flops. In a counter the progress of Up and
Down counting operation s are selected by the control signal. After selecting the counting
operation by enforcing the clock pulses to the flip-flops desired counting operation is
executed. If the control signal is logic low (0) then the counter counts in the decreasing
order that is down counter. When the control signal is logic high (1) then the counter
counts in the increasing order that is up counter.

PROCEDURE:
1. Connections are given as per the logic diagram.
2. Apply the clock pulse and verify the truth table.

RESULT:

59
 LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:
1
U3A
3 CLR
2
74LS00N
HIGH (1)
U1A U1B U2A U2B
14 1J 1Q 12 7 2J 2Q 9 14 1J 1Q 12 7 2J 2Q 9
1 1CLK 5 2CLK 1 1CLK 5 2CLK
3 1K ~1Q 13 10 2K ~2Q 8 3 1K ~1Q 13 10 2K ~2Q 8
2 6 2 6
CLK ~1CLR ~2CLR ~1CLR ~2CLR

74LS73N 74LS73N 74LS73N 74LS73N

Q1 Q2 Q3 Q4

LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:

1
U6A
3 CLR
2

74LS00N
HIGH (1)
U4A U4B U5A U5B
14 1J 1Q 12 7 2J 2Q 9 14 1J 1Q 12 7 2J 2Q 9
1 1CLK 5 2CLK 1 1CLK 5 2CLK
3 1K ~1Q 13 10 2K ~2Q 8 3 1K ~1Q 13 10 2K ~2Q 8

2 6 2 6
CLK ~1CLR ~2CLR ~1CLR ~2CLR

74LS73N 74LS73N 74LS73N 74LS73N

Q1 Q2 Q3 Q4

TRUTH TABLE of MOD-10: TRUTH TABLE of MOD-12:

Input OUTPUTS Input OUTPUTS

CLK Q4 Q3 Q2 Q1 CLK Q4 Q3 Q2 Q1
0 0 0 0 0 0 0 0 0 0
1 0 0 0 1
1 0 0 0 1
2 0 0 1 0
2 0 0 1 0
3 0 0 1 1
3 0 0 1 1 4 0 1 0 0
4 0 1 0 0 5 0 1 0 1
5 0 1 0 1 6 0 1 1 0
7 0 1 1 1
6 0 1 1 0
8 1 0 0 0
7 0 1 1 1 9 1 0 0 1
8 1 0 0 0 10 1 0 1 0
9 1 0 0 1 11 1 0 1 1
10 0 0 0 0 12 0 0 0 0

60
Date:
VERIFICATION OF MODULO – N COUNTER
Expt. No.:

AIM:
To construct and verify the circuit of MOD 10 and MOD 12 ripple counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

4. JK FLIP FLOP IC 7473 2
5. NAND GATE IC7400 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 30

THEORY:

MODULO - N COUNTER: Modulo – N (mod – N) counter is a type of counter

that counts the N count sequence repeatedly by the control of clock pulse. The logic
circuit of mod-10 and 12 in its basic form is a BCD counter. However the presence of
NAND gate will alter this sequence as follows: the NAND gate output is connected to
the asynchronous RESET inputs of each flip-flops. As long as the NAND gate output is
high, it will have no effect on the counter. When it goes low, it will reset all the flip-flops
so that counter immediately goes to the 0000 state.

PROCEDURE:
1. Connections are given as per the logic diagram.
2. Apply the clock pulse and verify the truth table.

RESULT:

61
 LOGIC DIAGRAM FOR JOHNSON COUNTER:

PRE (1)
4 Q1 10 Q2 4 Q3 10 Q4
~1PR ~2PR ~1PR ~2PR
2 1D 1Q 5 12 2D 2Q 9 2 1D 1Q 5 12 2D 2Q 9
U1A U1B U2A U2B
74LS74N 74LS74N 74LS74N 74LS74N
3 1CLK ~1Q 6 11 2CLK ~2Q 8 3 1CLK ~1Q 6 11 2CLK ~2Q 8

CLK ~1CLR ~2CLR ~1CLR ~2CLR

1 13 1 13

CLR (1)

TRUTH TABLE OF JOHNSN COUNTER

Input OUTPUTS

CLK Q1 Q2 Q3 Q4

0 0 0 0 0

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 0 0 1

62
Date:
VERIFICATION OF JOHNSON COUNTER
Expt. No.:

AIM:
To construct and verify the circuit of MOD 10 and MOD 12 ripple counter.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. JK FLIP FLOP IC 7474 2
2. IC TRAINER KIT - 1
3. PATCH CORDS - 30

THEORY:
JOHNSON COUNTER: Johnson counter is a modified ring counter that the inverted
output of last flip-flop is applied input for first flip-flop. Hence it is also called as twisted
ring counter or switch tail ring counter. The diagram is constructed with series connected
common clocked four negative edge triggered flip-flops. Commonly clocked negative
edge triggered flip-flop shifts the binary data by one bit when the clock pulse is switched
from logic 1 to logic 0. The count sequence of Johnson counter is obtained by shifting the
numbers in circle for the triggering of each clock pulse.

PROCEDURE:
1. Connections are given as per the logic diagram.
2. Apply the clock pulse and verify the truth table.

RESULT:

63
LOGIC DIAGRAM: SERIAL-IN-SERIAL-OUT SHIFT REGISTER
SERIAL
4 10 4 10 DATA OUT
~1PR ~2PR ~1PR ~2PR
SERIAL 2 1D 5 12 9 2 5 12 9
U1A 1Q 2DU1B 2Q 1DU2A 1Q 2D U2B 2Q
DATA IN 74LS74N 74LS74N 74LS74N 74LS74N
3 1CLK ~1Q 6 11 2CLK ~2Q 8 3 1CLK ~1Q 6 11 2CLK ~2Q 8

CLK ~1CLR ~2CLR ~1CLR ~2CLR

1 13 1 13

CLR (1)

PIN DIAGRAM:

TRUTH TABLE OF SERIAL-IN-SERIAL-OUT SHIFT REGISTER

Binary data stored in

Serial Input Serial Output
Clock Pulse Register
Data In Q1 Q2 Q3 Q4 Data out = Q4
Initial Vaue 1111 0 0 0 0 0
After 1st Clk 111 1 0 0 0 0
After 2nd Clk 11 1 1 0 0 0
After 3rd Clk 1 1 1 1 0 0
After 4th Clk - 1 1 1 1 1

LOGIC DIAGRAM: SERIAL-IN-PARALLEL-OUT SHIFT REGISTER

PRE
PARALLEL DATA OUT
4
Q1 10 Q2 4 Q3 10 Q4
~1PR ~2PR ~1PR ~2PR
SERIAL 2 1D 5 12 9 2 5 12 9
U1A 1Q 2D
U1B 2Q 1D
U2A 1Q 2D
U2B 2Q
DATA IN 74LS74N 74LS74N 74LS74N 74LS74N
3 1CLK ~1Q 6 11 2CLK ~2Q 8 3 1CLK ~1Q 6 11 2CLK ~2Q 8

CLK ~1CLR ~2CLR ~1CLR ~2CLR

1 13 1 13

CLR (1)

64
Date:
DESIGN AND IMPLEMENTATION OF SHIFT REGISTER
Expt. No.:

AIM:
To design and implement
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35

THEORY:
SHIFT REGISTER: Shift register is a group of flip- flops that has the capability of
storing and shifting the binary information. In digital system the binary datum are
required to shift in the register from one position to next position. Shift register performs
the logic operation shifting of binary data from one flip-flop to next flip-flop. In the shift
register, the shifting operation is controlled by common clock pulse. All the flip-flops
employed with shift register receives the clock pulse that helps to shift the data from one
position to next.

SERIAL-IN-SERIAL-OUT SHIFT REGISTER: This Shift register is constructed in

the way of connecting the output of one flip-flop to the input of next flip –flop. All the
flip-flops are connected with a common clock pulse. The binary inputs are applied in the
input terminal of first flip-flop in series and the outputs are obtained from the output
terminal of last flip-flop in series.

65
 TRUTH TABLE OF SERIAL-IN-PARALLEL-OUT SHIFT REGISTER

Serial Input Parallel Output

Clock Pulse
Data In Q1 Q2 Q3 Q4
Initial Vaue 1011 0 0 0 0
After 1st Clk 111 1 0 0 0
After 2nd Clk 11 1 1 0 0
rd
After 3 Clk 1 0 1 1 0
th
After 4 Clk - 1 0 1 1

LOGIC DIAGRAM: PARALLEL-IN-PARALLEL-OUT SHIFT REGISTER

PARALLEL DATA IN
I 4 I 10 I 4 I 10
1 2 3 4
~1PR ~2PR ~1PR ~2PR
2 1D 5 12 9 2 5 12 9
U3A 1Q 2D
U3B
2Q 1D
U4A 1Q 2D
U4B
2Q

74LS74N 74LS74N 74LS74N 74LS74N

3 1CLK ~1Q 6 11 2CLK ~2Q 8 3 1CLK ~1Q 6 11 2CLK ~2Q 8

CLK ~1CLR Q ~2CLR

Q ~1CLR
Q ~2CLR
1 2 3 Q
1 13 1 13 4
PARALLEL DATA O UT

CLR (1)

TRUTH TABLE OF PARALLEL-IN-PARALLEL-OUT SHIFT REGISTER

Parallel Input Parallel Output

Clock Pulse
I1 I2 I3 I4 Q1 Q2 Q3 Q4
Initial Value 0 0 0 0 0 0 0 0
After 1st Clk 1 0 0 0 1 0 0 0
nd
After 2 Clk 1 1 0 0 1 1 0 0
rd
After 3 Clk 0 1 1 0 0 1 1 0
After 4th Clk 1 0 1 1 1 0 1 1

66
SERIAL-IN-SERIAL-OUT SHIFT REGISTER: This register accepts the binary data
in series to provide the output in parallel. In logic diagram the flip-flops are connected
similar to SISO shift register that logic diagram is constructed in the way of connecting
the output of one flip-flop to the input of next flip-flop. The binary inputs are applied in
the input terminal of first flip-flop in series and the outputs are obtained in parallel from
the output terminal of each flip-flop employed with register. Hence this configuration is
called serial-in-serial-out shift register.

PARALLEL-IN-PARALLEL-OUT SHIFT REGISTER: This register accepts the

binary input in parallel to provide the output in parallel. All the flip-flops present in the
register are triggered with common clock pulse. The binary inputs are applied in parallel
to all the flip-flops and the outputs are obtained in parallel from the output terminal of
each flip-flop employed with register. Hence this configuration is called parallel-in-
parallel-out shift register.

PARALLEL-IN-SERIAL-OUT SHIFT REGISTER: This register accepts the binary

input in parallel to provide the output in series form right most flip-flop. The logic
diagram is constructed by flip-flop and combination of logic gates. The combinational
logic gates are functioning as a control circuit to load the input of shift the stored binary
information. A control signal ‘shift’ is an active high signal i.e., when the control signal
line is activated with logic high input a shift register performs the shifting operation. A
control signal 'Write' is an active low signal i.e. when the control signal line is activated
with logic low input a shift register loads the newly appeared input signals into the flip-
flops in parallel. These logic operations are controlled by the combinational circuits.

67
LOGIC DIAGRAM: PARALLEL-IN-SERIAL-OUT SHIFT REGISTER
SHIFT / WRITE

1
U6A I1 I2 I3 I4
74LS04D

1
U1A 9
U1C 1
U2A
3 8 3
2 10 2
74LS08N U5A 74LS08N U5B 74LS08N U5C
1 4 9
3 6 8

4
U1B 2
12
U1D 5
4
U2B 10

6 74LS32N 11 74LS32N 6 74LS32N

5 13 5
74LS08N 74LS08N 74LS08N

PRE
4 10 4 10
~1PR ~2PR ~1PR ~2PR
2 1D 5 12 9 2 5 12 9
U3A 1Q 2D
U3B 2Q 1DU4A 1Q 2D
U4B 2Q
74LS74N 74LS74N 74LS74N 74LS74N
3 1CLK ~1Q 6 11 2CLK ~2Q 8 3 1CLK ~1Q 6 11 2CLK ~2Q 8

~1CLR ~2CLR ~1CLR ~2CLR

CLK
1 13 1 13
SEIRAL
DATA OUT
CLR (1)

TRUTH TABLE OF PARALLEL-IN-PARALLEL-OUT SHIFT REGISTER

Control signals Parallel Input Serial Output

Clock Pulse SHIFT / WRITE I1 I2 I3 I4 Q4
0 X 0 0 0 0 No Change (Initial state)
1 0 0 0 0 1 1
1 0 1 1 0 0 0
1 1 1 1 0 0
1 1 1 1 0
1 1 1 1
1 1 - 1

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

68
Date: STUDY OF ICS - REGISTER, DECADE COUNTER AND
Expt. No.: RIPPLE COUNTER

AIM:
To study the given ICs (IC 7495, IC7490 and IC7493)

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. REGISTER IC IC 7495 1
2. DECADE COUNTER IC IC 7490 1
3. RIPPLE COUNTER IC IC 7493 1
4. IC TRAINER KIT - 1
5. PATCH CORDS - 35

THEORY:

IC-74LS95 chip Study:

Description: The IC-74LS95 is a 4-bit shift register with serial and parallel
synchronous operating modes. It has serial data (DS) and four parallel data (D0 – D3)
inputs and four parallel outputs (Q0 – Q3). The serial or parallel mode of operation is
controlled by a mode select input (S) and two clock (CP1 and CP2 ) inputs. The serial
(shift right) or parallel data transfers occur synchronously with the HIGH – to – LOW
transition of the selected clock input.
When the mode select input (S) is CP2 HIGH, is enabled. A HIGH – to –
LOW transition on CP2 enabled loads parallel data from the (D0 – D3) inputs into the
CP1
CP1

register. When (S) is low, is enabled. A HIGH – to – LOW transition on enabled shifts
the data from serial input DS to Q0 and transfers the data from Q0 to Q1, Q1 to Q2 and Q2
to Q3 respectively (shift right). Shift left is accomplished by externally connecting Q3 to
D2, Q2 to D1 and Q1 to D0 and operating the IC-74LS95 in the parallel mode (S = HIGH)

69
70