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RTL Design of AHB Protocol

AHB implements the features required for high-performance, high clock frequency systems including:
o Burst transfers.
o Single clock-edge operation.
o Non- tristate implementation.
o Wide data bus configurations.
The most common slaves are internal memory devices, external memory interface, and high-bandwidth
peripherals.

AHB Block Diagram

This block diagram shows only single master AHB system design with the AHB master and 3AHB slaves. The bus
interconnect logic consists of one address decoder and a slave to master multiplexer. The decoder monitors the
address from the master so that the appropriate slave is selected and the multiplexer routes the corresponding
slave output data back to the master.
While AHB also support multi master designs by the use of an interconnect component that provides arbitration
and routing signals from different masters to the appropriate slaves.

[Note Only the main address and data buses and typical data routing are shows in this block diagram.]

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master =>
A master provides address and control information to initiate read and write operations. Below diagram
shows a master interface.

Slave =>
A slave responds to transfers initiated by master in the systems. The slave uses the HSELx select signal
from the decoder to control when it responds to a bus transfer.
The slave signal back to the master:
o The completion or extension of the bus transfer.
o The success or failure of the bus transfer.

Interconnect =>
An interconnect provides the connection between masters and slaves in a system.
• In case of single master system only requires the use of a Decoder and Multiplexer.
• While in case of multi master system requires the use of an interconnect that provides arbitration and the
routing of signals from different masters to the appropriate slaves. The routing is required for address,
control, and write data signals.
Decoder =>Decoder decodes the address of each transfer and provides a select signal for the slave that is
involved in the transfer. It also provides a control signal to the multiplexer.
A single centralized decoder is required in all implementations that use two or more slaves.

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Multiplexer =>
A slave to master multiplexer is required to multiplex the read data bus and response signals from
the slaves to the master. The decoder provides control for the multiplexer.
A single centralized multiplexer is required in all implementations that use two or more slaves.

Signal Descriptions
Name Destination Description
Global Signals
HCLK The bus clock times all bus transfers. All signal timings are related to the rising
edge of HCLK.
HRESETn The bus reset signal is active LOW and resets the system and the bus. This is
the only active LOW signal.
Master Signals
HADDR [31:0] Slave and The 32-bit system address bus.
Decoder
HBURST [2:0] Slave The burst indicates if the transfer is a single transfer or forms parts of burst.
Fixed length bursts of 4, 8, 16 beats are supported.
HMASTERLOCK Slave When HIGH indicates that the current transfer is part of a locked sequence.
It has the same thing as the address and control signals.
HPROT Slave The protection control signals provide additional information about a bus
access and indicate how an access should handle within a system.
HSIZE [2:0] Slave Indicates the size of the transfer, that is typically byte, halfword, or word.
This protocol allows for larger transfer sizes up to a maximum of 1024 bits.
HMASTER [3:0] Access Master identifier. Generated by a master if it has multiple Exclusive capable
monitor threads.
HTRANS [1:0] Slave Indicates the transfer type of the current transfer. This can be: IDLE, BUSY,
SEQUENTIAL, NONSEQUENTIAL.
HWDATA [31:0] Slave The write data bus transfers data from the master to the slaves during write
operations.
HWRITE slave Indicates the transfer direction. When HIGH this signal indicates a write
transfer and when LOW a read transfer.
Slave Signals
HRDATA [31:0] MUX During read operations, the read data bus transfers data from the selected
Slave to the multiplexer. The multiplexer then transfers the data to the master.
HREADYOUT MUX When HIGH, the HREADYOUT signal indicates that a transfer has finished on
the Bus. This signal can be driven LOW to extract a transfer.
HRESP MUX The transfer response, after passing through the multiplexer, provides the
Master with additional information on the status of a transfer.
Decoder Signals
HSELx Slave Each slave has its own slave signal HSELx and this signal indicates that the
current transfer is intended for the selected slave. When the slave in initially
selected, it must also monitor the status of HREADY to ensure that previous
bus transfer has completed, before it responds to the current transfer.
The HSELx signal is a combinatorial decode of the address bus.
Multiplexer Signals
HRDATA [31:0] Master Read data bus, selected by the decoder.
HREADY Master and When HIGH, the HREADY signal indicates to the master and all slaves, that the
Slave previous transfer is complete.
HRESP Master Transfer response, selected by the decoder.

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Transfers
1. Basic Read Transfer =>

2. Basic Write Transfer =>

3. Read Transfer with two wait state =>

4. Write Transfer with one wait state =>

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5. Undefined Length Bursts, INCR =>

6. Four-beat Wrapping Burst, WRAP4 =>

7. Four- beat Incrementing Burst, INCR4 =>

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Tools =>
Schematic: Quartus Prime (FSM viewer), Xilinx Vivado
Simulator – Xilinx Vivado

Simulation Result=>
1. Decoder waveform

2. Multiplexer waveform

3. *Top Module waveform*

4. Basic Write Read waveform

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5. Wait State Write Read waveform

6. Undefined Length Bursts, INCR waveform

7. Four-beat Wrapping Burst, WRAP4 waveform

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8. Four- beat Incrementing Burst, INCR4 waveform

*RTL Schematic =>

*FSM (Finite State machine) Schematic =>

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2. Slave1

3. Slave2

4. Slave3

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5. Slave4

Check my previous post : “RTL Design of AXI Stream Protocol”.

Reference: ARM IHI 0033B.b

✔️ For source code ping me on LinkedIn.

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