COA Course File For Data Science
COA Course File For Data Science
COA Course File For Data Science
Sponsored by
Lavu Educational Society
(Approved by AICTE and Affiliated to JNT University, Hyderabad)
Course File
For
By
CH RAMAIAH
Assistant Professor EEE Department
CONTENTS
6 Academic Calender 7
7 Time Table 8
10 Course Objectives 14
To evolve into a center of excellence in Science & Technology through creative and innovative
internationally accepted competitive and world class professionals who are psychologically strong and
To provide high quality academic programmes, training activities, research facilities and opportunities
leadership and research aptitude among students and contribute to the economic and technological
PEO2: To provide knowledge based services so as to meet the needs of the society and industry.
PEO3: To make the students understand, design and implement the concepts in multiple arenas.
PEO4: Graduates with leadership skills, Lifelong learning ability for a successful professional Career.
To educate the students in disseminating the research findings with good soft skills so as to become
successful entrepreneurs.
4. PROGRAM OUTCOMES (POs)
Engineering Graduates will be able to:
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and
an engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate review research literature and analyze complex engineering
problems reaching substantiated conclusions using first principle of mathematics, natural science and
engineering science.
3. Design/development of solutions: Design solutions for complex engineering problems and design
system components or processes that meet the specified needs with appropriate consideration for the public
health and safety, and the cultural, societal, and environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research methods
including design of experiments, analysis and interpretation of data, and synthesis of the information to provide
valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with an
understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal,
health, safety, legal and cultural issues and the consequent responsibilities relevant to the professional
engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering solutions in
societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the
engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in diverse
teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the engineering and
management principles and apply these to one's own work, as a member and leader in a team, to manage projects
and in multidisciplinary environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.
PSO-1 Students were enabled to apply the core engineering subjects related to Digital signal processing, Signal
and Systems also Electrical circuits, Manufacturing knowledge in analysis and to conduct experimental
investigation of complex mechanical products / systems.
PSO-2 Graduates were enabled to use the modern modeling and finite element analysis software’s in
developing the new mechanical products and also demonstrates the social responsibility, professional ethics and
environmental safety in their professional and personal life.
PSO-3 Co-curricular activities in collaboration with industries, R&D centers and professional bodies and also
extra-curricular activities enable the students to acquire organizing abilities, team & competitive spirit,
communication & management skills and knowledge of emerging technologies.
6. ACADEMIC CALENDER
7. TIME TABLE
8. ROLL LIST
44
21891A6745 PATIBANDLA RADHIKA SWATHI
21891A6746 PEDDI.AKSHAY
45
21891A6747 P.TANISH REDDY
46
21891A6748 P SAI VINAY
47
21891A6749 RALLABANDI UDAY
48
21891A6750 RAPOL PRANEETH KUMAR
49
21891A6751 R.SAICHARAN
50
21891A6752 SEETHA NIKHIL VARMA
51
21891A6753 S. SAI KARTHIK
52
21891A6754 KOLHE SRINIVAS
53
21891A6755 SRIPADA PALLAVI
54
21891A6756 SURAKANTI SOWMYA SREE
55
21891A6757 SUREPALLY MOKSHA SRI
56
21891A6758 VANUKURI HEMANTH REDDY
57
21891A6759 VASA KRUTHI
58
21891A6760 VASA SRUTHI
59
21891A6761 VEDANTAM SRI VAISHNAVI
60
21891A6762 VELUTURUMAL LI BHAVITHA NAGA PRASUNA
61
62 21891A6763 VOGETI ABHINAV KUMAR
21891A6764 V.SAICHARAN
63
21891A6765 YALLATI AMITH
64
22895A6701 MINNAKANTI SAI KRISHNA CHAITANYA
65
22895A6702 PULLURI NISHABHAVANI
66
22895A6703 VEMUGANTI NIHARIKA
67
22895A6704 GUTTULA HUMA RAJESH
68
69 22895A6705 KAVALI VAMSHI KRISHNA
UNIT - II
Microprogrammed Control: Control memory, Address sequencing, micro program
example, design
of control unit.
Central Processing Unit: General Register Organization, Instruction Formats,
Addressing modes,
Data Transfer and Manipulation, Program Control.
UNIT - III
Data Representation: Data types, Complements, Fixed Point Representation,
Floating Point
Representation.
Computer Arithmetic: Addition and subtraction, multiplication Algorithms,
Division Algorithms,
Floating – point Arithmetic operations. Decimal Arithmetic unit, Decimal Arithmetic
operations.
UNIT - IV
Input-Output Organization: Input-Output Interface, Asynchronous data transfer,
Modes of Transfer,
Priority Interrupt Direct memory Access.
Memory Organization: Memory Hierarchy, Main Memory, Auxiliary memory,
Associate Memory,
Cache Memory.
.
UNIT - V
Reduced Instruction Set Computer: CISC Characteristics, RISC Characteristics.
Pipeline and Vector Processing: Parallel Processing, Pipelining, Arithmetic
Pipeline, Instruction
Pipeline, RISC Pipeline, Vector Processing, Array Processor.
Multi Processors: Characteristics of Multiprocessors, Interconnection Structures,
Interprocessor
arbitration, Interprocessor communication and synchronization, Cache Coherence.
TEXT BOOK:
1. Computer System Architecture – M. Moris Mano, Third Edition, Pearson/PHI.
REFERENCES:
1. Computer Organization – Car Hamacher, Zvonks Vranesic, Safea Zaky, Vth
Edition, McGraw
Hill.
2. Computer Organization and Architecture – William Stallings Sixth Edition,
Pearson/PHI.
3. Structured Computer Organization – Andrew S. Tanenbaum, 4th Edition,
PHI/Pearson
10. COURSE OBJECTIVES
2)It begins with basic organization, design, and programming of a simple digital
computer and introduces simple register transfer language to specify various
computer operations.
C204.1 Understand the basics of instructions sets and their impact on processor design.
C204.2 Demonstrate an understanding of the design of the functional units of a digital computer
system
C204.3 Evaluate cost performance and design trade-offs in designing and constructing a computer
processor including memory
C204.4 Design a pipeline for consistent execution of instructions with minimum hazards.
Descriptive Questions
UNIT – I
2 CO1 PO1 L2
Define Micro operations? List out the types of Micro CO1 PO1 L1
b 3
operations?
What are the Logical Micro operations and Explain the CO1 PO1 L3
c 5
applications of Logical Micro operations
UNIT-2
QNO Description of Question Marks Course Progra BTL
outcome m
(CO) Outcom
e(PO)
CO2 PO1 L2
2
b Explain symbolic microinstruction format with example 3 CO2 PO1 L2
With the help of a block diagram , explain how do we select CO2 PO2 L2
c the address of control memory 10
Evaluate the following arithmetic statement using zero, one, CO2 PO3 L2
d two and three address instructions. Use the conventional 5
symbols and instructions. X = (A+B) * (C+D).
UNIT-3
QN Description of Question Marks Course Program BTL
O outcome Outcome
(CO) (PO)
CO3 PO1 L3
Give the 2's complement notation for the following signed CO3 PO1 L3
2 b decimal numbers 3
for 8 bit word i.) +1 ii) +127 iii) -1 iv) -64.
Represent 32.75 and 18.125 in single precision IEEE 754 5 CO3 PO1 L2
Representation
d ____
CO3
4 Show the hardware to be used for Multiplication with signed CO3 PO3 L2
a 2
magnitude numbers
Perform the operation (-9)+(-6)= -15 with binary numbers in CO3 PO1 L3
a signed 2’s complement representation using only five bits to 2
represent each number (including the sign).
UNIT-4
2 a 2 CO4 PO2 L1
How many characters per second can be transmitted over a CO4 PO2 L3
a 2
1200 baud line in Synchronous serial transmission?[
Explain the different types mapping techniques are used in CO4 PO1 L2
c 10
usage of the cache memory
c How many 128 × 8 RAM chips are needed to provide a 5 CO4 PO2 L2
memory capacity of 2048 bytes? How many lines of
address bus must be used to access 2048 bytes of memory?
How many of these lines will be common to all chips?
With the help of a neat diagram explain the match logic for CO4 PO3 L2
d 5
one word of Associative Memory
UNIT-5
QNO Description of Question Marks Course Program BTL
outcom Outcome
e (CO) (PO)
CO5 PO1 L1
iii) How many stages and how many Switches in each stage
are needed in a n x n omega switching network.
How many switch points are there in a crossbar switch CO5 PO1 L2
b 3
network that connects p processors to m memory modules
6 What are the various forms available for establishing an CO5 PO1 L2
c 5
interconnection network in a multi processor system?
Objective Questions
UNIT – I
b. The determination of what hardware should be used and how the parts
be connected.
2. The part of the hardware of computer that controls the transfer of information
between
computer and the outside word is
[ ]
7. To design a common bus system for 4 register of 4-bits each, by using tristate
buffers and a decoder, what is the size of the decoder?
[ ]
a) 2 to 4 Decoder b) 3 to 8 Decoder c) 4 to 16 Decoder d)5 to 32 decoder
8. If the address field of an instruction specifies the effective address, then the
instruction is
[ ]
a) Immediate Instruction b) Direct Instruction c) Indirect Instruction d) None
9 There are ___________ different logical operations that can be performed with 2
binary variables
[ ]
a) 2 b) 4 c) 8 d) 16.
10. In the Binary Adder/subtractor if M=0 the circuit is __________
[ ]
a) adder b) subtractor c) both adder & subtractor d) exclusive Binary Operation.
11. The _________ operation is similar to the selective clear operation except that
the bits of A are cleared only where there are corresponding 0's in B.
[ ]
a) Selective – set b) Selective – complement c) Mask d) Insert .
12. The type of shift used to shift the contents of a register which contains a signed
binary number is called ___________
13. If the memory size is 4096*16, then ___ address lines are required to address any
memory location
14. The ______________ operation sets to 1 bit in register A where there are
corresponding 1’s in register B.
15. Description of SPA instruction ______________________________
UNIT – 2
1. The control logic is implemented with gates, flip-flops, decoders, and other digital
circuits. [ ]
12 In the Micro instruction code Format the condition field consists of two bits
which are encoded to specify_______ status bit conditions
13 A _____________ requires changes in the wiring among the various components
if the design has to be modified (or) changed.
14. The transformation from the instruction code bits to an address in control
memory where the routine located is referred as __________
15. In Micro programmed organization, the control information is stored in
_______________
16. A control unit whose binary control variables are stored in memory is called
_____________ control unit
17 The register that holds the address for the stack is called __________
18 Internal interrupts are also called as ___________
19 The implied operand of an operation in a single accumulator organization is
_____________
20.In a memory stack, after the pop operation, the stack pointer will be
____________
UNIT – 3
2. In the Hardware for Signed –Magnitute addition and subtraction two magnitudes
are subtracted if the sign are different for an ________ Operation (or) identical for an
________ operation. [ ]
c. 111100111010011111000010 d. 111110011001100000010010
7. Perform the subtraction with the following unsigned decimal number by
[ ]
16. In BCD addition, when the binary sum is greater than 1001, then addition of
_______ converts the binary sum to correct BCD representation
18. In a Array multiplier circuit with ‘j’ multiplier bits and ‘k’ multiplicand bits, the
number of
AND gates required are ___________
19. A divide overflow condition occurs, if the high order half bits of the dividend is
__________________
20. ___________ algorithm specifies a procedure for multiplying two binary integers
in Signed 2’s complement.
UNIT-4
1. Machines whose instructions generate 32-bit address can utilize a memory that
contains up to _______ memory locations
[ ]
UNIT-5
1. The speed up of a pipeline processing over an equivalent non-pipeline processing
is defined by the ratio S =_________
[ ]
A. ntn /(k+n-1)tp B. ntp/(k+n-1)tn C.ntn /(k+n+1)tp D.ntp/(k-n-1)tn
2 The ______ organization consists of a number of cross points that are placed at
intersections between processors buses and memory module paths.
[ ]
A. Multiport memory B. Hypercube system C. Crossbar
Switch D. Time –shared common bus
3. Application of Vector Processing is
[ ]
A. Library System B. Medical Diagnosis C. Seismic Wave Analysis D. Space
Research
20 Each processor element in a _______________ system has its own private local
memory
UNIT-II
Learning Objectives:
UNIT-III
Data Representation,Computer Arithmetic
Learning Objectives:
UNIT-IV
UNIT-V
RISC,Pipeline and Vector Processing,Multi Processors
Learning Objectives:
---