COA Course File For Data Science

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Department Of Computer Science and Engineering (Data Science)

Sponsored by
Lavu Educational Society
(Approved by AICTE and Affiliated to JNT University, Hyderabad)

Course File

COMPUTER ORGANIZATION AND ARCHITECTURE

For

II Year B.Tech I Sem(Regulation-R18)

By
CH RAMAIAH
Assistant Professor EEE Department

CONTENTS

Sl. No. PARTICULARS PAGE NO.

1 Vision & Mission of the College 1

2 Vision & Mission of the Department 2

3 Programme Educational Objectives(PEOs) 3

4 Program Outcomes 4-5

5 Program Specific Outcomes 6

6 Academic Calender 7

7 Time Table 8

8 Roll List 9-12

Syllabus Copy with Information of


9 13
a. Text books
b. Reference books
c. Online resources

10 Course Objectives 14

11 Course Outcomes (COs) 15

12 Lecture Plan 16-19

13 Question bank( Descriptive & Objective) 20-31

14 Unit Wise Learning Objectives 32-33

15 Assignment Test Question Papers -

16 Mid -I , Mid -II Question Paper( Descriptive & Objective ) 34-37


17 Mid -I , Mid -II Scheme of Evaluation 38-53

18 Mid -I, Mid-II Marks 54-65

19 Model papers( if it is new subject) -

20 Previous Year University Question Papers 65-66

21 Subject Hand Written Notes DS

22 Unit Wise PPT DS

1.1. VISION OF THE COLLEGE

To evolve into a center of excellence in Science & Technology through creative and innovative

practices in teaching-learning, promoting academic achievement & research excellence to produce

internationally accepted competitive and world class professionals who are psychologically strong and

emotionally balanced imbued with social consciousness and ethical values.

1.2. MISSION OF THE COLLEGE

To provide high quality academic programmes, training activities, research facilities and opportunities

supported by continuous industry-institute interaction aimed at employability, entrepreneurship,

leadership and research aptitude among students and contribute to the economic and technological

development of the region, state and nation.


2.1. DEPARTMENT (CSD) VISION
To emerge as a premier center for education and research in computer science and engineering and in
transforming students into innovative professionals of contemporary and future technologies to cater
the global needs of human resources for IT and ITES companies .

2.2. DEPARTMENT (CSD) MISSION


1. To produce excellent computer science professionals by imparting quality training, hands-on-
experience and value based education.
2. To strengthen links with industry through collaborative partnerships in research & product
development and student internships.
3. To promote research based projects and activities among the students in the emerging areas of
technology.
4. To explore opportunities for skill development in the application of computer science among
rural and under privileged population.

3. PROGRAM EDUCATIONAL OBJECTIVES (PEOs)


PEO1: To create and sustain a community of learning in which students acquire knowledge and apply
in their concerned fields with due consideration for ethical, ecological, and economic issues.

PEO2: To provide knowledge based services so as to meet the needs of the society and industry.

PEO3: To make the students understand, design and implement the concepts in multiple arenas.

PEO4: Graduates with leadership skills, Lifelong learning ability for a successful professional Career.
To educate the students in disseminating the research findings with good soft skills so as to become
successful entrepreneurs.
4. PROGRAM OUTCOMES (POs)
Engineering Graduates will be able to:

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering fundamentals, and
an engineering specialization to the solution of complex engineering problems.

2. Problem analysis: Identify, formulate review research literature and analyze complex engineering
problems reaching substantiated conclusions using first principle of mathematics, natural science and
engineering science.

3. Design/development of solutions: Design solutions for complex engineering problems and design
system components or processes that meet the specified needs with appropriate consideration for the public
health and safety, and the cultural, societal, and environmental considerations.

4. Conduct investigations of complex problems: Use research-based knowledge and research methods
including design of experiments, analysis and interpretation of data, and synthesis of the information to provide
valid conclusions.

5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities with an
understanding of the limitations.

6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess societal,
health, safety, legal and cultural issues and the consequent responsibilities relevant to the professional
engineering practice.

7. Environment and sustainability: Understand the impact of the professional engineering solutions in
societal and environmental contexts, and demonstrate the knowledge of, and need for sustainable development.

8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and norms of the
engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader in diverse
teams, and in multidisciplinary settings.

10. Communication: Communicate effectively on complex engineering activities with the engineering
community and with society at large, such as, being able to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive clear instructions.

11. Project management and finance: Demonstrate knowledge and understanding of the engineering and
management principles and apply these to one's own work, as a member and leader in a team, to manage projects
and in multidisciplinary environments.

12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.

5. PROGRAM SPECIFIC OUTCOMES (PSOs)

PSO-1 Students were enabled to apply the core engineering subjects related to Digital signal processing, Signal
and Systems also Electrical circuits, Manufacturing knowledge in analysis and to conduct experimental
investigation of complex mechanical products / systems.

PSO-2 Graduates were enabled to use the modern modeling and finite element analysis software’s in
developing the new mechanical products and also demonstrates the social responsibility, professional ethics and
environmental safety in their professional and personal life.

PSO-3 Co-curricular activities in collaboration with industries, R&D centers and professional bodies and also
extra-curricular activities enable the students to acquire organizing abilities, team & competitive spirit,
communication & management skills and knowledge of emerging technologies.
6. ACADEMIC CALENDER
7. TIME TABLE
8. ROLL LIST

VIGNAN INSTITUTE OF TECHNOLOGY & SCIENCE


B.TECH II YEAR I SEMESTER ROLL LIST ACADEMIC YEAR - 2022-23
BRANCH: CSD
S. No HTNO Name Remarks
21891A6701 A.ABISHITHA REDDY
1
21891A6702 AERRA SHIVAJI
2
21891A6703 A.ROHITH
3
21891A6704 B.PRADEEP REDDY
4
21891A6705 BV SAI KISHORE
5
21891A6706 BANDLA ROHAN KRISHNA
6
21891A6708 BELAPU KARTHIK RAO
7
21891A6709 B V K PREETHI
8
21891A6710 BOBBILI JOSHNA
9
21891A6711 D JAYANTH
10
21891A6712 DANURI SAHITHI
11
21891A6713 DAYYALA CHANDAN KUMAR
12
21891A6714 SUJANA DUDYALA
13
21891A6715 FATHIMA SULTHANA
14
21891A6716 GAJAM.SRI VAISHNAVI
15
21891A6717 GANGADEVI SHRILAXMI
16
21891A6718 GANGAPURAM SIDDARTHA
17
21891A6719 GINJALAVARSH A
18
21891A6720 GUNTI TRIVENI
19
21891A6721 J.SRUTHI
20
21891A6722 J.SAHASRA
21
21891A6723 JANGAM ROHITH KUMAR
22
21891A6724 K.SAI NITHIN
23
21891A6725 JAI HIND REDDY
24
21891A6726 KASARLA JAHNAVI
25
21891A6727 KASULA MAHESH BABU
26
21891A6728 K.AISHWARYA
27
21891A6729 KONETI VIJAYARAMARA JU
28
21891A6730 LANGARI SRAVYA
29
21891A6731 LIKKY KARTHIK REDDY
30
21891A6732 M. YASHWITHA
31
21891A6733 MADDI NITHIN REDDY
32
21891A6734 M.BHARATH KUMAR
33
21891A6735 MAILARAM BHANUPRIYA
34
21891A6736 MANNE TEJASWINI
35
21891A6737 MD.AMANULLA H
36
21891A6738 MIHIR KUMAR RAI
37
38 21891A6739 MD SABA SULTANA
21891A6740 N SAMPATH REDDY
39
21891A6741 NIVAS THADAKAMALL A
40
21891A6742 P AKHIL SAGAR
41
21891A6743 PALEPU SUMITH
42
21891A6744 P.MAYUKA REDDY
43

44
21891A6745 PATIBANDLA RADHIKA SWATHI

21891A6746 PEDDI.AKSHAY
45
21891A6747 P.TANISH REDDY
46
21891A6748 P SAI VINAY
47
21891A6749 RALLABANDI UDAY
48
21891A6750 RAPOL PRANEETH KUMAR
49
21891A6751 R.SAICHARAN
50
21891A6752 SEETHA NIKHIL VARMA
51
21891A6753 S. SAI KARTHIK
52
21891A6754 KOLHE SRINIVAS
53
21891A6755 SRIPADA PALLAVI
54
21891A6756 SURAKANTI SOWMYA SREE
55
21891A6757 SUREPALLY MOKSHA SRI
56
21891A6758 VANUKURI HEMANTH REDDY
57
21891A6759 VASA KRUTHI
58
21891A6760 VASA SRUTHI
59
21891A6761 VEDANTAM SRI VAISHNAVI
60
21891A6762 VELUTURUMAL LI BHAVITHA NAGA PRASUNA
61
62 21891A6763 VOGETI ABHINAV KUMAR
21891A6764 V.SAICHARAN
63
21891A6765 YALLATI AMITH
64
22895A6701 MINNAKANTI SAI KRISHNA CHAITANYA
65
22895A6702 PULLURI NISHABHAVANI
66
22895A6703 VEMUGANTI NIHARIKA
67
22895A6704 GUTTULA HUMA RAJESH
68
69 22895A6705 KAVALI VAMSHI KRISHNA

70 22895A6706 S NETHAJI GOUD

9. JNTUH SYLLABUS (R18 REGULATION)


UNIT - I
Digital Computers: Introduction, Block diagram of Digital Computer, Definition of
Computer
Organization, Computer Design and Computer Architecture.
Register Transfer Language and Micro operations: Register Transfer language,
Register Transfer,
Bus and memory transfers, Arithmetic Micro operations, logic micro operations, shift
micro operations,
Arithmetic logic shift unit.
Basic Computer Organization and Design: Instruction codes, Computer Registers
Computer
instructions, Timing and Control, Instruction cycle, Memory Reference Instructions,
Input – Output and
Interrupt.

UNIT - II
Microprogrammed Control: Control memory, Address sequencing, micro program
example, design
of control unit.
Central Processing Unit: General Register Organization, Instruction Formats,
Addressing modes,
Data Transfer and Manipulation, Program Control.

UNIT - III
Data Representation: Data types, Complements, Fixed Point Representation,
Floating Point
Representation.
Computer Arithmetic: Addition and subtraction, multiplication Algorithms,
Division Algorithms,
Floating – point Arithmetic operations. Decimal Arithmetic unit, Decimal Arithmetic
operations.

UNIT - IV
Input-Output Organization: Input-Output Interface, Asynchronous data transfer,
Modes of Transfer,
Priority Interrupt Direct memory Access.
Memory Organization: Memory Hierarchy, Main Memory, Auxiliary memory,
Associate Memory,
Cache Memory.
.
UNIT - V
Reduced Instruction Set Computer: CISC Characteristics, RISC Characteristics.
Pipeline and Vector Processing: Parallel Processing, Pipelining, Arithmetic
Pipeline, Instruction
Pipeline, RISC Pipeline, Vector Processing, Array Processor.
Multi Processors: Characteristics of Multiprocessors, Interconnection Structures,
Interprocessor
arbitration, Interprocessor communication and synchronization, Cache Coherence.

TEXT BOOK:
1. Computer System Architecture – M. Moris Mano, Third Edition, Pearson/PHI.

REFERENCES:
1. Computer Organization – Car Hamacher, Zvonks Vranesic, Safea Zaky, Vth
Edition, McGraw
Hill.
2. Computer Organization and Architecture – William Stallings Sixth Edition,
Pearson/PHI.
3. Structured Computer Organization – Andrew S. Tanenbaum, 4th Edition,
PHI/Pearson
10. COURSE OBJECTIVES

1) The purpose of the course is to introduce principles of computer organization and


the basic architectural concepts.

2)It begins with basic organization, design, and programming of a simple digital
computer and introduces simple register transfer language to specify various
computer operations.

3) Topics include computer arithmetic, instruction set design, microprogrammed


control unit,pipelining and vector processing, memory organization and I/O systems,
and multiprocessors
11. COURSE COUTCOMES

C204.1 Understand the basics of instructions sets and their impact on processor design.

C204.2 Demonstrate an understanding of the design of the functional units of a digital computer
system
C204.3 Evaluate cost performance and design trade-offs in designing and constructing a computer
processor including memory
C204.4 Design a pipeline for consistent execution of instructions with minimum hazards.

C204.5 Recognize and manipulate representations of numbers stored in digital computers


12. LECTURE PLAN

Session Topic Hours Teaching


No Mode
UNIT – I
Digital Computers, Register Transfer Language and Micro operations, Basic Computer
Organization and Design,
Digital Computers:
1 Introduction 1 Black
Board/PPT
2 Block diagram of Digital Computer 1 Black
Board/PPT
3 Definition of Computer Organization, Computer Design and 1 Black
Computer Architecture Board/PPT
4 Bus Structures ,Software 1 Black
Board/PPT
Register Transfer Language and Micro operations:
5 Register Transfer language, Register Transfer 1 Black
Board/PPT
6 Bus and memory transfers 1 Black
Board/PPT
7 Arithmetic Micro operations 1 Black
Board/PPT
8 logic micro operations 1 Black
Board/PPT
9 shift micro operations 1 Black
Board/PPT
10 Arithmetic logic shift unit 1 Black
Board/PPT
Basic Computer Organization and Design:
11 Instruction codes 1 Black
Board/PPT
12 Computer Registers 1 Black
Board/PPT
13 Computer instructions 1 Black
Board/PPT
14 Timing and Control, Instruction cycle 1 Black
Board/PPT
15 Memory Reference Instructions 1 Black
Board/PPT
16 Input – Output and Interrupt 1 Black
Board/PPT
ASSIGNMENT on UNIT – I Mode: Offline/Online
TOTAL HOURS FOR UNIT – I 16

Session Topic Hours Teaching


No Mode
UNIT – II
Micro Programmed Control , Central Processing Unit
Micro Programmed Control:
1 Control memory 1 Black
Board/PPT
2 Address sequencing 1 Black
Board/PPT
3 micro program example 1 Black
Board/PPT
4 Symbolic Microinstructions 1 Black
Board/PPT
5 design of control unit 1 Black
Board/PPT
6 Microprogram Sequencer 1 Black
Board/PPT
Central Processing Unit:
7 General Register Organization 1 Black
Board/PPT
8 Instruction Formats 1 Black
Board/PPT
9 Addressing modes 1 Black
Board/PPT
10 Data Transfer and Manipulation 1 Black
Board/PPT
11 Program Control 1 Black
Board/PPT
ASSIGNMENT on UNIT – II Mode: Mode:
TOTAL HOURS FOR UNIT – II 11

Session Topic Hours Teaching


No Mode
UNIT – III
Data Representation, Computer Arithmetic
Data Representation:
1 Data types: Number systems 1 Black
Board/PPT
2 Number systems, complements 1 Black
Board/PPT
3 Fixed Point Representation 1 Black
Board/PPT
4 Floating Point Representation. 1 Black
Board/PPT
Computer Arithmetic:
5 Addition and subtraction with signed magnitude numbers 1 Black
Board/PPT
6 Addition and subtraction with signed 2’s complement numbers 1 Black
Board/PPT
7 Multiplication algorithms 1 Black
Board/PPT
8 Division algorithms 1 Black
Board/PPT
9 Floating point Arithmetic operations 1 Black
Board/PPT
10 Decimal Arithmetic unit 1 Black
Board/PPT
11 Decimal Arithmetic operations 1 Black
Board/PPT
ASSIGNMENT on UNIT – III Mode: Offline / Online
TOTAL HOURS FOR UNIT – III 11

Session Topic Hours Teaching


No Mode
UNIT – IV
Computer Arithmetic, Input-Output Organization
Input-Output Organization:
1 Peripheral Devices, Input-Output Interface 1 Black
Board/PPT
2 Asynchronous data transfer 1 Black
Board/PPT
3 Asynchronous data transfer 1 Black
Board/PPT
4 Modes of Transfer 1 Black
Board/PPT
5 Priority Interrupt 1 Black
Board/PPT
6 Direct memory Access 1 Black
Board/PPT
Memory Organization:
7 Memory Hierarchy 1 Black
Board/PPT
8 Main Memory: RAM and ROM chips 1 Black
Board/PPT
9 Memory Address Map, Auxiliary memory 1 Black
Board/PPT
10 Associate Memory 1 Black
Board/PPT
11 Cache Memory-Mapping Techniques, writing into cache 1 Black
Board/PPT
ASSIGNMENT on UNIT – IV Mode: Offline / Online
TOTAL HOURS FOR UNIT – IV 11
Session Topic Hours Teaching
No Mode
UNIT – V
Memory Organization, Pipeline and Vector Processing, Multi Processors

Pipeline and Vector Processing:

1 RISC and CISC 1 Black


Board/PPT
2 Parallel Processing, Pipelining 1 Black
Board/PPT
3 Arithmetic Pipeline 1 Black
Board/PPT
4 Instruction Pipeline 1 Black
Board/PPT
5 RISC PIPELINE 1 Black
Board/PPT
6 Vector Processing, Array Processors 1 Black
Board/PPT
Multi Processors:

7 Characteristics of Multiprocessors, 1 Black


Board/PPT
8 Interconnection Structures 1 Black
Board/PPT
9 Inter processor arbitration 1 Black
Board/PPT
10 Inter processor communication, and synchronization 1 Black
Board/PPT
11 Cache coherence 1 Black
Board/PPT

TOTAL HOURS FOR UNIT – V 11

GRAND TOTAL NUMBER OF HOURS 60


13. COA QUESTION BANK

Descriptive Questions

UNIT – I

Q.NO Description of Question Marks Course Program BTL


outcome Outcome
(CO) (PO)

Define Computer Organization and Computer CO1 PO1 L1


a 2
Architecture

Differentiate between Von Neumann Architecture and CO1 PO1 L4


1 b 3
Harvard Architecture

Explain the functional units of digital computer with CO1 PO1 L2


c 10
block diagram

2 CO1 PO1 L2

a Explain RTL and its control function. 2

Define Micro operations? List out the types of Micro CO1 PO1 L1
b 3
operations?

c Design a common bus system for 4 registers of 4 bits 5 CO1 PO3 L3


using Multiplexers
Design a common bus system for 4 registers of 1 bit CO1 PO3 L3
d 5
each using three state buffers

a What is Full Adder 2 CO1 PO1 L1

b Describe the Arithmetic Micro operations 3 CO1 PO1 L2


3
c Explain the 4 bit Arithmetic Circuit 5 CO1 PO1 L2

d Explain the 4bit binary adder- subtractor 5 CO1 PO1 L2

a Define Instruction code [ 2 CO1 PO1 L1

A digital computer has a common bus system for 16 CO1 PO3 L1


registers of 32bit each. The bus constructed with
multiplexers.

b i) How many multiplexer are there in the bus?? 3


4 ii)What size of Multiplexer are needed?

iii) How many selection inputs are there in each


multiplexer?

What are the Logical Micro operations and Explain the CO1 PO1 L3
c 5
applications of Logical Micro operations

d Describe shift Micro operations 5 CO1 PO1 L2

a List out the Basic Computer Registers 2 CO1 PO1 L1

Define Direct addressing mode and Indirect addressing CO1 PO1 L1


b 3
5 mode

Explain the different types of basic computer CO1 PO3 L2


c 10
instructions with their formats

6 a What is interrupt cycle 2 CO1 PO1 L2

b Describe the Register Reference Instructions 3 CO1 PO1 L2

c Describe the Memory Reference instructions 5 CO1 PO1 L2

d What is instruction cycle and explain the basic 5 CO1 PO1 L1


computer instruction cycle

UNIT-2
QNO Description of Question Marks Course Progra BTL
outcome m
(CO) Outcom
e(PO)

What is a pipeline register in micro programmed control CO2 PO1 L1


a 2
unit

b Discuss about control memory and its organization 3 CO2 PO1 L2


1
Differentiate between hardwired control unit and CO2 PO2 L4
Microprogrammed control unit. Hardwired control unit is
c 10
faster than micro programmed control unit. Justify this
statement

CO2 PO1 L2

Discuss about mapping process in microprogrammed


a 2
control unit

2
b Explain symbolic microinstruction format with example 3 CO2 PO1 L2

With the help of a block diagram , explain how do we select CO2 PO2 L2
c the address of control memory 10

3 a Why do we need subroutine register in a control unit?[ 2 CO2 PO2 L1

Define the following: CO2 PO1 L1

b i)Microoperation ii)Microinstruction iii) 3


Microprogram iv)Control Address Register

Explain the decoding of microoperation fields in control CO2 PO3 L2


c 5
unit?[

d Show the general block diagram of a micro program 5 CO2 PO3 L2


sequencer and also explain the inputs and outputs along
with their functioning

a What is stack pointer 2 CO2 PO1 L1

b Explain about data transfer instructions 3 CO2 PO1 L2


4
What is an addressing mode? Explain various addressing CO2 PO1 L2
c 10
modes with examples

Write the generic instruction types present in a computer CO2 PO1 L1


a 2
system

b Explain about shift instructions 3 CO2 PO1 L2


5
c Explain the General Register Organization 5 CO2 PO1 L2

What is an interrupt? What are the uses of interrupts? CO2 PO1 L1


d 5
Explain about the different type of interrupts?.

Give an example each of Zero-address, One-address, two- CO2 PO2 L1


a 2
address and three-address instruction

b Explain about Logical and Bit Manipulation Instructions 3 CO2 PO1 L2


6 c Explain about Program Control Instructions 5 CO2 PO1 L2

Evaluate the following arithmetic statement using zero, one, CO2 PO3 L2
d two and three address instructions. Use the conventional 5
symbols and instructions. X = (A+B) * (C+D).

UNIT-3
QN Description of Question Marks Course Program BTL
O outcome Outcome
(CO) (PO)

a Solve for X in the equation (19.125)10 =(X)8 2 CO3 PO1 L3

b Using 2’s complement perform (42)10 –( 68)10 3 CO3 PO2 L3


1
Explain about sign magnitude and 2’s complement CO3 PO1 L2
c approaches for representing the fixed point numbers. Why 5
2’s complement is preferable.
What is the use of complements? Perform subtraction using CO3 PO1 L1
d 5
7's complement for the given Base-7 numbers (565)-(666).

CO3 PO1 L3

a Using 10’s complement subtract 72532-3250 2

Give the 2's complement notation for the following signed CO3 PO1 L3
2 b decimal numbers 3
for 8 bit word i.) +1 ii) +127 iii) -1 iv) -64.

Solve for x CO3 PO3 L3

c i) (367)8=(x)2 ii) (323)4 = ( )5 10

iii) (B9F. AE)16 = (x)8 iv) (16)10 = (100) x

Represent the decimal number 46.5 as a floating point CO3 PO1 L3


a 2
number with 16 bit mantissa and 8 bit exponent

b Convert the following (527)10=(?)Gray=(?)BCD=(?)XS-3 3 CO3 PO1 L3

Explain 2's complement method of representing numbers. CO3 PO1 L2


3 c When can you say that an overflow has occurred when 5
adding or subtracting two fixed point numbers.

Represent 32.75 and 18.125 in single precision IEEE 754 5 CO3 PO1 L2
Representation
d ____

CO3

4 Show the hardware to be used for Multiplication with signed CO3 PO3 L2
a 2
magnitude numbers

b Define Divide overflow? 3 CO3 PO1 L1


Explain in detail with neat sketch Booth Multiplication CO3 PO3 L2
c 10
Algorithm with example

Perform the operation (-9)+(-6)= -15 with binary numbers in CO3 PO1 L3
a signed 2’s complement representation using only five bits to 2
represent each number (including the sign).

Give Register configuration for floating point arithmetic CO3 PO3 L2


5 b 3
operations

Explain in detail addition and subtraction with signed CO3 PO3 L2


c 5
magnitude numbers

d Explain different methods of decimal addition 5 CO3 PO1 L2

a What is an array multiplier and give example 2 CO3 PO1 L1

b Define overflow and underflow 3 CO3 PO1 L1


6 c Explain Division Algorithms 5 CO3 PO1 L2

Explain the floating point additions and subtractions CO3 PO1 L2


d 5
operations With a flow chart

UNIT-4

QNO Description of Question Marks Course Program BTL


outcome Outcome
(CO) (PO)

a What is an I/O interface 2 CO4 PO1 L1

b Differentiate isolated I/O and memory mapped I/O 3 CO4 PO1 L4


1
Explain different types of modes of transfer (or) I/O CO4 PO1 L2
c 10
communication techniques

2 a 2 CO4 PO2 L1

What is the basic advantage of using interrupt-initiated


data transfer over transfer under program control without
an interrupt?

b Explain about Source-initiated transfer using handshaking 3 CO4 PO1 L2

What is Direct Memory Access? Explain the working of CO4 PO1 L1


c 10
DMA. What are the different kinds of DMA transfers?[

a Differentiate vectored and non vectored interrupt 2 CO4 PO1 L4

b Explain daisy-chain priority interrupt 3 CO4 PO1 L2


3
c Explain parallel priority interrupt? 5 CO4 PO1 L2

d Explain Asynchronous serial transfer 5 CO4 PO1 L2

How many characters per second can be transmitted over a CO4 PO2 L3
a 2
1200 baud line in Synchronous serial transmission?[

Give a neat sketch that illustrate the components in a CO4 PO3 L4


4 b 3
typical memory Hierarchy

Explain the different types mapping techniques are used in CO4 PO1 L2
c 10
usage of the cache memory

a Define hit ratio and miss ratio 2 CO4 PO1 L1

b Differentiate between SRAM and DRAM 3 CO4 PO1 L4


5 c Explain about types of ROM 5 CO4 PO1 L2

What is memory address map table ? Explain with CO4 PO1 L1


d 5
example?

6 a What is an Auxilary Memory 2 CO4 PO1 L1

b Differentiate write through and write back 3 CO4 PO1 L4

c How many 128 × 8 RAM chips are needed to provide a 5 CO4 PO2 L2
memory capacity of 2048 bytes? How many lines of
address bus must be used to access 2048 bytes of memory?
How many of these lines will be common to all chips?

With the help of a neat diagram explain the match logic for CO4 PO3 L2
d 5
one word of Associative Memory

UNIT-5
QNO Description of Question Marks Course Program BTL
outcom Outcome
e (CO) (PO)

a What is space time diagram and give example 2 CO5 PO1 L1

b Differentiate between RISC and CISC 3 CO5 PO2 L4


1
c Explain array processor in detail 10 CO5 PO1 L2

d What is pipeline and explain with example CO5 PO1 L1

CO5 PO1 L1

a What are the pipeline conflicts 2

b What is delayed branch? Explain with example 3 CO5 PO1 L2

c Explain RISC pipeline or three segment instruction pipeline 10 CO5 PO1 L2

a What are the applications of vector processing 2 CO5 PO1 L1

b Define memory interleaving 3 CO5 PO1 L1


3 c Explain arithmetic pipeline with example 5 CO5 PO1 L2

Explain the various hardware techniques to minimize the CO5 PO2 L2


d 5
performance degradation caused by instruction branching

4 a Draw the system bus structure for multiprocessors 2 CO5 PO1 L2

Differentiate between tightly coupled multiprocessor and CO5 PO2 L4


b 3
loosely coupled multiprocessor

c i)Explain the functioning of omega switching network with 10 CO5 PO3 L2


a neat sketch.

ii) In 8 X 8 omega switching network how many stages


are there and in each stage how many Switches are there.

iii) How many stages and how many Switches in each stage
are needed in a n x n omega switching network.

a Explain the cache incoherence 2 CO5 PO1 L2

5 b Explain multiport memory organization with a neat sketch 3 CO5 PO1 L2

c Explain static arbitration and dynamic arbitration algorithms 5 CO5 PO1 L2

a Define critical section 2 CO5 PO1 L1

How many switch points are there in a crossbar switch CO5 PO1 L2
b 3
network that connects p processors to m memory modules
6 What are the various forms available for establishing an CO5 PO1 L2
c 5
interconnection network in a multi processor system?

What is cache coherence? Explain different solutions to the CO5 PO1 L2


d 5
cache coherence problem

Objective Questions

UNIT – I

Multiple Choice Questions:

1.Computer Organization is concerned with


[ ]
a. The way hardware components operate and connected together to form
Computer system.

b. The determination of what hardware should be used and how the parts
be connected.

c. The structure and behavior of the computer as seen by the user.


d. Design of electronic components of computer.

2. The part of the hardware of computer that controls the transfer of information
between
computer and the outside word is
[ ]

a)CPU b)Memory c)IOP d)Microprocessor

3. In direct addressing mode address part of instruction specifies


[ ]

a)Address of next instruction b)Address of register


c)Address of operand in memory d)Operand itself

4. In indirect addressing mode address part of instruction specifies


[ ]

a)Address of next instruction b)Address of current instruction


c)Address of operand d)Address of memory location containing address of
operand
5. The memory reference instruction that denotes operation PC 🡨AR is
[ ]

a) AND b) BSA c) BUN d)STA

6. The transfer of information from a memory word to the outside environment is


called a ________ operation.
[ ]
a) Read b) write c) both d) none

7. To design a common bus system for 4 register of 4-bits each, by using tristate
buffers and a decoder, what is the size of the decoder?
[ ]
a) 2 to 4 Decoder b) 3 to 8 Decoder c) 4 to 16 Decoder d)5 to 32 decoder

8. If the address field of an instruction specifies the effective address, then the
instruction is
[ ]
a) Immediate Instruction b) Direct Instruction c) Indirect Instruction d) None

9 There are ___________ different logical operations that can be performed with 2
binary variables
[ ]
a) 2 b) 4 c) 8 d) 16.
10. In the Binary Adder/subtractor if M=0 the circuit is __________
[ ]
a) adder b) subtractor c) both adder & subtractor d) exclusive Binary Operation.

11. The _________ operation is similar to the selective clear operation except that
the bits of A are cleared only where there are corresponding 0's in B.
[ ]
a) Selective – set b) Selective – complement c) Mask d) Insert .

Fill in the blanks:

12. The type of shift used to shift the contents of a register which contains a signed
binary number is called ___________
13. If the memory size is 4096*16, then ___ address lines are required to address any
memory location
14. The ______________ operation sets to 1 bit in register A where there are
corresponding 1’s in register B.
15. Description of SPA instruction ______________________________

16. An _____________ is s a group of bits that instruct the computer to perform a


specific operation.
17. A _______________ is a fast electronic calculating machine that accepts
digitized input information, processes it according to a list of internally stored
instructions and the resulting output information.
18. The ____________ holds the address of the next instruction to be read from
memory after the current instruction is executed.

19. An elementary operation performed on the information stored in one or more


registers is referred as ___________
20. A common bus for eight registers of 16 bits each requires _______ number of
multiplexers.
21. An arithmetic shift right ________ the signed binary number by 2. An
arithmetic shift left _______ a signed binary number by 2.

22.__________ holds the address of the memory location to be accessed


23. ______________ holds the instruction code that is currently being executed.

UNIT – 2

1. The control logic is implemented with gates, flip-flops, decoders, and other digital
circuits. [ ]

a) Hardwired control b) Microprogrammed c)Control logic d)None


2. If the control signals are generated using hardware with conventional logic design
techniques then the control unit is said to be
[ ]

a)Micro programmed b)Hardwired


c)Nano programmed d)Programmed

3. The register used to store return address of sub routine is [ ]


a)Control address Register (CAR) b)Sub routine register (SBR)
c)Instruction register (IR) d)Program counter (PC)

4. Micro instructions are stored in [ ]

a)Main memory b)Secondary memory c)Control memory d)Virtual memory

5. The memory reference instruction that denotes operation AC 🡨M[AR] is [ ]

a)AND b)BSA c)BUN d)LDA


6. RPN is also called as
[ ]

a) Infix Notation b) Polish Notation c) Prefix Notation d) Postfix Notation

7 _________ refer to the transfer of program control from a currently running


program to another service program as result of external or internal generated
request. [ ]

a)Program Interrupt b) Internal Interrupt c) External Interrupt d) Software


Interrupt

8. Postfix notation of (A+B)*C is


[ ]
a. AB+*C b. AB*+C c . ABC+* d. AB+C*

9 Stack follows the __________ operation


[ ]
a) L I F O b) F I F O c) S J F d) none

10 Which of the following is shift instruction


[ ]
a) RORC b) CALL C) SKP d) SETC

Fill in the blanks:

11. The next address generator is also called as ______________________

12 In the Micro instruction code Format the condition field consists of two bits
which are encoded to specify_______ status bit conditions
13 A _____________ requires changes in the wiring among the various components
if the design has to be modified (or) changed.
14. The transformation from the instruction code bits to an address in control
memory where the routine located is referred as __________
15. In Micro programmed organization, the control information is stored in
_______________
16. A control unit whose binary control variables are stored in memory is called
_____________ control unit
17 The register that holds the address for the stack is called __________
18 Internal interrupts are also called as ___________
19 The implied operand of an operation in a single accumulator organization is
_____________
20.In a memory stack, after the pop operation, the stack pointer will be
____________

UNIT – 3

1.Binary coded decimal number for 99 is ________


[ ]
a) 1100011 b) 00110101 c) 10011001 d) 00100000.

2. In the Hardware for Signed –Magnitute addition and subtraction two magnitudes
are subtracted if the sign are different for an ________ Operation (or) identical for an
________ operation. [ ]

a) add , subtract b) add , Multiply c) subtract , add d) Multiply , add.


3. Convert the following binary number into decimal 101110
[ ]
a) 55 b) 45 c)46 d)56
4. Obtain the 10’s complement of the following 6-bit decimal number 100000
[ ]
a. 999999 b. 899999 c. 900000 d. 100000

5. What is the description about following decimal arithmetic microoperation? Q L


QL+1 [ ]
a.Increment QL register b. Increment BCD number in QL

c. Increment decimal number in QL d. All the above


6. Convert the hexadecimal number F3A7C2 to binary
[ ]
a.111101101101100010101001 b. 111111000101101101011110

c. 111100111010011111000010 d. 111110011001100000010010
7. Perform the subtraction with the following unsigned decimal number by
[ ]

taking the 10’s complement of the subtrahend 1200-250.

a. 450 b. 750 c. 749 d. 449

8. N-bit sign magnitude numbers can represent quantities from


[ ]
a) –(2(n-1)-1) to +(2(n-1)) b) –(2(n-1)-1) to +(2(n-1)-1) c) –(2n-1) to +(2n-1) d) –(2n-1)
to +2n
9.What is the 8-bit 2’s complement of -12
[ ]

a. 1111 0100 b. 1000 1100 c. 0000 0100 d. 0000 0011

10. If (123)5=(x3)y, then the number of possible values of x is


[ ]
a. 4 b. 1 c. 3 d. 2

Fill in the blanks:

11. A floating- point number is said to be _____________if the most- significant


digit of the mantissa is nonzero.
12The Divisor is shifted once to the right and subtracted from the dividend. That
difference is called a ______________.
13The r’s complement of an n-digit number N in base r is defined as
_____________
14. The decimal equivalent of the binary number 101.101 is _____________
15. The 9’s complement of BCD (1001) is _____________

16. In BCD addition, when the binary sum is greater than 1001, then addition of
_______ converts the binary sum to correct BCD representation

17 An n-bit 2’s complement number can represent values _____________

18. In a Array multiplier circuit with ‘j’ multiplier bits and ‘k’ multiplicand bits, the
number of
AND gates required are ___________

19. A divide overflow condition occurs, if the high order half bits of the dividend is
__________________
20. ___________ algorithm specifies a procedure for multiplying two binary integers
in Signed 2’s complement.

UNIT-4
1. Machines whose instructions generate 32-bit address can utilize a memory that
contains up to _______ memory locations
[ ]

A. 28 B. 216 C. 232 D. 248


2. The CPU has distinct i/p and o/p instructions and each of these instructions is
associated with the address of an interface register.
[ ]
A. Memory Mapped I/O B. I/O Port C. Isolated I/O D. I/O Command
3. Backup storage is called as
[ ]
A. Cache Memory B. Main Memory C. Auxiliary Memory D. Virtual Memory
4. Baud rate is data transfer in
[ ]
A.bits per second B. bytes per second C. words per second D. all the above
5. During a _________ operation, the sense/read circuits, the information stored in
the cells selected by a word line and transmit this information to the o/p data lines
[ ]
A. Write B. Read C. Read/Write D. Write & Read/Write
6. The interface transfer s data into and out of the memory unit through the memory
bus. [ ]

A. Programmed-I/O B. Interrupted-Initiated I/O C. Direct


Memory Access D. all the above
7In the ____________ only the cache is updated and the location is marked so that it
can be copied later into main memory.
[ ]

A. Write through policy B. Cache Coherence C. Write-


back policy D. Cache Incoherence
8. Many instructions in localized areas of the program are executed repeatedly during
some time period, and the remainder of the program is accessed relatively
infrequently . [ ]
A. Locality reference B. spatial C. temporal D. cache
9. Which of the following is volatile?
[ ]

A) Bubble memory B) RAM C) ROM D) Magneticdisk

10. In a non-vectored interrupt


[ ]

A) The branch address is assigned to a fixed location in memory


B)The interrupting source supplies the branch information to the processor through
an interrupt vector
C)The branch address is obtained from a register in the process
D)Both The interrupting source supplies the branch information to the processor
through an interrupt vector & The branch address is obtained from a register in the
process

Fill in the blanks:

11 In an _____________ different sets of addresses are assigned to different memory


locations.
12. The bus grant signal is replaced by a set of lines called poll lines which are
connected to all units is called as ____________
13 Expand UART: _______________________
14 The number of hits stated as a fraction of all attempted accesses is called
____________
15. In the _____________ policy, both cache and main memory are updated with
every write operation.
16Input-Output interface provides a method for transferring information between
_______________
17The DMA controller to transfer one data word at a time, after which it must return
control of the buses to the cpu, this technique is called as ____________
18. Associative memory is called ______________
19 A serial transmission technique which employs special bits to mark the ends of
character is called _______________
20 If the branch address of the interrupt routine is supplied by the source it is called
____________ interrupt.

UNIT-5
1. The speed up of a pipeline processing over an equivalent non-pipeline processing
is defined by the ratio S =_________
[ ]
A. ntn /(k+n-1)tp B. ntp/(k+n-1)tn C.ntn /(k+n+1)tp D.ntp/(k-n-1)tn

2 The ______ organization consists of a number of cross points that are placed at
intersections between processors buses and memory module paths.
[ ]
A. Multiport memory B. Hypercube system C. Crossbar
Switch D. Time –shared common bus
3. Application of Vector Processing is
[ ]
A. Library System B. Medical Diagnosis C. Seismic Wave Analysis D. Space
Research

4 An __________ is an auxiliary processor attached to a general purpose computer .


[ ]
A. SIMD array Processor B. Attached array Processor C.
Vector Processor D. All the above
5. An ______________is a processor that as single instruction multiple data
organization [ ]
A. SIMD array Processor B. Attached array Processor C. Vector Processor D. All the
Above
6. To compute n-tasks using a k-segments pipeline requires ______ clock cycles
[ ]
A. k-(n+1) B. k-(n-1) C. k+ (n-1) D. k+ (n+1)
7. The _________ algorithm allocates a fixed –length time slice of bus time that is
offered sequentially to each processor.
[ ]

A. FIFO B. LRU C. Time slice D. Polling


8. _________ arise from branch and other instructions that change the value of pc
[ ]

A. Data Dependency B. Resource conflict C. Branch difficulties D. NONE


9________________ caused by access to memory by two segments at the same time
[ ]

A. Data dependency B. Resource Conflict C. Branch


difficulties D. Delay load
10The ______algorithm gives the highest priority to the requesting device that has
not used the bus for the longest interval.
[ ]
A. Round - robin B.FIFO C. LRU D. rotating daisy-chain

Fill in the blanks:

11 ____________ is a technique of decomposing a sequential process into sub


operations, with each sub process being executed in a special dedicated segment that
operates concurrently with all other segments.
12 An ________________ operates on a stream of instructions by overlapping the
fetch, decode and execute phases of the instruction cycle.
13A ___________________ is a program sequence that, once begun, must
complete execution before another processor access the same shared resource.
14Expand SIMD _____________________________
15. Multi processors and Multi computer system come into ____________ category
16 A hyper cube with 2-dimensions contain _________ number of processors.
17 An 8x8 omega switching network contains _________ number of switches
18 The number of stages in nxn omega switching network is _________
19. The bus controller that monitors the cache coherence problem is referred as
_____________

20 Each processor element in a _______________ system has its own private local
memory

14.UNIT WISE LEARNING OBJECTIVES


UNIT-I

Digital Computers,Register Transfer Language and Micro operations


Learning Objectives:

After completion of this unit the student would be able to:

Able to Understand what is computer organization,computer design and computer



architecture.
Identify the major parts in digital computer

RTL and different types of micro operations

Able to understand instruction codes and computer registers

Able to understand different types of instructions.

Able to Understand the instruction cycle

UNIT-II

Microprogrammed Control,Central Processing Unit

Learning Objectives:

After completion of this unit the student would be able to:

● Understanding the design of control unit

Understanding the control memory


Understanding the instruction formats


Understanding the micro programs


Understanding the register organization



Understanding the addressing modes

Understanding the types of instructions


UNIT-III
Data Representation,Computer Arithmetic

Learning Objectives:

After completion of this unit the student would be able to:

Understanding data types



Learning about complements

Learning fixed point and floating point representation

Understanding addition,subtraction,multiplication and division algorithms

Understanding floating – point and arithmetic operations

UNIT-IV

Input-Output Organization,Memory Organization


Learning Objectives:

After completion of this unit the student would be able to:

Understanding input output interface



Learning asynchronous data transfer

Learning modes of transfer

Learning priority interrupt

Understanding Direct Memory Access

Understanding memory hierarchy

Understanding types of memories

Understanding associate memory

Learning cache mappings

UNIT-V
RISC,Pipeline and Vector Processing,Multi Processors

Learning Objectives:

After completion of this unit the student would be able to:

Understanding RISC and CISC characterestics.



Understanding parallel processing

Understanding pipelining and different types of pipelining

Understanding characterestics of multi processors,interconnection structures and

cache coherence
Understanding interprocessor communication and synchronization

20. PREVIOUS YEAR UNIVERSITY QUESTION PAPERS

Code No: 153AG R18


JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD

B.Tech II Year I Semester Examinations, October – 2020


COMPUTER ORGANIZATION AND ARCHITECTURE
(Computer Science and Engineering)

Time: 2 hours Max. Marks: 75

Answer any five questions All questions carry equal marks

---

1. a) Draw the bus system for four registers and explain.


b) An 8-bit register contains the binary value 10011100. What is the register
value after an Arithmetic Shift Right? Starting from the initial number 10011100,
determine the register value after an arithmetic Shift Left, and state whether there
is an overflow. [7+8]

2. Draw block diagram of a control memory and the associated hardware


needed for selecting the next micro instruction address. [15]

3. Perform the arithmetic operation (+42)+(-13) and (-42)-(-13) in binary


using signed 2’s complement representation for negative numbers. [15]

4. a) Differentiate between Isolated I/O and memory-mapped I/O.


b) Explain programmed-I/O in detail. [8+7]

5. a) Write the major characteristics of RISC processors.


b) Draw a space-time diagram for a four-segment pipeline showing the time
it takes to process six tasks and explain. [7+8]

6. a) Draw the flowchart for instruction cycle and explain.


b) Explain the following instructions: BUN, ISZ, BSA, LDA, STA. [7+8]

7. Explain various Data Manipulation instructions with examples. [15]

8. With an example, explain Booth Multiplication algorithm. [15]

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