EC319 VLSI Systems

Module-2: The Wire and Interconnection

Interconnect Parameters, Electrical Wire Models, Capacitive Parasitics, Resistive Parasitics,
Inductive Parasitics, Advanced Interconnect Techniques, I/O structures Design: VDD and VSS
pads, output & input pads, tri-state and bidirectional pads, application of Schmitt trigger in
I/O pads, MOSIS I/O pads, Mixed-Voltage I/O pad.
Introduction
 The parasitics effects introduced by wires dominate relevant metrics of digital
integrated circuits (speed, energy-consumption and reliability).
 Wiring of integrated circuits form a complex geometry that introduces capacitive,
resistive, and inductive parasitics. All three have multiple effects on the circuit
behavior.
1. Increase in propagation delay (drop in performance)
2. Impact on energy dissipation and power distribution
3. Introduction of extra noise sources (affects the reliability of the circuit)
 A designer may include all these parasitic effects in analysis and designoptimization
process.
 It is important that the designer has a clear insight in the parasitic wiring effects, their
relative importance, and their models.
Interconnect Parameters (Capacitance, Resistance and Inductance)
Capacitance
 The interconnect structure of integrated circuit is three-dimensional.
 The capacitance of a wire is a function of its shape, its environment, its distance to the
substrate and the distance to surrounding wires.
 A designer uses advanced extraction tool to get precise values of the interconnect
capacitances of a completed layout.
 Semiconductor manufacturers provide empirical data for various capacitance
contributions.
 Simple first-order model may provide a basic understanding of the nature of
interconnect capacitance and its parameters. Consider a simple rectangular wire
placed above the semiconductor substrate as shown in Figure.

Fig: Parallel-plate capacitance model of interconnect wire

 If the width of the wire is substantially larger than the thickness of the insulating
material, it may be assumed that the electrical-field lines are orthogonal to the
capacitor plates and its capacitance can be modeled by the parallel-plate capacitor
 model (area capacitance). Under these circumstances, the total capacitance of the
wire can be approximated as

Where W and L are width and length of the wire, and tdi and ԑdi representthe thickness
of the dielectric layer and its permittivity.
 SiO2 is the dielectric material of choice in integrated circuits. (ԑ = ԑrԑ0; ԑ0 = 8.854 x 10-12
F/m is the permittivity of free space, and ԑr the relative permittivity of the insulating
material).

Table: Relative permittivity of typical dielectric materials

 To minimize the resistance of the wires, it is desirable to keep the cross-section of the
wire (WxH) as large as possible.
 Small values of W lead to denser wiring and less area overhead. There is a steady
reduction in the W/H-ratio (below unity in advanced processes).
 Under these circumstances, the parallel-plate model becomes inaccurate.The
capacitance between the side-walls of the wires and the substrate, called thefringing
capacitance, can no longer be ignored and contributes to the overall capacitance.This
effect is illustrated in Figure

Fig: The fringing-field capacitance. The model decomposes the capacitance into two contributions: a parallel-
plate capacitance, and a fringing capacitance, modelled by a cylindrical wire with a diameter equal to the
thickness of the wire
 Simplified model approximates the capacitance as the sum of two components: a
parallel-plate capacitance determined by the orthogonal field between a wire of width
w and the ground plane, in parallel with the fringing capacitance modeled by a
 cylindrical wire with a dimension equal to the interconnect thickness H. The resulting
approximation is simple and works well in practice.

With w=W-H/2, a good approximation for the width of the parallel-plate capacitor.

Fig: Capacitance of interconnect wire as a function of (W/tdi), including fringing-field effects. Two values of
H/tdiare considered. Silicon-dioxide with ԑr = 3.9 is used asdielectric. (tdi is the dielectric thickness)

 For larger values of (W/H) the total capacitance approaches the parallel-plate model.
 For (W/H) smaller than 1.5, the fringing component becomes the dominant
component. The fringing capacitance can increase the overall capacitance by a factor
of more than 10 for small line widths.
 Total capacitance levels off to a constant value of approximately 1 pF/cm for line
widths smaller than the insulator thickness. In other words, the capacitance is no
longer a function of the width.
 It is a good model for semiconductor interconnections when the number of
interconnect layers was restricted to 1 or 2.
 Today’s processes offer many layers of interconnect, which are packed quite densely.
This is illustrated in Figure below

Fig: Capacitive coupling between wires in interconnect hierarchy.

 Capacitance components of a wire embedded in an interconnect hierarchy are
identified. Each wire is not only coupled to the grounded substrate, but also to the
neighbouring wires on the same layer and on adjacent layers.
 This does not change the total capacitance connected to a given wire. The main
difference is that not all its capacitive components do terminate at the grounded
substrate, but that a large number of them connect to other wires, which have
 dynamically varying voltage levels. These floating capacitors form not only a source of
noise (crosstalk), but also can have a negative impact on the performance of the
circuit.
 Inter-wire capacitances become a dominant factor in multi-layer interconnect
structures. This effect is more outspoken for wires in the higher interconnect layers, as
these wires are farther away from the substrate. The increasing contribution of the
inter-wire capacitance to the total capacitance with decreasing feature sizes is best
illustrated by Figure 4.7. In this graph, which plots the capacitive components of a set
of parallel wires routed above a ground plane, it is assumed that dielectric and wire
thickness are held constant while scaling all other dimensions. When W becomes
smaller than 1.75 H, the inter-wire capacitance starts to dominate.

Fig: Interconnect capacitance as a function of design rules. It consists of a capacitance to ground and an
inter-wire capacitance
 Interconnect Capacitance Design Data

Table: Wire area and fringe capacitance values for typical 0.25 mm CMOS process. Thetable rows
represent the top plate of the capacitor, the columns the bottom plate. Thearea capacitances are
expressed in F/µm2, while the fringe capacitances (given in the shaded rows) are in F/µm.

Resistance
 The resistance of a wire is directly proportional to its length L and inversely
proportional to its cross-section A. The resistance R of a rectangular conductor can be
expressed as
 Where the constant ρ is the resistivity of the material (in W-m).
Since H is a constant for a given technology

is the sheet resistance having units ohm per square.

 Resistance of a square conductor is independent of its absolute size. To obtain the
resistance of a wire, simply multiply the sheet resistance by its ratio (L/W).
 The resistivity of somecommonly-used conductive materials are given below

 Aluminium is the interconnectmaterial often used in integrated circuits because of its

low cost and its compatibilitywith the standard integrated-circuit fabrication process. It
has alarge resistivity compared to Copper. Top-of-the-line processes are now
increasinglyusing Copper as the conductor of choice.
 Interconnect Resistance Design Data

Table: Sheet resistance values for a typical 0.25 mm CMOS process

 Advanced processes offer silicided polysilicon and diffusion layers. A silicide is a

compound material formed using silicon and a refractory metal. This creates a highly
conductive material that can withstand high-temperature process steps without
melting. The silicides are often used in a configuration called a polycide, which is a
simple layered combination of polysilicon and a silicide. A typical polycide consists of a
lower level of polysilicon with an upper coating of silicide and combines the best
properties of both materials—good adherence and coverage (from the poly) and high
conductance (from the silicide).
 A MOSFET fabricated with a polycide gate is shown in Figure
 Fig: A polycide-gate MOSFET

 The advantage of the silicided gate is a reduced gate resistance. Similarly, silicided
source and drainregions reduce the source and drain resistance of the device.
 Transitions between routing layers add extra resistance to a wire, called the
contactresistance. The preferred routing strategy is thus to keep signal wires on a
single layerwhenever possible and to avoid excess contacts or via’s.
 It is possible to reduce the contactresistance by making the contact holes larger.
 Current tends to concentratearound the perimeter in a larger contact hole. This effect,
called current crowding, puts apractical upper limit on the size of thecontact.
 The following contact resistances (for minimum-size contacts) are typical for a 0.25
mm process:
o 5-20 Ω for metal or polysilicon ton+, p+, and metal to polysilicon;
o 1-5 Ω for via’s (metal-to-metal contacts)
 At very high frequencies skin effect comes into play such that the resistance becomes
frequency-dependent. High-frequency currents tend to flow primarily on the surface
of a conductor with the current density falling off exponentially with depth into the
conductor.
 The skin depth(δ) is defined as the depth where the current falls off to a value of e-1 of
its nominal value, and is given by

withf the frequency of the signal and µ the permeability of the surrounding dielectric
(permeability of free space, or µ = 4πx10-7 H/m). For Aluminium at 1GHz, the skin
depth is equal to 2.6 µm.

Fig: The skin-effect reduces the flow of the currentto the surface of the wire.

 The effect can be approximated by assuming that the current flows uniformly in
anouter shell of the conductor with thickness δ for a rectangular wire.

 Assuming that the overall cross-section of the wire is now limited to approximately
2(W+H)δ, we obtain the following expression for the resistance (per unit length) athigh
frequencies (f > fs):

 The increased resistance at higher frequencies may cause an extra attenuation

andhence distortion of the signal being transmitted over the wire.
 To determine the on-set of the skin-effect, we can find the frequency fs where the skin
depth is equal to half the largest dimension (W or H) of the conductor. Below f s the
 whole wire is conducting current and the resistance is equal to low-frequency
resistance of the wire.

Fig: Skin-effect induced increase in resistance as a function of frequency and wire width. All simulations
were performed for a wire thickness of 0.7 µm
 Skin-effect is only an issue for wider wires. Since clocks tend to carry the highest-
frequency signals on a chip and also are fairly wide to limit resistance, the skin effect is
likely to have its first impact on these lines.
 This is a real concern for GHz-range design, as clocks determine the overall
performance of the chip (cycle time, instructions per second, etc.).
 Another major design concern is that the adoption of better conductors such as
Copper may move the on-set of skin-effects to lower frequencies.

Inductance
 Consequences of on-chip inductance include ringing and overshoot effects, reflections
of signals due to impedance mismatch, inductive coupling between lines, and
switching noise due to Ldi/dt voltage drops.
 The inductance of a section of a circuit can always be evaluated with its definition,
which states that a changing current passing through an inductor generates a voltage
drop ΔV

 It is possible to compute the inductance of a wire directly from its geometry and
itsenvironment. A simpler approach relies on the fact that the capacitance c and the
inductancel (per unit length) of a wire are related by the following expression
Cl=ԑµ
with ԑ and µ are the permittivity and permeability of the surrounding dielectric.
 Expression is valid only if the conductor is completely surrounded by a uniform
dielectric medium. This is most often not the case.
  When the wire is embedded in different dielectric materials, it is possible to adopt
“average” dielectric constants and Eq. Cl=ԑµ can be used to get an approximate value
of the inductance.
 The constant product of permeability and permittivity also defines the speed ѵ at
which an electromagnetic wave can propagate through the medium

 c0equals the speed of light (30 cm/nsec) in a vacuum.

Table: Dielectric constants and wave-propagation speeds for various materials used in electronic circuits.
The relative permeability mr of most dielectrics is approximately equal to 1.

 Inductance becomes an issue in integrated circuits for frequencies that are well above
1 GHz.

Electrical Wire Models

 Parasitic elements (capacitance, resistance, inductance) have an impact on the
electrical behaviour of the circuit and influence its delay, power dissipation, and
reliability.
 To study these effects requires the introduction of electrical models that estimate and
approximate the real behaviour of the wire as a function of its parameters.
 These models vary from simple to complex depending upon the effects that are being
studied and the required accuracy.

The Ideal Wire

 In schematics, wires occur as simple lines with no attached parameters or parasitics.
These wires have no impact on the electrical behaviour of the circuit.
 A voltage change at one end of the wire propagates immediately to its other ends.
 It may be assumed that the same voltage is present at every segment of the wire at
every point in time and that the whole wire is an equipotential region.
 While this ideal-wire model is simplistic, it has its value, especially in the early phases
of the design process when the designer wants to concentrate on the properties and
the behaviour of the transistors that are being connected.
 When studying small circuit components such as gates, the wires tend to be very short
and their parasitics ignorable.

The Lumped Model

 The circuit parasitics of a wire are distributed along its length.
  When only a single parasitic component is dominant, when the interactionbetween
the components is small, or when looking at only one aspect of the circuitbehaviour, it
is useful to lump the different fractions into a single circuit element.
 The advantage is that the effects of the parasitic can be described by an ordinary
differential equation. (Description of a distributed element requires partial differential
equations).
 As long as the resistive component of the wire is small and the switching frequencies
are in the low to medium range, it is meaningful to consider only the capacitive
component of the wire, and to lump the distributed capacitance into a single capacitor
as shown in Figure

Fig: Distributed versus lumped capacitance model of wire. C lumped = Lxcwire, with L the length of the
wire and cwire the capacitance per unit length. The driver is modeled as a voltage source and a source
resistanceRdriver.

The Lumped RC model

 On-chip metal wires of over a few mm length have a significant resistance. The
equipotential is no longer adequate and a resistive-capacitive model has to be
adopted.
 One approach lumps the total wire resistance of each wire segment into one single R
and similarly combines the global capacitance into a single capacitor C. It is inaccurate
for long interconnect wires. Long interconnect wires are adequately represented by a
distributed rc-model.
 The distributed rc-model is complex and no closed form solutions exist. The behaviour
of the distributed rc-line can be adequately modeled by a simple RC network. A
common practice in the study of the transient behaviour of complex transistor-wire
networks is to reduce the circuit to an RC network. Having a means to analyse such a
network effectively and to predict its first-order response would add a great asset to
the designers tool box.
 RC chain (or ladder) is shown in Figure . This network is a structure that is encountered
in digital circuits. It represents an approximate model of a resistive-capacitive wire.

Figure: RC chain

 The Elmore delay of this chain network can be derived

The Distributed rc Line
 L represents the total length of the wire, while r and c stand for the resistance and
capacitance per unit length. A schematic representation of the distributed rc line is
given in Figure

Fig: Distributed RC line wire-model and its schematic symbol

 The voltage at node i of this network can be determined by solving the following set of
partial differential equations:

 The correct behaviour of the distributed rc line is obtained by reducing ΔL

asymptoticallyto 0. Diffusion equation is given as

Where V is the voltage at a particular point in the wire, and x is the distance between
thispoint and the signal source.

The Transmission Line

 When the switching speeds of the circuits become sufficiently fast, and the quality of
the interconnect material become high enough so that the resistance of the wire is
kept within bounds, the inductance of the wire starts to dominate the delay behaviour,
and transmission line effects must be considered.
 This is more precisely the case when the rise and fall times of the signal become
comparable to the time of flight of the signal waveform across the line as determined
by the speed of light.
 With the advent of Copper interconnect and the high switching speeds enabled by the
deep-submicron technologies, transmission line effects are considered in the fastest
CMOS designs.
Transmission Line Model
 A distributed rlc model of a wire, known as the transmission line model, becomes the
most accurate approximation of the actual behaviour.
 The transmission line has the prime property that a signal propagates over the
interconnection medium as a wave.
  In the wave mode, a signal propagates by alternatively transferring energy from the
electric to the magnetic fields, or equivalently from the capacitive to the inductive
modes.

Figure:Lossy transmission line

 Consider the point x along the transmission line of Figure at time t. The followingset of
equations holds:

 Assuming that the leakage conductance g equals 0, which is true for most insulating
materials and eliminating the current i yields the wave propagation equation

 Where r, c, and l are the resistance, capacitance, and inductance per unit length
respectively.

Advanced Interconnect Techniques

Polysilicon Refractory metal interconnect
 Polysilicon resistance can be reduced by combining it with a refractory metal. Slicide
(silicon and tantalum) is used as gate material. Silicides are mechanically strong.
Tantalum silicide is stable throughout standard processing.
 A molybdenum gate capped with silicides yields a metal silicide sandwich.
 Silicide/ polysilicon approach may be extended to include the formation of source and
drain regions.
Metal Interconnect Technologies for CMOS
 According to the scaling rule, it is necessary to reduce device feature sizes for
improving CMOS performance.
 In order to improve current driving capability of the scaled CMOS for high-speed
operation, low-resistance silicide technologies such as titanium silicide, cobalt silicide
and nickel silicide have been developed.
 Low-resistivity copper interconnects in conjunction with low-k interlayer dielectrics
have been developed to improve RC delay time in scaled global interconnects.
 Silicide TiSi2 has been used for several technology nodes down to 0.25 μm, but it has
become difficult to use for sub 0.25 μm technologies due to the difficulty of
maintaining low sheet resistance on small geometries.
 Copper interconnects have been introduced to substitute aluminium because of its
lower resistivity and higher electromigration resistance.
  However, Cu could not be patterned by conventional halogen plasma etching process
because of the low vapor pressure of its compound. Consequently chemical
mechanical polishing process was introduced for patterning Cu lines.
 Cu is deposited by electroplating on Cu seed layer in trench lines formed in interlayer
dielectric films.
 Dual damascene process was developed to reduce process steps for Cu via and line
formation for multilevel interconnects.
 In order to improve high-frequency performance of CMOS technology, it is necessary
to reduce not only resistivity of metal interconnects but also capacitance of interlayer
dielectrics.
 Porous low-k interlayer dielectrics are needed to reduce dielectric constants less than
2.0 for future CMOS.
 However, the mechanical strength decreased with increasing porosity.
 It is necessary to develop ultra-low-k films with both sufficient elastic modulus and
lower dielectric constant.
Local interconnect
 Local interconnect is defined in a polycrystalline silicon layer.
 Openings to underlying conducting regions are made through an insulating layer after
the local interconnect conductor definition.
 A thin extra polycrystalline silicon layer is then deposited over the device and etched
back to form polycrystalline silicon sidewall elements.
 These sidewalls connect the polycrystalline silicon local interconnect conductors to the
underlying conductive regions.
 Standard silicidation techniques are then used to form a refractory metal silicide on
the exposed underlying conductive regions, the polycrystalline silicon sidewall
elements, and the polycrystalline silicon local interconnect conductors.
 This result in a complete silicided connection between features connected by the local
interconnects conductors.
I/O structures Design
 The input/output (I/O) subsystem is responsible for communicating data between the
chip and the external world. A good I/O subsystem has the following properties:
1. Drives large capacitances typical of off-chip signals
2. Operates at voltage levels compatible with other chips
3. Provides adequate bandwidth
4. Limits slew rates to control high-frequency noise
5. Protects chip against damage from electrostatic discharge (ESD)
6. Protects against over-voltage damage
7. Has a small number of pins (low cost)
 I/O pad design requires specialized analog expertise and knowledge of processspecific
ESD structures.
 A pad consists of a square of top-level metal of approximately 100 µm on a side that is
either soldered to a bond wire connecting to the package or coated with a lead solder
ball.
 The term pad refers to the metal square or to the complete cell containing the metal,
ESD protection circuitry, and I/O transistors.
 Input and output pads usually contain built-in receiver and driver circuits to perform
level conversion and amplification.
 Basic I/O pads include VDD and GND, digital input, output, and bidirectional pads, and
analog pads.
VDD and VSS pads
 Power and ground pads are simply squares of metal connected to the package and the
on-chip power grid.
 Most high-performance chips devote half of their pins to power and ground. This large
number of pins is required to carry the high current and to provide low supply
inductance.
 One of the largest sources of noise in many chips is the ground bounce caused when
output pads switch. The pads must rapidly charge the large external capacitive loads,
causing a big current spike and high L di/dt noise.
 The problem is bad when many pins switch simultaneously (64-bit off-chip data bus).
Such busses should be interdigitated with many power and ground pins to supply the
output current through a low-inductance path.
 In many designs power and ground lines serving the output pads are separated from
the main power grid to reduce the coupling of I/O related noise into the core.
 Many chips use separate pads for the I/O power supply and for the core.
 This is essential if the I/O runs at a different voltage than the core, but it also serves to
isolate the noisy I/O power from the quieter core.
Output pads
 An output pad must have sufficient drive capability to deliver adequate rise and fall
times into a given capacitive load. If the pad drives resistive loads, it must also deliver
enough current to meet the required DC transfer characteristics.
 Given a load capacitance (typically 2–50 pF) and a rise/fall time specification, the
output transistor widths can be calculated or determined through simulation.
Typically, these transistors must be very wide and are folded into many legs.
  Output pads generally contain additional buffering to reduce the load seen by the
onchip circuitry driving the pad. Fastest buffers are built from strings of inverters with
fanouts of about 4.
 In practice, a higher fanout (6–8) gives nearly as good delay while reducing the area
and power consumption of the buffer.
 The final stage may have high fanout because the edge rates in the external world are
normally an order of magnitude longer than those on chip. However, the final stage
must be large enough to source or sink reasonable amounts of current with a small
voltage drop.
 Latchup is a particular problem near output pads, especially when the pads experience
voltage transients above VDD or below GND. These transients are likely to occur
because of ringing from the bond wire inductance and/or from driving improperly
terminated transmission lines. These transients cause the drainto-body diodes to
become forward-biased, forcing current to flow into the substrate or well and
potentially causing latchup.
 To avoid latchup, the nMOS and pMOS transistors should be separated by substantial
distances and surrounded by guard rings.
 If possible, the output transistors (i.e., those whose drains connect directly to external
circuitry) should be doubly guard-ringed. This means that an n-transistor should be
encircled with p+ substrate contacts connected to GND, and then further encircled
with n+ well contacts in an n-well connected to VDD. The rings should be continuous in
diffusion with frequent contacts to metal. Furthermore, dummy collectors consisting
of p+ connections to GND and n+ in nwell connections to VDD should be placed
between the output transistors and any internal circuitry. These dummy collectors and
guard rings serve to capture most of the stray carriers injected into the substrate when
the diodes are forward-biased. The output transistors also often have gates longer
than normal to prevent avalanche breakdown damage when overvoltage is applied to
the drains. Non silicided gates are also preferable because the polysilicon gate
resistance better distributes overvoltage across the legs of the output transistor,
preventing damage.

Fig: Double guard rings around folded nMOS output transistor

Input pads
 Input pads also contain an inverter or buffer to convert the signal from the noisy
external world into a valid logic level for the core circuitry.
 The input pad also contains electrostatic discharge (ESD) protection circuitry. The
buffer may perform level conversion.
 In a high-speed system, the buffer typically drives a clocked input register. Pads can
include pullup or pulldown resistors to place an unconnected pad in a known state.
  Some input pads also contain Schmitt triggers. A Schmitt trigger has hysteresis that
raises the switching point when the input is low and lowers the switching point when
the input is high.
 This helps filter out glitches that might occur if the input rises slowly or is rather noisy.

Fig: Schmitt trigger

Tri-state and bidirectional pads
 Figure shows a bidirectional pad with an output driver that can be tristated and an
input receiver.

Fig: Bidirectional pad circuitry

 The output driver consists of independently controlled nMOS and pMOS transistors.
When the enable is 1, one of the two transistors turns ON. When the enable is 0, both
transistors are OFF so the pad is tristated.
 Figure below shows a variation on this design in which the NAND and NOR are merged
together into a single six-transistor network with two outputs.

Fig: Improved tristate buffer

 Such a tristate buffer is smaller and presents less input capacitance on the Dout
terminal. Many pad libraries provide only a bidirectional pad. By hardwiring the enable
signal to 1 or 0, the pad can be used as an output or input.
Application of Schmitt trigger in I/O pads
Schmitt trigger circuits are used as input circuits to guard against noise-induced false
switching. Schmitt triggers are characterized by having hysteresis in their voltage transfer
curve. The hysteresis insures that small fluctuations on the rising or falling edge of the input
signal do not induce a false switching event.
Analog Pads
 Analog inputs and outputs connect to simple metal pads and then directly to the on-
chip analog circuitry without any digital buffer or driver.
 Analog pads require ESD protection circuitry.

MOSIS (Metal Oxide Silicon Implementation Service) I/O pads

 Figure shows a layout of a bidirectional pad from the MOSIS service for a 1.6 µm two-
metal layer process illustrating the general principles of pad design.


 The overall cell is about 200 µm on a side. The pad is the large (100 × 75 µm) rectangle
consisting of a sandwich of metal1 and metal2 connected with many vias.
 The SiO2 overglass covering the metal2 is etched away over the pad so the bond wire
can be connected directly to the pad.
 Two large metal2 rectangles cover most of the pad. The upper one with the legs
sticking up is GND, while the lower is VDD.
  The bidirectional pad schematic is shown in Figure below

Fig: MOSIS bidirectional pad schematic

 The input protection circuitry consists of some resistance, a thick oxide transistor and
the drain diffusion diodes of the wide output transistors.
 The resistors are n+ and p+ diffusion wires, each 3.5 squares long. They have nominal
sheet resistances of 53 and 75 Ω/□. So the parallel combination of resistance is 109Ω.
 To the left and right of the metal pad are thick oxide nMOS transistors consisting of
interdigitated fingers. They consist of a source and drain separated by 3λ, but have no
gate. They help protect the pad from ESD because high voltages will punch through the
channel and dissipate.
 The effectiveness of thick oxide transistors is process-dependent. The pad uses many
substrate/well contacts and is surrounded by double guard rings to prevent latchup
during ESD events.
 The tristate driver and receiver use extensively folded transistors to fit in the space
available.
Mixed-Voltage I/O pad
 Many chips require a low core voltage for the logic transistors and also interface with
other chips operating at higher voltages.
 The I/O pads include level converter circuits to translate between different voltage
standards.
 If Vds of a transistor becomes too large punch through occurs causing excessive current
flow until the interconnect melts.
 Transistors with smaller dimensions have a lower punch through voltage.
 I/O circuits often use transistors with longer channels and thicker oxides to endure the
higher voltages.
 Transistors can be stacked to increase their voltage tolerance.
 Table below summarizes typical logic levels for single-ended drivers.

 Logic levels definitions may vary between vendors.

 74-series logic gates of the 1970s and 1980s used the 5 V transistor-transistor logic
(TTL) standard with highly asymmetric logic levels because outputs are pulled down by
a strong transistor but pulled up by a weaker resistor.
 The 5 V CMOS standard was more symmetric. In the 1990s, low voltage (3.3 V) flavours
of TTL and CMOS were introduced.
 Bipolar circuits perform poorly below 3.3 V, so CMOS standards prevailed as voltage
continued to decrease.
 The 5 V CMOS and TTL standards are now completely obsolete, but 3.3 V LVCMOS is
still widely supported for compatibility even when the core operates at a much lower
voltage.
 Figure below shows some simple level converters for chips using a low VDDL core
voltage and higher VDDH I/O voltage.

 Figure (a) is an output driver that takes a low swing input voltage and produces a
higher-swing output voltage. It uses a CVSL structure consisting of four high-voltage
transistors indicated in bold. The inverter uses low-voltage transistors and the low-
voltage power supply. The output Y can be followed by a high-voltage inverter or
buffer to deliver more uniform rise/fall times.
 Figure (b) is an input receiver that takes a high-swing input voltage and produces a
lower-swing voltage for core circuits. It consists of a simple inverter using highvoltage
transistors that can withstand the large gate voltages.
 To avoid the need for high-voltage transistors, some output drivers use stacked
transistors. Figure below shows a cascode driver for a 3.3 V output in a 2.5 V process.

 The inner (cascode) transistors are tied to supplies in such a way that V gs and Vds across
an individual transistor never exceed 2.5 V even though the output has a larger swing.
 If the voltages on the cascode transistors are provided externally rather than
generated internally, the system must apply them in the proper sequence to avoid
momentarily exposing the I/O circuitry to damaging electric fields.