University of Basrah

College of Engineering
Department of Electrical Engineering

Digital Electronics
CS308

Third Year Class

Lecturer
Assist. Prof. Dr. Abdul-Basset A. Al-Hussein

1
➢ Basic Operational Characteristics and Parameters
Before studding the logical operation of digital ICs, you must know such operational properties as Voltage Levels,
Noise Immunity, Power Dissipation, Fan-out, and Propagation Delay Time.
➢ DC Supply Voltage:
❑ The nominal value of the dc supply voltage for TTL (transistor-transistor logic) devices is +5 V.
❑ CMOS (complementary metal-oxide semiconductor) devices are available in different supply voltages:
+5 V, +3.3 V, +2.5 V, and 1.8 V.
➢ CMOS Logic Levels
❑ There are four different logic-level specifications: VIL, VIH, VOL, and VOH.
❑ For CMOS circuits, the ranges of input voltages (VIL): LOW (logic 0): 0 V to 1.5 V for the +5 V logic, and 0 V
to 0.8 V for the 3.3 V logic.
❑ The ranges of input voltages (VIH): HIGH (logic 1): 3.5 V to 5 V for the 5 V logic and 2 V to 3.3 V for the 3.3 V
logic, as shown in Fig. 3-1.
❑ The ranges of values from 1.5 V to 3.5 V for 5 V logic and 0.8 V to 2 V for 3.3 V logic are regions of
unpredictable performance, and values in these ranges are unacceptable.
❑ The ranges of CMOS output voltage s (VOL and VOH) for both 5 V and 3.3 V logic are also shown in Fig. 3-1.
➢ TTL Logic Levels
❑ The input and output logic levels for TTL are shown in Fig.3-2.

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 Fig. 3-1 Input and output logic levels for CMOS
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Assist. Prof. Dr. Abdul-Basset A. Al-Hussein
Fig. 3-1 Continued.

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Fig. 3-2 Input and output logic levels for TTL.

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➢ Noise Immunity:
❑ Noise is unwanted voltage that is induced in electrical circuits and can effect the proper operation of the circuit.
❑ Examples of noise, the electromagnetic radiation (high-frequency) and the power-line voltage fluctuation (low-
frequency).
❑ In order to protect the logic circuit from the noise, it must have a certain amount of noise immunity.
❑ This is the ability to tolerate a certain amount of unwanted voltage fluctuation on its inputs without changing its
output state. Figure 3-3 shows the effects of input noise on the gate operation.

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Assist. Prof. Dr. Abdul-Basset A. Al-Hussein
Fig. 3-3

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➢ Noise Margin:
❑ A measure of a circuit’s noise immunity, which is expressed in volts. There are two values of noise margin
specified for a given logic circuit: the HIGH-level noise margin (VNH) and the LOW-level noise margin (VNL).
❑ These parameters are defined by the following equations:
VNH=VOH(min)-VIH(min)
VNL=VIL(max)-VOL(max)
❑ Figure 3-4 shows the noise margins.

Fig. 3-4.
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Example 3-1: Determine the HIGH-level and LOW-level noise margins for CMOS and for TTL by using the
Information in Figures 3-1 and 3-2.

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HW:

Solution: For gate A, VNH=VOH(min)-VIH(min)=2.4-2=0.4 V

VNL=VIL(max)-VOL(max)=0.8-0.4=0.4 V
For gate B, VNH=VOH(min)-VIH(min)=3.5-2.5=1 V
VNL=VIL(max)-VOL(max)=0.6-0.2=0.4 V
For gate C, VNH=VOH(min)-VIH(min)=4.2-3.2=1 V
VNL=VIL(max)-VOL(max)=0.8-0.2=0.6 V
Must select gate C.
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➢ Power Dissipation:
❑ A logic gate draws current from the dc supply voltage source as shown in Fig. 3-5.

❑ As an example, if ICCH is 1.5 mA when VCC

is 5 V and if the gate is in a HIGH output
state, the power dissipation (PD) of the gate
is
PD=VCC ICCH= 5 V * 1.5 mA= 7.5 mW

Fig. 3-5

❑ When the gate is pulsed, its output switches back and forth between HIGH and LOW, and the amount of
supply current varies between ICCH and ICCL.
❑ The average power dissipation depends on the duty cycle. When the duty cycle is 50%, the output is HIGH half
the time and LOW the other half. The average supply current is:

❑ The average power dissipation is

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Assist. Prof. Dr. Abdul-Basset A. Al-Hussein
Example 3-2: A certain gate draws 2 when its output is HIGH and 3.6 when its output is LOW. What is
its average power dissipation if VCC is 5 V and the gate is operated on a 50% duty cycle?

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➢ Propagation Delay Time:
❑ When a signal propagates through a logic circuit, it always experiences a time delay, as shown in Fig. 3-6.

Fig. 3-6 Propagation delay time.

❑ tPHL: The time between a designated point on the input pulse and the corresponding point on the output pulse
when the output is changing from HIGH to LOW.
❑ tPLH: The time between a designated point on the input pulse and the corresponding point on the output pulse
when the output is changing from LOW to HIGH.

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❑ Note that, the propagation delay of a gate limits the frequency at which it can be operated. The greater the
propagation delay time, the lower the maximum frequency. Thus, a higher-speed circuit is one that has a smaller
propagation delay time. For example, a gate with a delay of 3 ns is faster than one with 10 ns delay.

➢ Speed-Power Product:
❑ The speed-power product provides a basis for comparison of logic circuits when both propagation delay time
and power dissipation are important considerations in the selection of the type of logic to be used in a certain
application.
❑ The lower the speed-power product, the better.
❑ The unit of speed-power product is the picojoule (pJ). For example, HCMOS has a speed-power product of
1.2 pJ at 100 kHz while LS TTL has a value of 22 pJ.

➢ Loading and Fan-out:

❑ When the output of a logic gate is connected to one or more inputs
of the other gates, a load on the driving gate is created, as indicated in Fig. 3-7.
❑ There is a limit to the number of load gate inputs that a given gate can drive.
❑ This limit is called the fan-out. Fan-out is expressed as unit loads.

Fig. 3-7 Loading a gate output with

gate inputs.
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Assist. Prof. Dr. Abdul-Basset A. Al-Hussein
➢ CMOS Loading:
❑ Loading in CMOS differs from that in TTL because the type of transistors used in CMOS logic present a usually
capacitive load to the driving gate, as shown in Fig. 3-8.
❑ In this case, the limitations are the charging and discharging times associated with the output resistance of the
driving gate and the input capacitance of the load gates.
❑ When the output of the driving gate is HIGH, the input capacitance of the load gate is charging through the
output resistance of the driving gate. When the output of the driving gate is LOW, the capacitance is discharging.
❑ When more load gate inputs are added to the driving gate output, the total capacitance increases because the
input capacitances effectively appear in parallel. This increase in capacitance increases the charging and
discharging times, thus reducing the maximum frequency at which the gate can be operated. Therefore, the fan-
out of a CMOS gate depends on the frequency of operation.

Fig. 3-8 Capacitive loading of a CMOS gate.

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➢ TTL Loading:
❑ A TTL driving gate sources current to a load gate input in the HIGH state (IIH) and sinks current from the load
gate in the LOW state (IIL).
❑ Figure 3-9 shows the current sourcing and current sinking.

Fig. 3-9 Current sourcing and current sinking.

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➢ HIGH state TTL loading

❑ The fan-out is the maximum number of load gate inputs that can be connected without adversely affecting the
specified operational characteristics of the gate. For example, low-power Schottky (LS) TTL has a fan-out of
20 unit loads.

Fig. 3-10 HIGH state TTL loading.

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 ➢ LOW state TTL loading:

Fig. 3-11 Low state TTL loading.

Note: In TTL, the current –sinking capability (LOW output state) is the limiting factor in determining the fan-out.

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HW:

Solution: Yes, G2
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Assist. Prof. Dr. Abdul-Basset A. Al-Hussein
➢ CMOS Circuits:

Fig. 3-12 Basic symbols and switching

actions of MOSFETs.

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CMOS Circuits:

Fig. 3-13 A CMOS NAND gate circuit.

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 Fig. 3-14 A CMOS NOR gate circuit.

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Assist. Prof. Dr. Abdul-Basset A. Al-Hussein
➢ Tri-state CMOS Gates:

Fig. 3-15 The tri-state CMOS inverter.

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➢ TTL (bipolar) Circuits:

TTL Inverter:
❑ Figure 3-16 shows a standard TTL inverter circuit.
❑ In this circuit, Q1 is input coupling transistor, and D1 is the input
clamp diode. Transistor Q2 is called a phase splitter, and the
combination of Q3 and Q4 forms the output circuit often referred
to as a totem-pole.

❑ Diode D1 prevents negative spikes of voltage on

the input from damaging Q1.
❑ Diode D2 ensures that Q4 will turn off when Q2
is on (HIGH input). In this condition, the collector
voltage of Q2 is equal to VBE (Q3)+VCE (Q2).
❑ Diode D2 provides an additional VBE equivalent drop
in series with the base-emitter junction of Q4 to ensure
its turn-off when Q2 is on.
Fig. 3-16 A standard TTL inverter circuit.

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Assist. Prof. Dr. Abdul-Basset A. Al-Hussein
Operation of a TTL inverter:

Fig. 3-17 A TTL inverter operation.

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TTL NAND Gate: Figure 3-18 shows a 2-input
TTL NAND gate with multiple-emitter transistor is
used for input. Figure 3-19 indicate the diode
equivalent circuit for a multiple-emitter transistor.

Circuit Operation:
❑ A Low on either input A or input B forward-
biased the corresponding diode and reverse-
biases D3 (Q1 base-collector junction). This
action keep Q2 off and results in a HIGH
output. Also a LOW on both inputs will do the
same thing.
❑ A HIGH on both inputs reverse-biases both
input diodes and forward-biases D3 (Q1 base- Fig. 3-18 A TTL NAND gate circuit.
collector junction). This action turns Q2 on.
❑ The output is LOW only if all inputs are
HIGH.

Fig. 3-19 Diode equivalent of a multiple-emitter transistor.

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Open-Collector Gates:
❑ In addition to the totem-pole output circuit, there is another type of output available in TTL which is called the
open-collector, as shown in Fig. 3-20.

Open collector symbol in an inverter.

Fig. 3-20. TTL inverter with open-collector output.

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Tri-state TTL Gates:
❑ When the enable input is LOW, Q2 is off, and the output circuit operates as a normal totem-pole configuration.
❑ When the enable input is HIGH, Q2 is on, as shown in Fig. 3-21.
❑ There is a LOW on the second emitter of Q1, causing Q3 and Q5 to turn off, and diode D1 is forward biased
causing Q4 also to turn off.
❑ When both totem-pole transistors are off, they are effectively open, and the output is completely disconnected
from the internal circuitry as indicated in Fig. 3-22.

Fig. 3-22 An equivalent circuit for the tri-state

Fig. 3-21 Basic tri-state inverter. output in a high-Z state.
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Schottky TTL:
❑ Most Schottky TTL logic provides a faster switching time by incorporating Schottky diodes to prevent transistors
from going into saturation, thereby decreasing the time for a transistor to turn on or off.
❑ Figure 3-23 shows the Schottky gate circuit.

Fig. 3-23 Schottky TTL NAND gate.

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Assist. Prof. Dr. Abdul-Basset A. Al-Hussein
Example 3-3: When a standard TTL NAND gate devices drives five TTL inputs, how much current dose the
driver output source, and how much does it sink? (Refer to Figure below)

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Solution: Total source current (in HIGH output state):
IIH (max)=40 uA per input.
IT(source)=(5 inputs)(40 uA/input)=5*40=200 uA

Total sink current (in LOW output state):

IIL(max)=-1.6 mA per input
IT(sink)=(5 inputs)(-1.6mA/input)=5*-1.6mA=-0.8 mA.
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 HW: Repeat the calculations in example 3-3 for an LS TTL NAND gate that drives five inputs. Refer to a data
available at www.ti.com.
Using Open-Collector Gates for Wired-AND Operation:
❑ The output of open-collector gates can be wired together to form what is called a wired-AND configuration.
❑ Figure 3-24 shows how four inverters are connected to produce a 4-input negative-AND gate.
❑ Note that the output X is HIGH only when all the inputs are LOW. Therefore, we have a negative-AND
function.
❑ Figure 3-25 shows the open-collector wired negative-AND gate with inverters.

Fig. 3-24
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 Fig. 3-25.

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Example 3-4: Write the output expression for the wired-AND configuration of open-collector AND gates in
Fig. 3-26.

Solution: The output expression is

X=ABCDEFGH

The wired-AND connection of the four 2-input AND gates creates an 8-inputs
AND gate.

HW: Determine the output expression if NAND gates are used in Fig. 3-26.

Fig. 3-26.

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Example 3-5: Three open-collector AND gates are connected in a wired-AND configuration as shown in Fig. 3-27.
Assume that the wired-AND circuit is driving four standard TTL inputs (-1.6 mA each).
(a) Write the logic expression for X.
(b) Determine the minimum value of Rp if IOL(max) for each gate is 30 mA and VOL(max) is 0.4 V.

Solution: (a) X=ABCDEF

(b) Total current= 4(1.6 mA)=6.4 mA
IRp= IOL(max)-6.4=30-6.4=23.6 mA

Rp=Vcc-VOL(mxa)/IRp=5-0.4/23.4mA=195 Ohm

HW: Show the wired-AND circuit for a 10-input AND function using
74LS09 quad 2 input AND gates.

Fig. 3-27.

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Connection of Totem-Pole Outputs:
❑ Totem-pole outputs cannot be connected together because such connection might produce excessive current and
result in damage to the devices. For example, when Q1 in device A and Q2 in device B are both on, the output
of device A is effectively shorted to ground through Q2 of device B as shown in Fig. 3-28.

Fig. 3-28.

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Open-Collector Buffer/Drivers

❑ A TTL circuit with a totem-pole output is limited in the amount of current that it can sink in the LOW state
(IOL(max)) to 16 mA for standard TTL and 8 mA for LS TTL.
❑ In many special applications, a gate must drive external devices, such as LEDs, lamps, or relays, that may
require more current than that.
❑ Because of their higher voltage and current-handling capability, circuits with open-collector outputs are
generally used for driving LEDs, lamps, or relays.
❑ Totem-pole outputs can be used, as long as the output current required by the external devices does not exceed
the amount that the TTL driver can sink.
❑ A typical open-collector buffer gate can sink up to 40 mA. In Fig. 3-29-a, the lamp requires no limiting resistor
because the filament is resistive. Typically, up to +30 V can be used on the open collector, depending on the
particular logic family.

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 Fig. 3-29.

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Example 3-6: Determine the value of the limiting resistor, RL, in the open-collector circuit of Fig. 3-30 if the LED
current is to be 20 mA. Assume a 1.5 V drop across the LED when it is forward-biased and a LOW-
state output voltage of 0.1 V at the output of the gate.

Solution:

VRL=5 V- 1.5 V= 3.4 V

RL=VRL/I= 3.4 V/ 20 mA= 170 Ohm.

Fig. 3-30.

HW: Determine the value of the limiting resistor, RL, if the LED requires 35 mA.

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Tied-Together Inputs:
❑ The most common method for handling unused gate inputs is to connect them to a used input of the same gate.
❑ For AND gates and NAND gates, all tied-together inputs count as one unit load in the LOW state;
❑ But for OR gates and NOR gates, each input tied to another input counts as a separate unit load in the LOW state.
❑ In the HIGH state, each tied-together input counts as a separate load for all types of TTL gates.
❑ Figure 3-31-a shows the methods of handling unused TTL inputs.
The AND and NAND gates present only a single unit load no matter how many inputs are tied together, whereas
OR and NOR gates present a unit load for each tied-together input.
This is because the NAND gate uses a multiple-emitter input transistor; so no matter how many inputs are LOW,
the total LOW-state current is limited to a fixed value. The NOR gate uses a separate transistor for each input;
therefore, the LOW-state current is the sum of the currents from all the tied-together inputs.
Inputs to Vcc or Ground:
❑ Unused inputs of AND and NAND gates can be connected to Vcc through a 1 k ohm resistor.
❑ This connection pulls the unused inputs to a HIGH level. Unused inputs of OR and NOR gates can be connected
to ground. These methods are indicated in Fig. 3-31-b.

Inputs to unused output:

❑ The unused gate output must be a constant HIGH for unused AND and NAND inputs and a constant LOW for
unused OR and NOR inputs, as shown in Fig. 3-31-c.
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 Fig. 3-31.

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Assist. Prof. Dr. Abdul-Basset A. Al-Hussein
Comparison of CMOS and TTL performance:

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Emitter-Coupled Logic (ECL) Circuits:

❑ ECL like TTL is a bipolar technology. The typical ECL circuit consists of a differential amplifier input circuit,
a bias circuit, and emitter follower outputs.
❑ ECL is much faster than TTL because transistors do not operate in saturation and is used in more specialized
high-speed applications.
❑ An ECL OR/NOR gate is shown in Fig. 3-32-a.
❑ Because of the low output impedance of the emitter-follower and the high input impedance of the differential
amplifier input, high fan-out operation is possible.
❑ The lack of saturation results in higher power consumption and limited voltage swing (less than 1 V), but it
permits high-frequency switching.
❑ The Vcc pin is normally connected to ground, and the VEE pin is connected to -5.2 V from the power supply for
best operation.
❑ The output varies from a LOW level of -1.75 V to a HIGH level of -0.9 V with respect to ground.
❑ In positive logic, a 1 is the HIGH level (less negative), and a 0 is the LOW level (more negative).

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 Fig. 3-32.

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Noise Margin: Typical ECL circuits have noise margins from 0.2 V to 0.25 V. These are less than for TTL and
make ECL less suitable in high-noise environments.

Comparison of ECL with TTL and CMOS:

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Problems:
1. Use open collector inverters to implement the following logic expressions:

2. Write the logic expression for each of the circuits in Fig. 3-33.

Fig. 3-33

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Assist. Prof. Dr. Abdul-Basset A. Al-Hussein
Problem 1 solution: see Fig. 3-35.

Fig. 3-35.

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3. Determine the minimum value for the pull-up resistor in each circuit in Fig. 3-33 if IOL(max)= 40 mA and
VOL(max)= 0.25 V for each gate. Assume that 10 standard TTL unit loads are being driven form output X and
the supply voltage is 5 V.
4. A certain relay requires 60 mA. Devise a way to use open collector NAND gates with IOL(max)= 40 mA to drive
the relay.
5. Determine the total propagation delay from each input to each output for each circuit in Fig. 3-34.

Fig. 3-34.

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Assist. Prof. Dr. Abdul-Basset A. Al-Hussein