2023 IEEE 2nd International Conference on Electrical Engineering, Big Data and Algorithms (EEBDA)

Analysis and Comparison of UART, SPI and I2C

Jinrong Chen†, * Shengqiu Huang†
2023 IEEE 2nd International Conference on Electrical Engineering, Big Data and Algorithms (EEBDA) | 978-1-6654-6253-2/23/$31.00 ©2023 IEEE | DOI: 10.1109/EEBDA56825.2023.10090677

XJTLU University Shanghai United International School, Wanyuan Campus

Suzhou, 215123, China Shanghai, 200050, China
Jinrong.Chen20@student.xjtlu.edu.cn
*Corresponding author
†
These authors contribute equally.

Abstract—Nowadays there are many hardware characterized by low power consumption and strong anti-
communications protocols to choose from, UART, SPI, I2C interference ability. Through the working principle and
three protocols are the most representative, they are widely used. characteristics of the above protocols, we get a better solution
They have different characteristics, and how to choose the right in the specific working environment or the general working
choice is a problem that has been bothering people for a long environment and provide new solutions for the application of
time. In this article, the composition of the three protocols, how the protocol in different scenarios, in the pursuit of low-
they work, and their advantages or disadvantages are described power environment solutions or the choice of long-distance
separately. And through the comparison of their transmission transmission, or the pursuit of excellent choices under high-
distance, it will be found that today's SPI protocol can transmit
speed transmission. The entire article aims to offer fresh
a longer distance, in the comparison of transmission rates SPI
protocol has a faster rate but many limited conditions, UART
suggestions for protocol collocation and selection.
has a more stable performance, SPI has a variety of II. UART
transmission modes to choose from. In terms of transmission
power consumption, UART has a huge advantage, Universal Asynchronous Receiver/Transmitter is an
outperforming the other two protocols. Through the article, we Asynchronous serial communication protocol. It is one of the
hope to provide a new way of thinking from the purpose most widely used hardware-to-hardware communication
required for the design. This leads to a new perspective on protocols. Nowadays UART has been used in many
protocol selection applications such as various types of environmental sensors,
wireless communication modules, and so on [1].
Keywords--UART, SPI, I2C
A. Working principle of UART
I. INTRODUCTION UART is a serial communication protocol, that differs
Various communication protocols are available from parallel communication, transmissions in that the
nowadays, each protocol has its own advantages and transmitted data does not reach the receiver at the same time
disadvantages, and the choice of hardware transmission [2]. It is transmitted bit by bit to the receiver via a data line.
protocol is also different in different situations. The topic to This means that its transfer rate may be slower than the
be covered in this post is how to pick a suitable protocol. The transfer rate of the parallel transfer protocol. The
following article discusses a few of the most well-liked transmitter’s TX pin is directly connected with the receiver’s
communication protocols now in use and examines RX pin. Data travels to and from a UART in parallel to the
numerous protocols' properties to determine which are control device, such as microcontrollers and microprocessors.
preferable and superior. UART is a widely used hardware When sending on the TX pin, the transmitter’s UART needs
communication protocol that requires only two data lines to to translate parallel information into serial and transmit it to
complete bidirectional data transmission and does not require the receiver. The receiver receives this data and translates it
clock signals for synchronous operation. It transfers data in back to parallel, then communicate with its controller.
packets, each with a variable size of data. A check digit can Another feature that distinguishes UART from other
be included in the package to guarantee security and integrity communication protocols is that the transmitter and receiver
during data transmission. Synchronization between the are not synchronized through the clock signal. Instead, the
transmitter and receiver is achieved by bit rate, which allows transmitter and receiver synchronize with each other at the
two devices operating at different frequencies to same baud rate. The baud rate is expressed in bits per second
communicate. The SPI protocol is a very fast transmission or bps, it is usually 9600 or 115200.
protocol that allows the master to communicate with the slave
at a higher frequency. The SPI protocol allows only one B. Structure of the UART
master to exist, but multiple slaves can exist. The master is UART transmitted data is organized into packets. Each
responsible for generating a clock signal that is used to packet contains 1 start bit, 5 to 9 data bits, a parity bit (ability
synchronize with its slave. The SPI saves pins by occupying to choose whether to use or not), 1 or 2 or 1/2 stop bits.
only 4 wires in the chip, which also benefits saving PCB START BIT: The UART protocol is in a high-level state
layout space. The I2C protocol is a two-wire serial bus that when the data line is idle. When data transfer starts, the
requires only two bidirectional lines, a serial data line, and a transmitter will change the level of the transmission line from
serial clock line. The bus interface is formed within the chip, high to low for one clock. It is added before the actual data.
optimizing space and cost. It supports multi-master and The receiver detects this change from high to low on the data
multi-slave devices, but only one host is allowed at a time. line and starts receiving the actual data.
The number of I2C protocols connected to the bus is limited
only by the maximum capacitance of the bus. It is DATA BITS: The data bits are the actual data that is

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transmitted between transmitter and receiver. The length of In master-slave mode, SPI operates. The slave is typically
data can be anywhere between 5 to 9 bits. In particular, 9-bit an EPROM, Flash, AD/DA, audio and video processing chip,
data is the resulting length without the use of parity bits. Most or other devices, while the host is typically a programmable
of the time the maximum data length is 8 bits. controller such as an FPGA, MCU, or DSP. The SCLK, CS,
MOSI, and MISO lines make up the majority of them. SCK,
PARITY BIT: The parity bit can help the receiver check SS, SDI, and SDO are examples of names that all have the
if any data has changed during the transmission. Bits can be same meaning. When there are multiple slave devices, the CS
changed in kinds of error, such as receiving overflow lost is used to select the slave device to be controlled.
data, the reason it has received lots of data but it cannot
process at once. Unfinished UART transmission results in A. Working principle of SPI
data loss, use this function to enter hibernation after sending, In general, the working mode of the machine parts is fixed,
power off the receiving device, and so on. After the receiver and the host machine needs to adopt the same working mode.
reads the data, the number of digits is counted as 1 and The Controller generally refers to the control registers in the
determines whether the total is odd or even if the parity bit is SPI device, which can be configured to set the transmission
0, the number of 1s in the packet is even, and if the parity bit mode of the SPI bus, so that both sides can normally
is 1, the number of 1s in the packet is odd. "communicate".
END BITS: As the name suggests, it is marking the end When the SPI is idle, the clock signal's polarity—
of the data packet. Typically, the stop bit occupies 1 or 2 CPOL—shows whether it is high or low. When the device is
clocks, but it is also possible to set 1/2 clocks. When the stop not in use, the clock signal at the SCK tube's foot is high if
bit ends, the data line is idle and its level returns to the high CPOL is set to 1. When CPOL is set to 0, the opposite is
position. accurate. SCK is zero when it is not in use, as shown by
C. Features of UART CPOL=0. When SCK is in use, CPOL=1 indicates that it is 1.
Unlike other hardware communication protocols, UART CPHA: clock phase, which specifies whether the SPI
only requires two data lines for full-duplex data transmission, device starts sampling data when the clock signal on the SCK
such as the SPI protocol, which requires at least four data pin transitions to a rising edge or a falling edge. If CPHA is
lines to be connected to each other. UART also does not set to 1, the clock signal's rising and falling edges cause the
require a clock or other time signal for communication SPI device to sample data and transfer data, respectively.
between two devices. Because of the presence of a parity bit, When CPHA is set to zero, the opposite is accurate. At the
the basic accuracy of the transmitted data is ensured when first edge of SCK, CPHA=0 denotes that the input and output
used. UART has a wide range of hardware applications and data are legitimate. The input and output data are valid at the
a variety of use scenarios. The UART protocol also has second edge of SCK when CPHA=1[4]. Of the four modes,
excellent power performance, enabling an advance in the modes 0 and 3 are the most widely used, and most SPI
development of green communication technology and is devices support both modes.
proven in Artix-7[3].
B. Structure of the SPI
As for its disadvantages, there are mainly the following By default, when we discuss SPI, we are referring to the
points: The maximum package size transmitted is limited to conventional 4-wire Motorola SPI protocol, which has four
9 bits. Compared to parallel transmissions, UART has a data lines total: SCLK, MOSI, MISO, and CS. The typical 4-
lower transmission rate. The UART protocol is not a bus wire system has the benefit of enabling full duplex data
communication, it cannot communicate with multiple transfer. An SPI interface can have only one host, but it can
devices at the same time, at a time can only be one-to-one have one or more slaves. One CS is required when there is
communication. Unlike the SPI protocol, a host can have just one host and one slave device, however, many slave
multiple slaves, the I2C protocol can allow multiple hosts to devices require several CS. MOSI and MISO are data lines.
exist with multiple slaves. The difference in baud rate MOSI sends data from the master to the slave, and MISO
between two UART protocol devices that communicate with sends data from the slave to the master [5]. The beginning of
each other should not exceed 10%. every data line: clock signal, or SCLK. The host output, slave
III. SPI input, host data MISO, host input, slave output, CS, slave
device selection, and active low level are all components of
The serial Peripheral Interface is known as SPI. It is a the SPI rate, which is determined by the clock frequency. The
full-duplex, high-speed synchronous communication bus that connection schematic was shown in figure 2 below.
only uses four pins on the chip, saving the chip's pins, freeing
up space, and making the PCB layout easier. More and more
chips, including AT91RM9200, are integrating this
communication protocol because of how simple it is to use.
The working principle is shown in Figure 1 below.

Figure 2. Working connection diagram

There are two primary varieties of 3-wire SPI, depending

on the various application scenarios:
Figure 1. Master-slave diagram
For simcom communication, some peripherals have only

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three SPI buses, one CS, one CLK, and one MOSI/MISO, output since they are on the same signal line as the slave
which means that the input and output of data are the same machine's MISO pins.
data line. The SCLK, SDIO, and CS wires are the only ones
present. A bidirectional port for half-duplex communication Daisy chain configuration is SPI's second connecting
is the SDIO. For instance, ADI's numerous ADC chips enable option. Daisy chaining is the process of serially transmitting
bidirectional transmission. Bidirectional ports should be signal wires from one device to the next until the data reaches
operated by FPGAs with high resistance state Z set when the destination device [6].
utilized as input. The primary drawback of the Daisy chain is that it will
disconnect the slave machine that has a lower priority than
C. Additional information
the device if the slave machine has a single point of failure.
There are several special characteristics shown through The priority for service will be lower for the slave machine
the SPI bus, not only limit to its high-frequency that is further away from the host machine. If necessary,
communication speed but also the daisy chain connection configure the priority going forward and the slave line
type can be shown that SPI is a superior communication detector [6].
protocol.
To avoid a single point of failure causing the entire link
1) Different connection structure to fail, respond quickly if a slave server times out.
SPI has two types of connections. The traditional The SPI shift register is fully utilized in daisy-chain mode
independent slave setup is the first. Each slave requires their when each slave copies input data to output in the subsequent
own CS line. The matching CS signal line is brought down clock cycle. The difference comparison diagram is shown in
while the other CS signal lines are kept high when the host Figure 3.
wants to talk to a certain slave. The MISO pins of the
unselected slave machine must be set up with high-resistance

Figure 3. Link comparison diagram

The primary drawback of Daisy chain is that it will IV. I2C

disconnect the slave machine that has a lower priority than
the device if the slave machine has a single point of failure. The full name of the I2C bus can be called IIC or Inter-
The priority for service will be lower for the slave machine Integrated Circuit. The number two in the phrase would
that is further away from the host machine. If necessary, likely be square, not two. The I2C is a synchronous, multi-
configure the priority going forward and the slave line controller and targets serial communication bus, developed
detector. by Philips Semiconductor in 1982. The most significant point
of this serial communication bus is that it can connect with
To avoid a single point of failure causing the entire link multiple devices with two lines, and the device can have the
to fail, respond quickly if a slave server times out. chance to change its characteristic with master and slave [7].
Also, there are different communication modes that can be
The SPI shift register is fully utilized in daisy-chain mode
chosen by developers. I2C is used to connect devices like
when each slave copies input data to output in the subsequent
microcontrollers, EEPROMs, I/O interfaces, and other
clock cycle.
peripheral devices in an embedded system [8]. For example,
2) Transmission rate air pressure sensor connected between Arduino and the
sensor would be a perfect application for the I2C bus. The
In contrast to I2C's normal mode of 100K, fast mode of ADC and DAC chip would convert the analog data to a
400K, and high-speed mode of 3.4m, the SPI protocol does digital i2c signal to keep the number constant and accurate.
not have a set rate. Instead, the maximum SPI clock
frequency, the CPU's capacity to interpret SPI data, and the A. Working principle of I2C
driving capacity of the output end all play major roles in I2C uses two wires, SCL and SDA, also known as Serial
determining the SPI transmission rate (maximum signal Clock Line and Serial Data Line, to connect with dozens of
transmission rate should be followed by the PCB layout). devices. Each device owns an addressing code with 7 bits.
From i2c-bus.org, it suggested that the bite width with 7 can
theoretically allow 128 I2C addresses, but for certain reasons,

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there are several addresses with special purposes, which are distance is about 200mm to 300mm without the use of
“0000000 0, 0000000 1, 0000001 X, 0000010 X, 0000011 X, repeaters. As can be seen in the above transmission
00001XX X, 11110XX X, 11111XX X”, has been noted as characteristics, the SPI protocol can be used under the
binary, 10-bit addresses [7]. requirements of the application environment that requires
long-distance transmission. The UART protocol operates at
The i2c simulation and concepts are based on the square different rates under different standards at different transfer
wave oscillation, in which electromagnetic or other rates, with a transfer rate of 20Kbps under RS-232 standards.
interference has not been considered. By using capacitors on Under the RS-422 standard, its transmission rate can reach
both SCL and SDA wire could reduce and filter the noise of 10Mbps. And the longer the transmission distance, the
the wave. However, the character of the capacitor and the smaller the maximum transmission rate. The transfer rate of
charging period would affect by the size of the capacitor. It the I2C protocol has different maximum transfer rates in
is extremely important to consider what size of the capacitor different modes, and its transfer rate is up to 100Kbps in
to use since the clock and data line should reach the logical standard mode. In ultra-fast mode it has a maximum transfer
high voltage, or the massage wouldn’t be recognized [8]. rate of 5Mbps. [10] The transmission rate of the SPI protocol
From Texas Instruments’ suggestion, the capacitor used for can reach up to 50Mbps, but its maximum transmission rate
the I2C bus of each device should follow the 400 pF for both is subject to three conditions: 1. System clock frequency 2.
Standard Mode and Fast Mode and specifies 550 pF for Fast CPU processing SPI data capability 3. Maximum signal
Mode Plus [9]. The following figure 4 shows the waveform. transmission rate allowed by the PCB. If the design requires
high-speed transmission, the SPI protocol's high rate is an
option. If the design requires simple connections and a
streamlined layout, I2C can do it. If the design is designed to
save energy, then UART is the best choice, it consumes much
less power than the other two protocols at 0.0135W.[11]
Figure 4. Operation waveform diagram
VI. CONCLUSION
B. Structure of the I2C
In this experiment, after studying the working principle,
As the I2C bus is resting, both SCL and SDA wires are format description and personality characteristics of UART,
keeping HIGH. When the device is planning to transfer data, we found that: The transmission rate of UART may be lower
SDA would switch to LOW and start transferring data than some parallel protocols, and the transmitter and receiver
through the SDA wire, and the clock wire would provide the are synchronized with each other without any medium. And
clock message to each of the devices. When the device is use packet form in transmission. The most important thing is
planning to stop transferring data, the SDA would switch that UART data transmission only requires two data lines,
from LOW to HIGH while the SCL is in HIGH condition. and it is a full duplex system, although it can only be one-to-
For writing data, the device first sends the stop signal to one, it can have multiple slave machines to achieve one-to-
the bus, reduces the condition of failing to write; then sends many.
the rest signal, the start signal. Send the address of 7 bits, and Then, we analyse all aspects of the SPI protocol and
the slave device would send back a feedback signal. Then conclude that SPI as a full-duplex and high-speed
start transferring data with 8 bits, getting back a feedback communication line can simplify the layout and the host can
signal from the slave as a period. For ending, send a stop change the controller by itself. The fourth line is a full duplex,
signal to the I2C bus, and release the bus in an idle state. while the third line is only half a duplex. It can be configured
C. Flaws of I2C to set the main transmission mode, and the rate is constantly
For several reasons, there are some disadvantages that changing. Chrysanthemum link is undoubtedly a very good
I2C is not suggested to be applicated in long-distance way of application, but the disadvantage is easy to cause the
communication. Though there are some ways that can solve failure of the point.
the bit flip issues, the parasitic capacitance from the PCB or Finally, we reviewed the relevant literature on I2C and
wire cannot be solved as a physical defect. If the material of made a self-perception. I2C can connect multiple Settings
the wire is inferior, the fluctuation of the parasitic with two lines, its characteristics can be changed, and the
capacitance and the resistance of the wire will further affect wave noise can be reduced to a certain extent. Finally, it has
the stability of the i2c bus. If the resistance is too large, the high requirements on wire material, because it will affect the
master cannot parse the data of the slaves, which will lead to stability of the bus, and too much resistance will affect the
a series of unreliable problems. analysis of server data.
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