Features

• Compatible with MCS-51™ Products

• 8K Bytes of In-System Reprogrammable Downloadable Flash Memory
– SPI Serial Interface for Program Downloading
– Endurance: 1,000 Write/Erase Cycles
• 2K Bytes EEPROM
– Endurance: 100,000 Write/Erase Cycles
• 4.0V to 6V Operating Range
• Fully Static Operation: 0 Hz to 24 MHz
• Three-Level Program Memory Lock
•
•
256 x 8-bit Internal RAM
32 Programmable I/O Lines
8-Bit
•
•
Three 16-bit Timer/Counters
Nine Interrupt Sources
Microcontroller
• Programmable UART Serial Channel
• SPI Serial Interface with 8K Bytes
• Low Power Idle and Power Down Modes
• Interrupt Recovery From Power Down Flash
• Programmable Watchdog Timer
• Dual Data Pointer
• Power Off Flag
AT89S8252
Description
The AT89S8252 is a low-power, high-performance CMOS 8-bit microcomputer with
8K bytes of Downloadable Flash programmable and erasable read only memory and
2K bytes of EEPROM. The device is manufactured using Atmel’s high density nonvol-
atile memory technology and is compatible with the industry standard 80C51 instruc-
tion set and pinout. The on-chip Downloadable Flash allows the program memory to
be reprogrammed in-system through an SPI serial interface or by a conventional non-
volatile memory programmer. By combining a versatile 8-bit CPU with Downloadable
Flash on a monolithic chip, the Atmel AT89S8252 is a powerful microcomputer which
provides a highly flexible and cost effective solution to many embedded control appli-
cations.
The AT89S8252 provides the following standard features: 8K bytes of Downloadable
Flash, 2K bytes of EEPROM, 256 bytes of RAM, 32 I/O lines, programmable watch-
dog timer, two Data Pointers, three 16-bit timer/counters, a six-vector two-level inter-
rupt architecture, a full duplex serial port, on-chip oscillator, and clock circuitry. In
addition, the AT89S8252 is designed with static logic for operation down to zero fre-
quency and supports two software selectable power saving modes. The Idle Mode
stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt sys-
tem to continue functioning. The Power Down Mode saves the RAM contents but
freezes the oscillator, disabling all other chip functions until the next interrupt or hard-
ware reset.
The Downloadable Flash can be changed a single byte at a time and is accessible
through the SPI serial interface. Holding RESET active forces the SPI bus into a serial
programming interface and allows the program memory to be written to or read from
unless Lock Bit 2 has been activated.

0401D-A–12/97

4-105
Pin Configurations
PDIP PLCC

P1.1 (T2 EX)

(T2) P1.0 1 40 VCC

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P1.4 (SS)

P1.0 (T2)
(T2 EX) P1.1 2 39 P0.0 (AD0)
P1.2 3 38 P0.1 (AD1)

VCC
P1.3
P1.2

NC
P1.3 4 37 P0.2 (AD2)
(SS) P1.4 5 36 P0.3 (AD3)

6
5
4
3
2
1
44
43
42
41
40
(MOSI) P1.5 6 35 P0.4 (AD4) (MOSI) P1.5 7 39 P0.4 (AD4)
(MISO) P1.6 7 34 P0.5 (AD5) (MISO) P1.6 8 38 P0.5 (AD5)
(SCK) P1.7 8 33 P0.6 (AD6) (SCK) P1.7 9 37 P0.6 (AD6)
RST 9 32 P0.7 (AD7) RST 10 36 P0.7 (AD7)
(RXD) P3.0 10 31 EA/VPP (RXD) P3.0 11 35 EA/VPP
(TXD) P3.1 11 30 ALE/PROG NC 12 34 NC
(INT0) P3.2 12 29 PSEN (TXD) P3.1 13 33 ALE/PROG
(INT1) P3.3 13 28 P2.7 (A15) (INT0) P3.2 14 32 PSEN
(T0) P3.4 14 27 P2.6 (A14) (INT1) P3.3 15 31 P2.7 (A15)
(T1) P3.5 15 26 P2.5 (A13) (T0) P3.4 16 30 P2.6 (A14)
(WR) P3.6 16 25 P2.4 (A12) (T1) P3.5 17 29 P2.5 (A13)

18
19
20
21
22
23
24
25
26
27
28
(RD) P3.7 17 24 P2.3 (A11)
XTAL2 18 23 P2.2 (A10)

(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
NC
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
XTAL1 19 22 P2.1 (A9)
GND 20 21 P2.0 (A8)

PQFP/TQFP
P1.1 (T2 EX)

P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P1.4 (SS)

P1.0 (T2)

VCC
P1.3
P1.2

NC
44
43
42
41
40
39
38
37
36
35
34

(MOSI) P1.5 1 33 P0.4 (AD4)

(MISO) P1.6 2 32 P0.5 (AD5)
(SCK) P1.7 3 31 P0.6 (AD6)
RST 4 30 P0.7 (AD7)
(RXD) P3.0 5 29 EA/VPP
NC 6 28 NC
(TXD) P3.1 7 27 ALE/PROG
(INT0) P3.2 8 26 PSEN
(INT1) P3.3 9 25 P2.7 (A15)
(T0) P3.4 10 24 P2.6 (A14)
(T1) P3.5 11 23 P2.5 (A13)
12
13
14
15
16
17
18
19
20
21
22
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
GND
(A8) P2.0
(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4

Pin Description Port 0 also receives the code bytes during Flash program-
ming and outputs the code bytes during program verifica-
VCC tion. External pullups are required during program verifica-
Supply voltage. tion.
GND Port 1
Ground. Port 1 is an 8-bit bidirectional I/O port with internal pullups.
Port 0 The Port 1 output buffers can sink/source four TTL inputs.
Port 0 is an 8-bit open drain bidirectional I/O port. As an When 1s are written to Port 1 pins, they are pulled high by
output port, each pin can sink eight TTL inputs. When 1s the internal pullups and can be used as inputs. As inputs,
are written to port 0 pins, the pins can be used as high- Port 1 pins that are externally being pulled low will source
impedance inputs. current (IIL) because of the internal pullups.
Port 0 can also be configured to be the multiplexed low- Some Port 1 pins provide additional functions. P1.0 and
order address/data bus during accesses to external pro- P1.1 can be configured to be the timer/counter 2 external
gram and data memory. In this mode, P0 has internal pul- count input (P1.0/T2) and the timer/counter 2 trigger input
lups. (P1.1/T2EX), respectively.

4-106 AT89S8252
 AT89S8252

Block Diagram
P0.0 - P0.7 P2.0 - P2.7

VCC
PORT 0 DRIVERS PORT 2 DRIVERS

GND

RAM ADDR. PORT 0 PORT 2

EEPROM REGISTER RAM LATCH LATCH FLASH

PROGRAM
B STACK ADDRESS
REGISTER ACC POINTER REGISTER

BUFFER
TMP2 TMP1

PC
ALU INCREMENTER

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PROGRAM
PSW COUNTER

PSEN
ALE/PROG TIMING INSTRUCTION
AND REGISTER DPTR
EA / VPP CONTROL
RST

WATCH PORT 3 PORT 1 SPI PROGRAM

DOG LATCH LATCH PORT LOGIC

OSC
PORT 3 DRIVERS PORT 1 DRIVERS

P3.0 - P3.7 P1.0 - P1.7

4-107
Furthermore, P1.4, P1.5, P1.6, and P1.7 can be configured
as the SPI slave port select, data input/output and shift
Port Pin Alternate Functions
clock input/output pins as shown in the following table.
P3.0 RXD (serial input port)
Port Pin Alternate Functions
P3.1 TXD (serial output port)
P1.0 T2 (external count input to Timer/Counter 2),
clock-out P3.2 INT0 (external interrupt 0)
P1.1 T2EX (Timer/Counter 2 capture/reload trigger P3.3 INT1 (external interrupt 1)
and direction control)
P3.4 T0 (timer 0 external input)
P1.4 SS (Slave port select input)
P3.5 T1 (timer 1 external input)
P1.5 MOSI (Master data output, slave data input pin
P3.6 WR (external data memory write strobe)
for SPI channel)
P3.7 RD (external data memory read strobe)
P1.6 MISO (Master data input, slave data output pin
for SPI channel)
RST
P1.7 SCK (Master clock output, slave clock input pin Reset input. A high on this pin for two machine cycles while
for SPI channel) the oscillator is running resets the device.

Port 1 also receives the low-order address bytes during ALE/PROG

Flash programming and verification. Address Latch Enable is an output pulse for latching the
low byte of the address during accesses to external mem-
Port 2 ory. This pin is also the program pulse input (PROG) during
Port 2 is an 8-bit bidirectional I/O port with internal pullups. Flash programming.
The Port 2 output buffers can sink/source four TTL inputs.
In normal operation, ALE is emitted at a constant rate of 1/6
When 1s are written to Port 2 pins, they are pulled high by
the oscillator frequency and may be used for external tim-
the internal pullups and can be used as inputs. As inputs,
ing or clocking purposes. Note, however, that one ALE
Port 2 pins that are externally being pulled low will source
pulse is skipped during each access to external data mem-
current (IIL) because of the internal pullups.
ory.
Port 2 emits the high-order address byte during fetches
If desired, ALE operation can be disabled by setting bit 0 of
from external program memory and during accesses to
SFR location 8EH. With the bit set, ALE is active only dur-
external data memory that use 16-bit addresses (MOVX @
ing a MOVX or MOVC instruction. Otherwise, the pin is
DPTR). In this application, Port 2 uses strong internal pul-
weakly pulled high. Setting the ALE-disable bit has no
lups when emitting 1s. During accesses to external data
effect if the microcontroller is in external execution mode.
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register. PSEN
Port 2 also receives the high-order address bits and some Program Store Enable is the read strobe to external pro-
control signals during Flash programming and verification. gram memory.
When the AT89S8252 is executing code from external pro-
Port 3
gram memory, PSEN is activated twice each machine
Port 3 is an 8 bit bidirectional I/O port with internal pullups.
cycle, except that two PSEN activations are skipped during
The Port 3 output buffers can sink/source four TTL inputs.
each access to external data memory.
When 1s are written to Port 3 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs, EA/VPP
Port 3 pins that are externally being pulled low will source External Access Enable. EA must be strapped to GND in
current (IIL) because of the pullups. order to enable the device to fetch code from external pro-
Port 3 also serves the functions of various special features gram memory locations starting at 0000H up to FFFFH.
of the AT89S8252, as shown in the following table. Note, however, that if lock bit 1 is programmed, EA will be
internally latched on reset.
Port 3 also receives some control signals for Flash pro-
gramming and verification. EA should be strapped to VCC for internal program execu-
tions. This pin also receives the 12-volt programming
enable voltage (VPP) during Flash programming when 12-
volt programming is selected.

4-108 AT89S8252
 AT89S8252

XTAL1 Special Function Registers

Input to the inverting oscillator amplifier and input to the
A map of the on-chip memory area called the Special Func-
internal clock operating circuit.
tion Register (SFR) space is shown in Table 1.
XTAL2 Note that not all of the addresses are occupied, and unoc-
Output from the inverting oscillator amplifier. cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indeterminate
effect.

Table 1. AT89S8252 SFR Map and Reset Values

0F8H 0FFH

B
0F0H 0F7H
00000000

0E8H 0EFH

ACC
0E0H 0E7H
00000000

0D8H 0DFH

PSW SPCR
0D0H 0D7H
00000000 000001XX

T2CON T2MOD RCAP2L RCAP2H TL2 TH2

0C8H 0CFH
00000000 XXXXXX00 00000000 00000000 00000000 00000000

0C0H 0C7H

IP
0B8H 0BFH
XX000000

P3
0B0H 0B7H
11111111

IE SPSR
0A8H 0AFH
0X000000 00XXXXXX

P2
0A0H 0A7H
11111111

SCON SBUF
98H 9FH
00000000 XXXXXXXX

P1 WMCON
90H 97H
11111111 00000010

TCON TMOD TL0 TL1 TH0 TH1

88H 8FH
00000000 00000000 00000000 00000000 00000000 00000000

P0 SP DP0L DP0H DP1L DP1H SPDR PCON

80H 87H
11111111 00000111 00000000 00000000 00000000 00000000 XXXXXXXX 0XXX0000

4-109
User software should not write 1s to these unlisted loca- SPI Registers Control and status bits for the Serial Periph-
tions, since they may be used in future products to invoke eral Interface are contained in registers SPCR (shown in
new features. In that case, the reset or inactive values of the Table 4) and SPSR (shown in Table 5). The SPI data bits
new bits will always be 0. are contained in the SPDR register. Writing the SPI data
Timer 2 Registers Control and status bits are contained in register during serial data transfer sets the Write Collision
registers T2CON (shown in Table 2) and T2MOD (shown in bit, WCOL, in the SPSR register. The SPDR is double buff-
Table 9) for Timer 2. The register pair (RCAP2H, RCAP2L) ered for writing and the values in SPDR are not changed by
are the Capture/Reload registers for Timer 2 in 16 bit cap- Reset.
ture mode or 16-bit auto-reload mode. Interrupt Registers The global interrupt enable bit and the
Watchdog and Memory Control Register The WMCON individual interrupt enable bits are in the IE register. In addi-
register contains control bits for the Watchdog Timer tion, the individual interrupt enable bit for the SPI is in the
(shown in Table 3). The EEMEN and EEMWE bits are used SPCR register. Two priorities can be set for each of the six
to select the 2K bytes on-chip EEPROM, and to enable interrupt sources in the IP register.
byte-write. The DPS bit selects one of two DPTR registers
available.

Table 2. T2CON—Timer/Counter 2 Control Register

T2CON Address = 0C8H Reset Value = 0000 0000B
Bit Addressable
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2
Bit 7 6 5 4 3 2 1 0

Symbol Function
TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either
RCLK = 1 or TCLK = 1.
EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3. RCLK = 0 causes Timer 1 overflows to be used for the receive clock.
TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port
Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if
Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2 Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).
CP/RL2 Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When
either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

4-110 AT89S8252
 AT89S8252

Dual Data Pointer Registers To facilitate accessing both appropriate value before accessing the respective Data
internal EEPROM and external data memory, two banks of Pointer Register.
16 bit Data Pointer Registers are provided: DP0 at SFR Power Off Flag The Power Off Flag (POF) is located at
address locations 82H-83H and DP1 at 84H-85H. Bit DPS bit_4 (PCON.4) in the PCON SFR. POF is set to “1” during
= 0 in SFR WMCON selects DP0 and DPS = 1 selects power up. It can be set and reset under software control
DP1. The user should always initialize the DPS bit to the and is not affected by RESET.

Table 3. WMCON—Watchdog and Memory Control Register

WMCON Address = 96H Reset Value = 0000 0010B

PS2 PS1 PS0 EEMWE EEMEN DPS WDTRST WDTEN

Bit 7 6 5 4 3 2 1 0

Symbol Function
PS2 Prescaler Bits for the Watchdog Timer. When all three bits are set to “0”, the watchdog timer has a nominal period of 16
PS1 ms. When all three bits are set to “1”, the nominal period is 2048 ms.
PS0
EEMWE EEPROM Data Memory Write Enable Bit. Set this bit to “1” before initiating byte write to on-chip EEPROM with the
MOVX instruction. User software should set this bit to “0” after EEPROM write is completed.
EEMEN Internal EEPROM Access Enable. When EEMEN = 1, the MOVX instruction with DPTR will access on-chip EEPROM
instead of external data memory. When EEMEN = 0, MOVX with DPTR accesses external data memory.
DPS Data Pointer Register Select. DPS = 0 selects the first bank of Data Pointer Register, DP0, and DPS = 1 selects the
second bank, DP1
WDTRST Watchdog Timer Reset and EEPROM Ready/Busy Flag. Each time this bit is set to “1” by user software, a pulse is
RDY/BSY generated to reset the watchdog timer. The WDTRST bit is then automatically reset to “0” in the next instruction cycle.
The WDTRST bit is Write-Only. This bit also serves as the RDY/BSY flag in a Read-Only mode during EEPROM write.
RDY/BSY = 1 means that the EEPROM is ready to be programmed. While programming operations are being executed,
the RDY/BSY bit equals “0” and is automatically reset to “1” when programming is completed.
WDTEN Watchdog Timer Enable Bit. WDTEN = 1 enables the watchdog timer and WDTEN = 0 disables the watchdog timer.

4-111
Table 4. SPCR—SPI Control Register
SPCR Address = D5H Reset Value = 0000 01XXB

SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0

Bit 7 6 5 4 3 2 1 0

Symbol Function
SPIE SPI Interrupt Enable. This bit, in conjunction with the ES bit in the IE register, enables SPI interrupts: SPIE = 1 and ES
= 1 enable SPI interrupts. SPIE = 0 disables SPI interrupts.
SPE SPI Enable. SPI = 1 enables the SPI channel and connects SS, MOSI, MISO and SCK to pins P1.4, P1.5, P1.6, and
P1.7. SPI = 0 disables the SPI channel.
DORD Data Order. DORD = 1 selects LSB first data transmission. DORD = 0 selects MSB first data transmission.
MSTR Master/Slave Select. MSTR = 1 selects Master SPI mode. MSTR = 0 selects Slave SPI mode.
CPOL Clock Polarity. When CPOL = 1, SCK is high when idle. When CPOL = 0, SCK of the master device is low when not
transmitting. Please refer to figure on SPI Clock Phase and Polarity Control.
CPHA Clock Phase. The CPHA bit together with the CPOL bit controls the clock and data relationship between master and
slave. Please refer to figure on SPI Clock Phase and Polarity Control.
SPR0 SPI Clock Rate Select. These two bits control the SCK rate of the device configured as master. SPR1 and SPR0 have
SPR1 no effect on the slave. The relationship between SCK and the oscillator frequency, FOSC., is as follows:
SPR1 SPR0 SCK = FOSC. divided by
0 0 4
0 1 16
1 0 64
1 1 128

Table 5. SPSR—SPI Status Register

SPSR Address = AAH Reset Value = 00XX XXXXB

SPIF WCOL — — — — — —
Bit 7 6 5 4 3 2 1 0

Symbol Function
SPIF SPI Interrupt Flag. When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if SPIE = 1 and
ES = 1. The SPIF bit is cleared by reading the SPI status register with SPIF and WCOL bits set, and then accessing
the SPI data register.
WCOL Write Collision Flag. The WCOL bit is set if the SPI data register is written during a data transfer. During data transfer,
the result of reading the SPDR register may be incorrect, and writing to it has no effect. The WCOL bit (and the SPIF
bit) are cleared by reading the SPI status register with SPIF and WCOL set, and then accessing the SPI data register.

4-112 AT89S8252
 AT89S8252

Table 6. SPDR—SPI Data Register

SPDR Address = 86H Reset Value = unchanged

SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0

Bit 7 6 5 4 3 2 1 0

Data Memory—EEPROM and RAM Programmable Watchdog Timer

The AT89S8252 implements 2K bytes of on-chip EEPROM The programmable Watchdog Timer (WDT) operates from
for data storage and 256 bytes of RAM. The upper 128 an independent oscillator. The prescaler bits, PS0, PS1
bytes of RAM occupy a parallel space to the Special Func- and PS2 in SFR WMCON are used to set the period of the
tion Registers. That means the upper 128 bytes have the Watchdog Timer from 16 ms to 2048 ms. The available
same addresses as the SFR space but are physically sepa- timer periods are shown in the following table and the
rate from SFR space. actual timer periods (at VCC = 5V) are within ±30% of the
When an instruction accesses an internal location above nominal.
address 7FH, the address mode used in the instruction The WDT is disabled by Power-on Reset and during Power
specifies whether the CPU accesses the upper 128 bytes Down. It is enabled by setting the WDTEN bit in SFR
of RAM or the SFR space. Instructions that use direct WMCON (address = 96H). The WDT is reset by setting the
addressing access SFR space. WDTRST bit in WMCON. When the WDT times out without
For example, the following direct addressing instruction being reset or disabled, an internal RST pulse is generated
accesses the SFR at location 0A0H (which is P2). to reset the CPU.
MOV 0A0H, #data Table 7. Watchdog Timer Period Selection
Instructions that use indirect addressing access the upper WDT Prescaler Bits Period (nominal)
128 bytes of RAM. For example, the following indirect
addressing instruction, where R0 contains 0A0H, accesses PS2 PS1 PS0
the data byte at address 0A0H, rather than P2 (whose 0 0 0 16 ms
address is 0A0H).
0 0 1 32 ms
MOV @R0, #data
0 1 0 64 ms
Note that stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are avail- 0 1 1 128 ms
able as stack space.
1 0 0 256 ms
The on-chip EEPROM data memory is selected by setting
the EEMEN bit in the WMCON register at SFR address 1 0 1 512 ms
location 96H. The EEPROM address range is from 000H to 1 1 0 1024 ms
7FFH. The MOVX instructions are used to access the
1 1 1 2048 ms
EEPROM. To access off-chip data memory with the MOVX
instructions, the EEMEN bit needs to be set to “0”.
The EEMWE bit in the WMCON register needs to be set to
“1” before any byte location in the EEPROM can be written.
User software should reset EEMWE bit to “0” if no further
EEPROM write is required. EEPROM write cycles in the
serial programming mode are self-timed and typically take
2.5 ms. The progress of EEPROM write can be monitored
by reading the RDY/BSY bit (read-only) in SFR WMCON.
RDY/BSY = 0 means programming is still in progress and
RDY/BSY = 1 means EEPROM write cycle is completed
and another write cycle can be initiated.
In addition, during EEPROM programming, an attempted
read from the EEPROM will fetch the byte being written
with the MSB complemented. Once the write cycle is com-
pleted, true data are valid at all bit locations.

4-113
Timer 0 and 1 Table 8. Timer 2 Operating Modes
Timer 0 and Timer 1 in the AT89S8252 operate the same RCLK + TCLK CP/RL2 TR2 MODE
way as Timer 0 and Timer 1 in the AT89C51, AT89C52 and
0 0 1 16-bit Auto-Reload
AT89C55. For further information, see the October 1995
Microcontroller Data Book, page 2-45, section titled, 0 1 1 16-bit Capture
“Timer/Counters.” 1 X 1 Baud Rate Generator
X X 0 (Off)
Timer 2
Timer 2 is a 16 bit Timer/Counter that can operate as either Capture Mode
a timer or an event counter. The type of operation is In the capture mode, two options are selected by bit
selected by bit C/T2 in the SFR T2CON (shown in Table 2). EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16 bit timer
Timer 2 has three operating modes: capture, auto-reload or counter which upon overflow sets bit TF2 in T2CON.
(up or down counting), and baud rate generator. The This bit can then be used to generate an interrupt. If
modes are selected by bits in T2CON, as shown in Table 8. EXEN2 = 1, Timer 2 performs the same operation, but a l-
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the to-0 transition at external input T2EX also causes the cur-
Timer function, the TL2 register is incremented every rent value in TH2 and TL2 to be captured into RCAP2H and
machine cycle. Since a machine cycle consists of 12 oscil- RCAP2L, respectively. In addition, the transition at T2EX
lator periods, the count rate is 1/12 of the oscillator fre- causes bit EXF2 in T2CON to be set. The EXF2 bit, like
quency. TF2, can generate an interrupt. The capture mode is illus-
In the Counter function, the register is incremented in trated in Figure 1.
response to a 1-to-0 transition at its corresponding external Auto-Reload (Up or Down Counter)
input pin, T2. In this function, the external input is sampled
Timer 2 can be programmed to count up or down when
during S5P2 of every machine cycle. When the samples
configured in its 16 bit auto-reload mode. This feature is
show a high in one cycle and a low in the next cycle, the
invoked by the DCEN (Down Counter Enable) bit located in
count is incremented. The new count value appears in the
the SFR T2MOD (see Table 9). Upon reset, the DCEN bit
register during S3P1 of the cycle following the one in which
is set to 0 so that timer 2 will default to count up. When
the transition was detected. Since two machine cycles (24
DCEN is set, Timer 2 can count up or down, depending on
oscillator periods) are required to recognize a 1-to-0 transi-
the value of the T2EX pin.
tion, the maximum count rate is 1/24 of the oscillator fre-
quency. To ensure that a given level is sampled at least Figure 2 shows Timer 2 automatically counting up when
once before it changes, the level should be held for at least DCEN = 0. In this mode, two options are selected by bit
one full machine cycle. EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to

Figure 1. Timer 2 in Capture Mode

OSC ÷12
C/T2 = 0

TH2 TL2 TF2

OVERFLOW
CONTROL
TR2
C/T2 = 1

T2 PIN CAPTURE

RCAP2H RCAP2L
TRANSITION
DETECTOR TIMER 2
INTERRUPT
T2EX PIN EXF2

CONTROL
EXEN2

4-114 AT89S8252
 AT89S8252

0FFFFH and then sets the TF2 bit upon overflow. The over- RCAP2H and RCAP2L to be reloaded into the timer regis-
flow also causes the timer registers to be reloaded with the ters, TH2 and TL2, respectively.
16 bit value in RCAP2H and RCAP2L. The values in A logic 0 at T2EX makes Timer 2 count down. The timer
RCAP2H and RCAP2L are preset by software. If EXEN2 = underflows when TH2 and TL2 equal the values stored in
1, a 16 bit reload can be triggered either by an overflow or RCAP2H and RCAP2L. The underflow sets the TF2 bit and
by a 1-to-0 transition at external input T2EX. This transition causes 0FFFFH to be reloaded into the timer registers.
also sets the EXF2 bit. Both the TF2 and EXF2 bits can The EXF2 bit toggles whenever Timer 2 overflows or
generate an interrupt if enabled. underflows and can be used as a 17th bit of resolution. In
Setting the DCEN bit enables Timer 2 to count up or down, this operating mode, EXF2 does not flag an interrupt.
as shown in Figure 3. In this mode, the T2EX pin controls
the direction of the count. A logic 1 at T2EX makes Timer 2
count up. The timer will overflow at 0FFFFH and set the
TF2 bit. This overflow also causes the 16 bit value in

Figure 2. Timer 2 in Auto Reload Mode (DCEN = 0)

Table 9. T2MOD—Timer 2 Mode Control Register

T2MOD Address = 0C9H Reset Value = XXXX XX00B
Not Bit Addressable
— — — — — — T2OE DCEN
Bit 7 6 5 4 3 2 1 0

Symbol Function
— Not implemented, reserved for future use.
T2OE Timer 2 Output Enable bit.
DCEN When set, this bit allows Timer 2 to be configured as an up/down counter.

4-115
Figure 3. Timer 2 Auto Reload Mode (DCEN = 1)

Figure 4. Timer 2 in Baud Rate Generator Mode

TIMER 1 OVERFLOW

÷2
"0" "1"
NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12
SMOD1

OSC ÷2
C/T2 = 0
"1" "0"
TH2 TL2
RCLK
Rx
CONTROL CLOCK
TR2 ÷16
C/T2 = 1
"1" "0"
T2 PIN
TCLK
RCAP2H RCAP2L Tx
CLOCK
TRANSITION
DETECTOR
÷ 16

TIMER 2
T2EX PIN EXF2 INTERRUPT

CONTROL
EXEN2

4-116 AT89S8252
 AT89S8252

Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting
Modes 1 and 3 Oscillator Frequency
TCLK and/or RCLK in T2CON (Table 2). Note that the baud --------------------------------------- = ----------------------------------------------------------------------------------------------
Baud Rate 32 × [ 65536 – ( RCAP2H,RCAP2L ) ]
rates for transmit and receive can be different if Timer 2 is
used for the receiver or transmitter and Timer 1 is used for
the other function. Setting RCLK and/or TCLK puts Timer 2 where (RCAP2H, RCAP2L) is the content of RCAP2H and
into its baud rate generator mode, as shown in Figure 4. RCAP2L taken as a 16 bit unsigned integer.
The baud rate generator mode is similar to the auto-reload Timer 2 as a baud rate generator is shown in Figure 4. This
mode, in that a rollover in TH2 causes the Timer 2 registers figure is valid only if RCLK or TCLK = 1 in T2CON. Note
to be reloaded with the 16 bit value in registers RCAP2H that a rollover in TH2 does not set TF2 and will not gener-
and RCAP2L, which are preset by software. ate an interrupt. Note too, that if EXEN2 is set, a 1-to-0
transition in T2EX will set EXF2 but will not cause a reload
The baud rates in Modes 1 and 3 are determined by Timer
from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer
2’s overflow rate according to the following equation.
2 is in use as a baud rate generator, T2EX can be used as
Timer 2 Overflow Rate an extra external interrupt.
Modes 1 and 3 Baud Rates = ------------------------------------------------------------ Note that when Timer 2 is running (TR2 = 1) as a timer in
16
the baud rate generator mode, TH2 or TL2 should not be
The Timer can be configured for either timer or counter read from or written to. Under these conditions, the Timer is
operation. In most applications, it is configured for timer incremented every state time, and the results of a read or
operation (CP/T2 = 0). The timer operation is different for write may not be accurate. The RCAP2 registers may be
Timer 2 when it is used as a baud rate generator. Normally, read but should not be written to, because a write might
as a timer, it increments every machine cycle (at 1/12 the overlap a reload and cause write and/or reload errors. The
oscillator frequency). As a baud rate generator, however, it timer should be turned off (clear TR2) before accessing the
increments every state time (at 1/2 the oscillator fre- Timer 2 or RCAP2 registers.
quency). The baud rate formula is given below.

Figure 5. Timer 2 in Clock-Out Mode

4-117
Programmable Clock Out UART
A 50% duty cycle clock can be programmed to come out on The UART in the AT89S8252 operates the same way as
P1.0, as shown in Figure 5. This pin, besides being a regu- the UART in the AT89C51, AT89C52 and AT89C55. For
lar I/0 pin, has two alternate functions. It can be pro- further information, see the October 1995 Microcontroller
grammed to input the external clock for Timer/Counter 2 or Data Book, page 2-49, section titled, “Serial Interface.”
to output a 50% duty cycle clock ranging from 61 Hz to 4
MHz at a 16 MHz operating frequency.
To configure the Timer/Counter 2 as a clock generator, bit
Serial Peripheral Interface
C/T2 (T2CON.1) must be cleared and bit T2OE (T2MOD.1) The serial peripheral interface (SPI) allows high-speed syn-
must be set. Bit TR2 (T2CON.2) starts and stops the timer. chronous data transfer between the AT89S8252 and
The clock-out frequency depends on the oscillator fre- peripheral devices or between several AT89S8252
quency and the reload value of Timer 2 capture registers devices. The AT89S8252 SPI features include the follow-
(RCAP2H, RCAP2L), as shown in the following equation. ing:
• Full-Duplex, 3-Wire Synchronous Data Transfer
Oscillator Frequency • Master or Slave Operation
Clock Out Frequency = -------------------------------------------------------------------------------------------
4 × [ 65536 – ( RCAP2H,RCAP2L ) ]
• 1.5-MHz Bit Frequency (max.)
• LSB First or MSB First Data Transfer
In the clock-out mode, Timer 2 rollovers will not generate
an interrupt. This behavior is similar to when Timer 2 is • Four Programmable Bit Rates
used as a baud-rate generator. It is possible to use Timer 2 • End of Transmission Interrupt Flag
as a baud-rate generator and a clock generator simulta- • Write Collision Flag Protection
neously. Note, however, that the baud-rate and clock-out
• Wakeup from Idle Mode (Slave Mode Only)
frequencies cannot be determined independently from one
another since they both use RCAP2H and RCAP2L.

Figure 6. SPI Block Diagram

S MISO
P1.6
OSCILLATOR M
MOSI
M PIN CONTROL LOGIC P1.5
MSB LSB
S
8/16-BIT SHIFT REGISTER
READ DATA BUFFER
DIVIDER
÷4÷16÷64÷128

CLOCK
SPI CLOCK (MASTER) SCK
SELECT CLOCK S 1.7
LOGIC
M
SPR1

SPR0

SS
P1.4
DORD
MSTR
SPE

MSTR
SPE
SPI CONTROL
WCOL

DORD

MSTR

CPHA
CPOL

SPR1
SPR0
SPIE
SPIF

SPE

SPI STATUS REGISTER SPI CONTROL REGISTER

8 8

SPI INTERRUPT INTERNAL

REQUEST DATA BUS

4-118 AT89S8252
 AT89S8252

The interconnection between master and slave CPUs with The Slave Select input, SS/P1.4, is set low to select an
SPI is shown in the following figure. The SCK pin is the individual SPI device as a slave. When SS/P1.4 is set high,
clock output in the master mode but is the clock input in the the SPI port is deactivated and the MOSI/P1.5 pin can be
slave mode. Writing to the SPI data register of the master used as an input.
CPU starts the SPI clock generator, and the data written There are four combinations of SCK phase and polarity
shifts out of the MOSI pin and into the MOSI pin of the with respect to serial data, which are determined by control
slave CPU. After shifting one byte, the SPI clock generator bits CPHA and CPOL. The SPI data transfer formats are
stops, setting the end of transmission flag (SPIF). If both shown in Figures 8 and 9.
the SPI interrupt enable bit (SPIE) and the serial port inter-
rupt enable bit (ES) are set, an interrupt is requested.

Figure 7. SPI Master-Slave Interconnection

MSB MASTER LSB MISO MISO MSB SLAVE LSB
8-BIT SHIFT REGISTER 8-BIT SHIFT REGISTER

MOSI MOSI

SPI SCK SCK

CLOCK GENERATOR SS SS
VCC

Figure 8. SPI transfer Format with CPHA = 0

*Not defined but normally MSB of character just received

4-119
Figure 9. SPI Transfer Format with CPHA = 1
SCK CYCLE # 1 2 3 4 5 6 7 8
(FOR REFERENCE)
SCK (CPOL=0)

SCK (CPOL=1)

MOSI MSB 6 5 4 3 2 1 LSB

(FROM MASTER)
MISO * MSB 6 5 4 3 2 1 LSB
(FROM SLAVE)
SS (TO SLAVE)

*Not defined but normally LSB of previously transmitted character

Interrupts
The AT89S8252 has a total of six interrupt vectors: two Timer 2 interrupt is generated by the logical OR of bits TF2
external interrupts (INT0 and INT1), three timer interrupts and EXF2 in register T2CON. Neither of these flags is
(Timers 0, 1, and 2), and the serial port interrupt. These cleared by hardware when the service routine is vectored
interrupts are all shown in Figure 10. to. In fact, the service routine may have to determine
Each of these interrupt sources can be individually enabled whether it was TF2 or EXF2 that generated the interrupt,
or disabled by setting or clearing a bit in Special Function and that bit will have to be cleared in software.
Register IE. IE also contains a global disable bit, EA, which The Timer 0 and Timer 1 flags, TF0 and TF1, are set at
disables all interrupts at once. S5P2 of the cycle in which the timers overflow. The values
Note that Table 10 shows that bit position IE.6 is unimple- are then polled by the circuitry in the next cycle. However,
mented. In the AT89C51, bit position IE.5 is also unimple- the Timer 2 flag, TF2, is set at S2P2 and is polled in the
mented. User software should not write 1s to these bit posi- same cycle in which the timer overflows.
tions, since they may be used in future AT89 products.

Table 10. Interrupt Enable (IE) Register Figure 10. Interrupt Sources
(MSB) (LSB)

EA — ET2 ES ET1 EX1 ET0 EX0

Enable Bit = 1 enables the interrupt.

Enable Bit = 0 disables the interrupt.

Symbol Position Function

Disables all interrupts. If EA = 0, no interrupt

is acknowledged. If EA = 1, each interrupt
EA IE.7
source is individually enabled or disabled by
setting or clearing its enable bit.

— IE.6 Reserved.

ET2 IE.5 Timer 2 interrupt enable bit.

ES IE.4 SPI and UART interrupt enable bit.

ET1 IE.3 Timer 1 interrupt enable bit.

EX1 IE.2 External interrupt 1 enable bit.

ET0 IE.1 Timer 0 interrupt enable bit.

EX0 IE.0 External interrupt 0 enable bit.

User software should never write 1s to unimplemented bits, because

they may be used in future AT89 products.

4-120 AT89S8252
 AT89S8252

Figure 11. Oscillator Connections Figure 12. External Clock Drive Configuration

Note: Note: C1, C2 = 30 pF ± 10 pF for Crystals

= 40 pF ± 10 pF for Ceramic Resonators

Oscillator Characteristics internal reset algorithm takes control. On-chip hardware

inhibits access to internal RAM in this event, but access to
XTAL1 and XTAL2 are the input and output, respectively,
the port pins is not inhibited. To eliminate the possibility of
of an inverting amplifier that can be configured for use as
an unexpected write to a port pin when idle mode is termi-
an on-chip oscillator, as shown in Figure 11. Either a quartz
nated by a reset, the instruction following the one that
crystal or ceramic resonator may be used. To drive the
invokes idle mode should not write to a port pin or to exter-
device from an external clock source, XTAL2 should be left
nal memory.
unconnected while XTAL1 is driven, as shown in Figure 12.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry Power Down Mode
is through a divide-by-two flip-flop, but minimum and maxi- In the power down mode, the oscillator is stopped and the
mum voltage high and low time specifications must be instruction that invokes power down is the last instruction
observed. executed. The on-chip RAM and Special Function Regis-
ters retain their values until the power down mode is termi-
Idle Mode nated. Exit from power down can be initiated either by a
hardware reset or by an enabled external interrupt. Reset
In idle mode, the CPU puts itself to sleep while all the on-
redefines the SFRs but does not change the on-chip RAM.
chip peripherals remain active. The mode is invoked by
The reset should not be activated before VCC is restored to
software. The content of the on-chip RAM and all the spe-
its normal operating level and must be held active long
cial functions registers remain unchanged during this
enough to allow the oscillator to restart and stabilize.
mode. The idle mode can be terminated by any enabled
interrupt or by a hardware reset. To exit power down via an interrupt, the external interrupt
must be enabled as level sensitive before entering power
Note that when idle mode is terminated by a hardware
down. The interrupt service routine starts at 16 ms (nomi-
reset, the device normally resumes program execution
nal) after the enabled interrupt pin is activated.
from where it left off, up to two machine cycles before the

Status of External Pins During Idle and Power Down Modes

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power Down Internal 0 0 Data Data Data Data
Power Down External 0 0 Float Data Data Data

4-121
Program Memory Lock Bits
The AT89S8252 has three lock bits that can be left unpro- value and holds that value until reset is activated. The
grammed (U) or can be programmed (P) to obtain the addi- latched value of EA must agree with the current logic level
tional features listed in the following table. at that pin in order for the device to function properly.
When lock bit 1 is programmed, the logic level at the EA pin Once programmed, the lock bits can only be unpro-
is sampled and latched during reset. If the device is pow- grammed with the Chip Erase operations in either the par-
ered up without a reset, the latch initializes to a random allel or serial modes.

Lock Bit Protection Modes(1)(2)

Program Lock Bits Protection Type
LB1 LB2 LB3
1 U U U No internal memory lock feature.
2 P U U MOVC instructions executed from external program memory are disabled from fetching code bytes
from internal memory. EA is sampled and latched on reset and further programming of the Flash
memory (parallel or serial mode) is disabled.
3 P P U Same as Mode 2, but parallel or serial verify are also disabled.
4 P P P Same as Mode 3, but external execution is also disabled.

Notes: 1. U = Unprogrammed
2. P = Programmed

Programming the Flash and EEPROM Parallel Programming Algorithm

Atmel’s AT89S8252 Flash Microcontroller offers 8K bytes To program and verify the AT89S8252 in the parallel pro-
of in-system reprogrammable Flash Code memory and 2K gramming mode, the following sequence is recommended:
bytes of EEPROM Data memory. 1. Power-up sequence:
The AT89S8252 is normally shipped with the on-chip Flash Apply power between VCC and GND pins.
Code and EEPROM Data memory arrays in the erased Set RST pin to “H”.
state (i.e. contents = FFH) and ready to be programmed. Apply a 3 MHz to 24 MHz clock to XTAL1 pin and wait
This device supports a High-Voltage (12V) Parallel pro- for at least 10 milliseconds.
gramming mode and a Low-Voltage (5V) Serial program-
2. Set PSEN pin to “L”
ming mode. The serial programming mode provides a con-
venient way to download the AT89S8252 inside the user’s ALE pin to “H”
system. The parallel programming mode is compatible with EA pin to “H” and all other pins to “H”.
conventional third party Flash or EPROM programmers. 3. Apply the appropriate combination of “H” or “L” logic
The Code and Data memory arrays are mapped via sepa- levels to pins P2.6, P2.7, P3.6, P3.7 to select one of the
rate address spaces in the serial programming mode. In programming operations shown in the Flash Program-
the parallel programming mode, the two arrays occupy one ming Modes table.
contiguous address space: 0000H to 1FFFH for the Code 4. Apply the desired byte address to pins P1.0 to P1.7
array and 2000H to 27FFH for the Data array. and P2.0 to P2.5.
The Code and Data memory arrays on the AT89S8252 are Apply data to pins P0.0 to P0.7 for Write Code opera-
programmed byte-by-byte in either programming mode. An tion.
auto-erase cycle is provided with the self-timed program-
5. Raise EA/VPP to 12V to enable Flash programming,
ming operation in the serial programming mode. There is
erase or verification.
no need to perform the Chip Erase operation to reprogram
any memory location in the serial programming mode 6. Pulse ALE/PROG once to program a byte in the Code
unless any of the lock bits have been programmed. memory array, the Data memory array or the lock bits.
The byte-write cycle is self-timed and typically takes
In the parallel programming mode, there is no auto-erase
1.5 ms.
cycle. To reprogram any non-blank byte, the user needs to
use the Chip Erase operation first to erase both arrays. 7. To verify the byte just programmed, bring pin P2.7 to
“L” and read the programmed data at pins P0.0 to P0.7.

4-122 AT89S8252
 AT89S8252

8. Repeat steps 3 through 7 changing the address and Serial Programming Fuse
data for the entire 2K or 8K bytes array or until the end A programmable fuse is available to disable Serial Pro-
of the object file is reached. gramming if the user needs maximum system security. The
9. Power-off sequence: Serial Programming Fuse can only be programmed or
Set XTAL1 to “L”. erased in the Parallel Programming Mode.
Set RST and EA pins to “L”. The AT89S8252 is shipped with the Serial Programming
Mode enabled.
Turn VCC power off.
Reading the Signature Bytes: The signature bytes are
In the parallel programming mode, there is no auto-erase
read by the same procedure as a normal verification of
cycle and to reprogram any non-blank byte, the user needs
locations 030H and 031H, except that P3.6 and P3.7 must
to use the Chip Erase operation first to erase both arrays.
be pulled to a logic low. The values returned are as follows:
DATA Polling (030H) = 1EH indicates manufactured by Atmel
The AT89S8252 features DATA Polling to indicate the end (031H) = 72H indicates 89S8252
of a write cycle. During a write cycle in the parallel or serial
programming mode, an attempted read of the last byte writ-
ten will result in the complement of the written datum on
Programming Interface
P0.7 (parallel mode), and on the MSB of the serial output Every code byte in the Flash and EEPROM arrays can be
byte on MISO (serial mode). Once the write cycle has been written, and the entire array can be erased, by using the
completed, true data are valid on all outputs, and the next appropriate combination of control signals. The write oper-
cycle may begin. DATA Polling may begin any time after a ation cycle is self-timed and once initiated, will automati-
write cycle has been initiated. cally time itself to completion.
All major programming vendors offer worldwide support for
Ready/Busy the Atmel microcontroller series. Please contact your local
The progress of byte programming in the parallel program- programming vendor for the appropriate software revision.
ming mode can also be monitored by the RDY/BSY output
signal. Pin P3.4 is pulled Low after ALE goes High during
programming to indicate BUSY. P3.4 is pulled High again Serial Downloading
when programming is done to indicate READY. Both the Code and Data memory arrays can be pro-
grammed using the serial SPI bus while RST is pulled to
Program Verify VCC. The serial interface consists of pins SCK, MOSI (input)
If lock bits LB1 and LB2 have not been programmed, the and MISO (output). After RST is set high, the Programming
programmed Code or Data byte can be read back via the Enable instruction needs to be executed first before pro-
address and data lines for verification. The state of the lock gram/erase operations can be executed.
bits can also be verified directly in the parallel programming
mode. In the serial programming mode, the state of the lock An auto-erase cycle is built into the self-timed programming
bits can only be verified indirectly by observing that the lock operation (in the serial mode ONLY) and there is no need
to first execute the Chip Erase instruction unless any of the
bit features are enabled.
lock bits have been programmed. The Chip Erase opera-
Chip Erase tion turns the content of every memory location in both the
Both Flash and EEPROM arrays are erased electrically at Code and Data arrays into FFH.
the same time. In the parallel programming mode, chip The Code and Data memory arrays have separate address
erase is initiated by using the proper combination of control spaces:
signals and by holding ALE/PROG low for 10 ms. The 0000H to 1FFFH for Code memory and 000H to 7FFH for
Code and Data arrays are written with all “1”s in the Chip Data memory.
Erase operation.
Either an external system clock is supplied at pin XTAL1 or
In the serial programming mode, a chip erase operation is a crystal needs to be connected across pins XTAL1 and
initiated by issuing the Chip Erase instruction. In this mode, XTAL2. The maximum serial clock (SCK) frequency should
chip erase is self-timed and takes about 16 ms. be less than 1/40 of the crystal frequency. With a 24 MHz
During chip erase, a serial read from any address location oscillator clock, the maximum SCK frequency is 600 kHz.
will return 00H at the data outputs.

4-123
Serial Programming Algorithm written. The write cycle is self-timed and typically takes
To program and verify the AT89S8252 in the serial pro- less than 2.5 ms at 5V.
gramming mode, the following sequence is recommended: 4. Any memory location can be verified by using the Read
1. Power-up sequence: instruction which returns the content at the selected
address at serial output MISO/P1.6.
Apply power between VCC and GND pins.
5. At the end of a programming session, RST can be set
Set RST pin to “H”.
low to commence normal operation.
If a crystal is not connected across pins XTAL1 and
Power-off sequence (if needed):
XTAL2, apply a 3 MHz to 24 MHz clock to XTAL1 pin
and wait for at least 10 milliseconds. Set XTAL1 to “L” (if a crystal is not used).
2. Enable serial programming by sending the Program- Set RST to “L”.
ming Enable serial instruction to pin MOSI/P1.5. The Turn VCC power off.
frequency of the shift clock supplied at pin SCK/P1.7
needs to be less than the CPU clock at XTAL1 divided
Serial Programming Instruction
by 40. The Instruction Set for Serial Programming follows a 3-byte
protocol and is shown in the following table:
3. The Code or Data array is programmed one byte at a
time by supplying the address and data together with
the appropriate Write instruction. The selected memory
location is first automatically erased before new data is

Instruction Set
Instruction Input Format Operation
Byte 1 Byte 2 Byte 3
Programming Enable 1010 1100 0101 0011 xxxx xxxx Enable serial programming interface after RST goes high.
Chip Erase 1010 1100 xxxx x100 xxxx xxxx Chip erase both 8K & 2K memory arrays.
Read Code Memory aaaa a001 low addr xxxx xxxx Read data from Code memory array at the selected address.
The 5 MSBs of the first byte are the high order address bits.
The low order address bits are in the second byte. Data are
available at pin MISO during the third byte.
Write Code Memory aaaa a010 low addr data in Write data to Code memory location at selected address. The
address bits are the 5 MSBs of the first byte together with the
second byte.
Read Data Memory 00aa a101 low addr xxxx xxxx Read data from Data memory array at selected address. Data
are available at pin MISO during the third byte.
Write Data Memory 00aa a110 low addr data in Write data to Data memory location at selected address.
Write Lock Bits 1010 1100 x x111 xxxx xxxx Write lock bits.
LB1
LB2
LB3

Set LB1, LB2 or LB3 = “0” to program lock bits.

Notes: 1. DATA polling is used to indicate the end of a write cycle which typically takes less than 2.5 ms at 5V.
2. “aaaaa” = high order address.
3. “x” = don’t care.

4-124 AT89S8252
 AT89S8252

Flash and EEPROM Parallel Programming Modes

Data I/O Address
Mode RST PSEN ALE/PROG EA/VPP P2.6 P2.7 P3.6 P3.7 P0.7:0 P2.5:0 P1.7:0

Serial Prog. Modes H h(1) h(1) x

(2)
Chip Erase H L 12V H L L L X X

Write (10K bytes) Memory H L 12V L H H H DIN ADDR

Read (10K bytes) Memory H L H 12V L L H H DOUT ADDR

Write Lock Bits: H L 12V H L H L DIN X

Bit - 1 P0.7 = 0 X

Bit - 2 P0.6 = 0 X

Bit - 3 P0.5 = 0 X

Read Lock Bits: H L H 12V H H L L DOUT X

Bit - 1 @P0.2 X

Bit - 2 @P0.1 X

Bit - 3 @P0.0 X

Read Atmel Code H L H 12V L L L L DOUT 30H

Read Device Code H L H 12V L L L L DOUT 31H

Serial Prog. Enable H L (2) 12V L H L H P0.0 = 0 X

Serial Prog. Disable H L (2) 12V L H L H P0.0 = 1 X

Read Serial Prog. Fuse H L H 12V H H L H @P0.0 X

Notes: 1. “h” = weakly pulled “High” internally.

2. Chip Erase and Serial Programming Fuse require a 10-ms PROG pulse. Chip Erase needs to be performed first before
reprogramming any byte with a content other than FFH.
3. P3.4 is pulled Low during programming to indicate RDY/BSY.
4. “X” = don’t care

4-125
Figure 14. Programming the Flash/EEPROM Memory Figure 15. Flash/EEPROM Serial Downloading
+5V +4.0V to 6.0V
AT89S8252 AT89S8252
A0 - A7 VCC VCC
ADDR. P1
0000H/27FFH PGM
P2.0 - P2.5 P0 DATA
A8 - A13
INSTRUCTION
P2.6 INPUT P1.5/MOSI
SEE FLASH ALE PROG P1.6/MISO
P2.7 DATA OUTPUT
PROGRAMMING
MODES TABLE P3.6 CLOCK IN P1.7/SCK
P3.7

XTAL2 EA VPP XTAL2

3-24 MHz 3-24 MHz

XTAL1 RST VIH XTAL1 RST VIH

GND PSEN GND

Figure 16. Verifying the Flash/EEPROM Memory

+5V
AT89S8252
A0 - A7 VCC
ADDR. P1
0000H/27FFH PGM DATA
P2.0 - P2.5 P0 (USE 10K
A8 - A13 PULLUPS)

P2.6
ALE VIH
SEE FLASH P2.7
PROGRAMMING
P3.6
MODES TABLE
P3.7

XTAL2 EA VPP

3-24 MHz

XTAL1 RST VIH

GND PSEN

4-126 AT89S8252
 AT89S8252

Flash Programming and Verification Characteristics-Parallel Mode

TA = 0°C to 70°C, VCC = 5.0V ± 10%

Symbol Parameter Min Max Units

VPP Programming Enable Voltage 11.5 12.5 V
IPP Programming Enable Current 1.0 mA
1/tCLCL Oscillator Frequency 3 24 MHz
tAVGL Address Setup to PROG Low 48tCLCL
tGHAX Address Hold After PROG 48tCLCL
tDVGL Data Setup to PROG Low 48tCLCL
tGHDX Data Hold After PROG 48tCLCL
tEHSH P2.7 (ENABLE) High to VPP 48tCLCL
tSHGL VPP Setup to PROG Low 10 µs
tGLGH PROG Width 1 110 µs
tAVQV Address to Data Valid 48tCLCL
tELQV ENABLE Low to Data Valid 48tCLCL
tEHQZ Data Float After ENABLE 0 48tCLCL
tGHBL PROG High to BUSY Low 1.0 µs
tWC Byte Write Cycle Time 2.0 ms

4-127
Flash/EEPROM Programming and Verification Waveforms - Parallel Mode

Serial Downloading Waveforms

SERIAL CLOCK INPUT
SCK/P1.7
7 6 5 4 3 2 1 0
SERIAL DATA INPUT
MOSI/P1.5 MSB LSB

SERIAL DATA OUTPUT

MISO/P1.6 MSB LSB

4-128 AT89S8252
 AT89S8252
Absolute Maximum Ratings*
Operating Temperature .................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground .....................................-1.0V to +7.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage............................................. 6.6V conditions for extended periods may affect device
reliability.
DC Output Current...................................................... 15.0 mA

DC Characteristics
The values shown in this table are valid for TA = -40°C to 85°C and VCC = 5.0V ± 20%, unless otherwise noted.
Symbol Parameter Condition Min Max Units
VIL Input Low Voltage (Except EA) -0.5 0.2 VCC - 0.1 V
VIL1 Input Low Voltage (EA) -0.5 0.2 VCC - 0.3 V
VIH Input High Voltage (Except XTAL1, RST) 0.2 VCC + 0.9 VCC + 0.5 V
VIH1 Input High Voltage (XTAL1, RST) 0.7 VCC VCC + 0.5 V
Output Low Voltage (1)
VOL IOL = 1.6 mA 0.5 V
(Ports 1,2,3)
Output Low Voltage (1)
VOL1 IOL = 3.2 mA 0.5 V
(Port 0, ALE, PSEN)
IOH = -60 µA, VCC = 5V ± 10% 2.4 V
Output High Voltage
VOH IOH = -25 µA 0.75 VCC V
(Ports 1,2,3, ALE, PSEN)
IOH = -10 µA 0.9 VCC V
IOH = -800 µA, VCC = 5V ± 10% 2.4 V
Output High Voltage
VOH1 IOH = -300 µA 0.75 VCC V
(Port 0 in External Bus Mode)
IOH = -80 µA 0.9 VCC V
IIL Logical 0 Input Current (Ports 1,2,3) VIN = 0.45V -50 µA
ITL Logical 1 to 0 Transition Current (Ports 1,2,3) VIN = 2V, VCC = 5V ± 10% -650 µA
Input Leakage Current
ILI (Port 0, EA) 0.45 < VIN < VCC ±10 µA

RRST Reset Pulldown Resistor 50 300 KΩ

CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF
Active Mode, 12 MHz 25 mA
Power Supply Current
Idle Mode, 12 MHz 6.5 mA
ICC
VCC = 6V 100 µA
Power Down Mode (2)
VCC = 3V 40 µA

Notes: 1. Under steady state (non-transient) conditions, IOL Maximum total IOL for all output pins: 71 mA
must be externally limited as follows: If IOL exceeds the test condition, VOL may exceed the
Maximum IOL per port pin: 10 mA related specification. Pins are not guaranteed to sink
Maximum IOL per 8-bit port: current greater than the listed test conditions.
Port 0: 26 mA 2. Minimum VCC for Power Down is 2V
Ports 1, 2, 3: 15 mA

4-129
AC Characteristics
Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other
outputs = 80 pF.

External Program and Data Memory Characteristics

Variable Oscillator
Symbol Parameter Min Max Units
1/tCLCL Oscillator Frequency 0 24 MHz
tLHLL ALE Pulse Width 2tCLCL - 40 ns
tAVLL Address Valid to ALE Low tCLCL - 13 ns
tLLAX Address Hold After ALE Low tCLCL - 20 ns
tLLIV ALE Low to Valid Instruction In 4tCLCL - 65 ns
tLLPL ALE Low to PSEN Low tCLCL - 13 ns
tPLPH PSEN Pulse Width 3tCLCL - 20 ns
tPLIV PSEN Low to Valid Instruction In 3tCLCL - 45 ns
tPXIX Input Instruction Hold After PSEN 0 ns
tPXIZ Input Instruction Float After PSEN tCLCL - 10 ns
tPXAV PSEN to Address Valid tCLCL - 8 ns
tAVIV Address to Valid Instruction In 5tCLCL - 55 ns
tPLAZ PSEN Low to Address Float 10 ns
tRLRH RD Pulse Width 6tCLCL - 100 ns
tWLWH WR Pulse Width 6tCLCL - 100 ns
tRLDV RD Low to Valid Data In 5tCLCL - 90 ns
tRHDX Data Hold After RD 0 ns
tRHDZ Data Float After RD 2tCLCL - 28 ns
tLLDV ALE Low to Valid Data In 8tCLCL - 150 ns
tAVDV Address to Valid Data In 9tCLCL - 165 ns
tLLWL ALE Low to RD or WR Low 3tCLCL - 50 3tCLCL + 50 ns
tAVWL Address to RD or WR Low 4tCLCL - 75 ns
tQVWX Data Valid to WR Transition tCLCL - 20 ns
tQVWH Data Valid to WR High 7tCLCL - 120 ns
tWHQX Data Hold After WR tCLCL - 20 ns
tRLAZ RD Low to Address Float 0 ns
tWHLH RD or WR High to ALE High tCLCL - 20 tCLCL + 25 ns

4-130 AT89S8252
 AT89S8252

External Program Memory Read Cycle

External Data Memory Read Cycle

4-131
External Data Memory Write Cycle

External Clock Drive Waveforms

External Clock Drive

Symbol Parameter VCC = 4.0V to 6.0V Units
Min Max
1/tCLCL Oscillator Frequency 0 24 MHz
tCLCL Clock Period 41.6 ns
tCHCX High Time 15 ns
tCLCX Low Time 15 ns
tCLCH Rise Time 20 ns
tCHCL Fall Time 20 ns

4-132 AT89S8252
 AT89S8252

Serial Port Timing: Shift Register Mode Test Conditions

The values in this table are valid for VCC = 4.0V to 6V and Load Capacitance = 80 pF.
Symbol Parameter Variable Oscillator Units
Min Max
tXLXL Serial Port Clock Cycle Time 12tCLCL µs
tQVXH Output Data Setup to Clock Rising Edge 10tCLCL - 133 ns
tXHQX Output Data Hold After Clock Rising Edge 2tCLCL - 117 ns
tXHDX Input Data Hold After Clock Rising Edge 0 ns
tXHDV Clock Rising Edge to Input Data Valid 10tCLCL - 133 ns

Shift Register Mode Timing Waveforms

AC Testing Input/Output Waveforms(1) Float Waveforms(1)

Notes: 1. AC Inputs during testing are driven at V CC - 0.5V Notes: 1. For timing purposes, a port pin is no longer floating
for a logic 1 and 0.45V for a logic 0. Timing mea- when a 100 mV change from load voltage occurs. A
surements are made at VIH min. for a logic 1 and VIL port pin begins to float when a 100 mV change from
max. for a logic 0. the loaded VOH/VOL level occurs.

4-133
 AT89S8252
TYPICAL ICC (ACTIVE) at 25°C
24
VCC = 6.0V
20
I
C 16
C VCC = 5.0V
12
m
A 8
4
0
0 4 8 12 16 20 24
F (MHz)

AT89S8252
TYPICAL ICC (IDLE) at 25°C
4.8
VCC = 6.0V
4.0
I
C 3.2
C 2.4 VCC = 5.0V

m 1.6
A
0.8
0.0
0 4 8 12 16 20 24
F (MHz)

Notes: 1. XTAL1 tied to GND for Icc (power down)

2. Lock bits programmed

4-134 AT89S8252
 AT89S8252

Ordering Information
Speed Power
(MHz) Supply Ordering Code Package Operation Range
16 4.0V to 6.0V AT89S8252-16AA 44A Automotive
AT89S8252-16JA 44J (-40°C to 105°C)
AT89S8252-16PA 40P6
AT89S8252-16QA 44Q
24 4.0V to 6.0V AT89S8252-24AC 44A Commercial
AT89S8252-24JC 44J (0°C to 70°C)
AT89S8252-24PC 40P6
AT89S8252-24QC 44Q
4.0V to 6.0V AT89S8252-24AI 44A Industrial
AT89S8252-24JI 44J (-40°C to 85°C)
AT89S8252-24PI 40P6
AT89S8252-24QI 44Q
33 4.5V to 5.5V AT89S8252-33AC 44A Commercial
AT89S8252-33JC 44J (0°C to 70°C)
AT89S8252-33PC 40P6
AT89S8252-33QC 44Q

= Preliminary Information

Package Type
44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC)
40P6 40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)
44Q 44 Lead, Plastic Gull Wing Quad Flatpack (PQFP)

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