System Level Test

March 4 - 7, 2018
Hilton Phoenix / Mesa Hotel

Mesa, Arizona
© 2018 BiTS Workshop – Image: pilgrims49 / iStock

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Session 3A Presentation 2
BiTS 2018 Really? - System Level Test
Key Drivers for SLT

(System Level Test)
Karthik Ranganathan
Astronics Test Systems
Conference Ready
BiTS Workshop
mm/dd/2014
March 4 - 7, 2018
Burn-in & Test Strategies Workshop www.bitsworkshop.org March 4-7, 2018

Agenda
• What is System-Level Test (SLT)?
• How is SLT done today?
• What are the trends driving need for more SLT?
• What are the key challenges and opportunities?
Key Drivers for SLT (System Level Test) 2

What is System-Level Test (SLT)?

• Application-specific functional tests that are performed
– on an IC Device Under Test (DUT)
– which is temporarily placed in a socket while SLT tests are applied
– to help “guarantee” that a device will meet its targeted specs and
performance goals when it is ultimately used in the final system.
• System includes both hardware and software
– Hardware – Device Under Test (DUT), sockets, application boards, power supplies, etc.
– Software – firmware, device drivers, operating systems, applications, etc.
System-Level Test ensures that the device is tested similar to the end user experience

What is System-Level Test (SLT)?

• 2 perspectives … component vs system
– Component perspective - does the device meet its specs?
– System perspective – does the “system” work when all the DUTs are
combined with software at the board level?
System-Level Test ensures that the device is tested similar to the end user experience

How is System-Level Test Done Today?

A Brief History of Time…
System Level
• Functional Test used to be the way to go
Test
– then designs started to get more complex
• Structural Test emerged; improved fault coverage 100%
Test
– device complexity continued to increase, quality became Coverage
important as well (hardware & software working together)
• System-Level Test is emerging to insure optimal Structural Functional
Test Test
performance of the integrated system
– but how do we afford it? Mesh of SLT, structural and
functional test leads to
maximum test coverage


Key Considerations
“How much SLT” is determined by: Component
– “Component” or “System” perspective not
Cost of Test or System
Escapes? Perspective?
covered by ATE
– Importance of hardware and software interactions
– Volume, Market segment, Product Life Time Quality
Requirements
– Product Quality and Reliability Requirements
– Thermal Requirements
– Time-to-Market (TTM), Time-To-Volume (TTV), Time-To-Profit (TTP)
– Cost of test escapes
SLT Testing
– End Market Requirements (i.e., safety)


Other Considerations for SLT
– Test Time: seconds, minutes, hours
Component
– Purpose: for TTM, qualification, production Cost of Test
Escapes?
or System
Perspective?
– Tester:
• “SLT on ATE”
• “SLT specialized equipment” Quality
Requirements
• “SLT Massively Parallel”
SLT Testing


Examples of equipment used today
Cost per DUT
SLT on custom
hardware
SLT on ATE
Low Parallel SLT
Massively Parallel SLT

Volume
Increasing SLT Unit Volume

Agenda
• What is System-Level Test (SLT)?
• How is SLT done today?
• What are the trends driving need for more SLT?
• What are the key challenges and opportunities?

What drives increasing need for more SLT?

Drive for Concurrent
higher Scenario
yield Testing
Guardband
Risk of PVT
Escape Stack &
untested Corner
costs Yield
transistors Explosion
Overkill
Business Technical
Drivers Drivers
People’s
lives New Node
Packaging Shrink at
depend Packaging Speed
/ 2.5 & 3D
on our Risk Coverage
product
Faster
Voltage
TTM and
Frequency
TTV
Scaling
ramps

Lower technology nodes dramatically increase

number of untested transistors
Moore’s Law doubles transistor count every technology node
# of Untested Transistors increasing:
At 99.5% coverage (static ATPG) At 85% coverage (at speed ATPG)
Millions untested (10 nm) Billions untested (10 nm)

Concurrent Scenario Testing: real-world scenarios
Consumer DUT Automotive Infotainment DUT Medical Pacemaker DUT
Production ATE: Replicating real world scenarios: MONTHS

System-Level Test: Replicating real world scenarios: MINUTES
How to generate test patterns for these scenarios without significant overkill?

Guard Band Stack and Yield Overkill

• Definitions
– Guard Band added margin for
VDD
worst case / ATE test
– Headroom = VDD (Supply Voltage)
/ CMOS threshold (turn on voltage
Process Node
Source: Samsung
SLT can help reduce the “fear of throwing away good parts” that comes with lower nodes

Guard Band Stack and Yield Overkill

With lower nodes, Guard Band becomes a higher percentage of VDD, “eating into the headroom”
Technology 100 mV CMOS Headroom 100mV

Vdd
Node Guardband as a Threshold Vdd- Threshold Guardband as
(V)
(nm) % of Vdd (V) (V) % of headroom
90 1.4 7.1% 0.5 0.9 11.1%
65 1.2 8.3% 0.5 0.7 14.3%
45 1.1 9.1% 0.5 0.6 16.7%
28 1 10.0% 0.5 0.5 20.0%
20 0.9 11.1% 0.45 0.45 22.2%
14 0.8 12.5% 0.4 0.4 25.0%
10 0.7 14.3% 0.4 0.3 33.3%
Assume: 100mV Guard Band (could also be ~100MHz Guard Band)
SLT can help reduce the “fear of throwing away good parts” that comes with lower nodes

DVFS Explosion + PVT Corners

• Dynamic Voltage Frequency
Scaling (DVFS)
– Ensures the DUT works at different Nominal
power conditions by simulation and Mode
Frequency
testing of each power situation
Hi-speed
• Process Voltage Temperature Mode
(PVT) Corners Sleep
– Addresses process and temperature Mode
variations with simulation and testing
Voltage
Without SLT, it is difficult if not impossible to test all scenarios!

DVFS Explosion + PVT Corners

Designers lack time to compensate for Significant Increase in PVT Corners
the DVFS and PVT Corner Explosion: 200
there isn’t enough test time to run all
the patterns!
100
SLT offers the advantages of

0
booting and running the DUT
natively in different voltage modes,
simulating end user experience Process Node
Source: Mentor
Without SLT, it is difficult if not impossible to test all scenarios!

Conventional Test Methods No Longer Catch Fails

3D process geometries are driving
new defect types that aren’t covered
by static ATPG*, at speed ATPG
(TDF**), and other test methods
FinFET Cross Section
IPs from different vendors: coverage Source: Cadence
was easier with one IP.
High speed, bidirectional interfaces
have faster read/write turnaround times
than the latency of ATE
SiP Module Cross Section
Source: ASE Group
*ATPG – Automatic test pattern generation for structural test
System-Level Test screens for these fail mechanisms

Challenges and Opportunities

Challenges Opportunities
• Lack of fault coverage metric to assess • More systematic approaches to create
SLT effectiveness “commonality”
• Complex nature of System-Level Test • Ecosystem of standards, tools, and
Failures makes it difficult to diagnose root equipment for efficient SLT flow
cause of failures • Close the loop with Data Analytics
• SLT Equipment Challenges
– No “one size fits all”
– Correlation between SLT and ATE
– Cost to add SLT
Being Addressed
– Limited throughput with Massively
– Large form factors Parallel SLT

Summary: Why is more SLT needed?

 We need higher yield! More SLT
 My customers demand quality! • Marginal defects • Concurrent Scenarios
• PVT Corners • Guard Band Overkill
 My new 3D packaging prevents
• Mission Test • High Speed Buses
using certain test modes
• Complexity
 Our TTM and TTV ramps are fast
but our test pattern generation is slow Less SLT
 People’s lives depend on us! • Cost of SLT
• Lower quality
targets

Reference
For additional information about SLT,
please see our whitepaper at:
https://www.astronics.com/test-systems/whitepaper-system-level-
testing-for-semiconductors

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March 4 - 7, 2018

Hilton Phoenix / Mesa Hotel

© 2018 BiTS Workshop – Image: pilgrims49 / iStock

There is NO copyright protection claimed on the presentation/poster content by BiTS

Key Drivers for SLT

Burn-in & Test Strategies Workshop www.bitsworkshop.org March 4-7, 2018

Key Drivers for SLT (System Level Test) 2

Burn-in & Test Strategies Workshop www.bitsworkshop.org March 4-7, 2018

What is System-Level Test (SLT)?

Key Drivers for SLT (System Level Test) 3

Burn-in & Test Strategies Workshop www.bitsworkshop.org March 4-7, 2018

What is System-Level Test (SLT)?

Key Drivers for SLT (System Level Test) 4

Burn-in & Test Strategies Workshop www.bitsworkshop.org March 4-7, 2018

How is System-Level Test Done Today?

Key Drivers for SLT (System Level Test) 5

Burn-in & Test Strategies Workshop www.bitsworkshop.org March 4-7, 2018

How is System-Level Test Done Today?

Key Drivers for SLT (System Level Test) 6

Burn-in & Test Strategies Workshop www.bitsworkshop.org March 4-7, 2018

How is System-Level Test Done Today?

Key Drivers for SLT (System Level Test) 7

Burn-in & Test Strategies Workshop www.bitsworkshop.org March 4-7, 2018

How is System-Level Test Done Today?

Low Parallel SLT

Massively Parallel SLT

Increasing SLT Unit Volume

Key Drivers for SLT (System Level Test) 8

Burn-in & Test Strategies Workshop www.bitsworkshop.org March 4-7, 2018

Key Drivers for SLT (System Level Test) 9

Burn-in & Test Strategies Workshop www.bitsworkshop.org March 4-7, 2018

What drives increasing need for more SLT?

Key Drivers for SLT (System Level Test) 10

Burn-in & Test Strategies Workshop www.bitsworkshop.org March 4-7, 2018

Lower technology nodes dramatically increase

Key Drivers for SLT (System Level Test) 11

Burn-in & Test Strategies Workshop www.bitsworkshop.org March 4-7, 2018

Concurrent Scenario Testing: real-world scenarios

Consumer DUT Automotive Infotainment DUT Medical Pacemaker DUT

Production ATE: Replicating real world scenarios: MONTHS

Key Drivers for SLT (System Level Test) 12

Burn-in & Test Strategies Workshop www.bitsworkshop.org March 4-7, 2018

Guard Band Stack and Yield Overkill

Key Drivers for SLT (System Level Test) 13

Burn-in & Test Strategies Workshop www.bitsworkshop.org March 4-7, 2018

Guard Band Stack and Yield Overkill

Technology 100 mV CMOS Headroom 100mV

Key Drivers for SLT (System Level Test) 14

Burn-in & Test Strategies Workshop www.bitsworkshop.org March 4-7, 2018

DVFS Explosion + PVT Corners

Without SLT, it is difficult if not impossible to test all scenarios!

Key Drivers for SLT (System Level Test) 15

Burn-in & Test Strategies Workshop www.bitsworkshop.org March 4-7, 2018

DVFS Explosion + PVT Corners

SLT offers the advantages of

Without SLT, it is difficult if not impossible to test all scenarios!

Key Drivers for SLT (System Level Test) 16

Burn-in & Test Strategies Workshop www.bitsworkshop.org March 4-7, 2018

Conventional Test Methods No Longer Catch Fails