Synopsys Design Flow

Physical Synthesis (IC Compiler II)

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
1
Physical Synthesis
(IC Compiler II)

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
2
Input and Output Files of IC Compiler II
Netlist
(.v, .ddc)

Cell Library Verilog

(.db) (.v)

TluPlus,
.map GDSII
IC Compiler II (.gds)
Tech file
.tf
Standard
Milkyway Ref Parasitics
library (ICC) Exchange
Format
(.spef)
NDM (ICC II)

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
3
IC Compiler II Design Flow
Invoke ICC II

Data preparation

Floorplanning

Power planning

Placement

Clock Tree Synthesis

Routing

Finishing

Results (.v, .gds, .spef)

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
4
NDM Library Creation
◼ To create the NDM design library, Choose File > Create Library

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
5
Setup Logic Libraries
◼ Choose File > Setup Library

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
6
TluPlus Setup
◼ Choose View > Map > Rail Parasitics

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
7
Design Importing
◼ Choose Task > Create Design > Create Design Library

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
8
Design Importing (2)

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
9
Floorplanning
◼ For floorplanning the design choose Task > Design Planning >
Floorplan Initilization

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
10
Floorplanning (2)

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
11
Power Straps
◼ Choose Task > Design Planning > Create PG

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
12
Core Placement and Optimization
Dialog Box
◼ To run placement, choose Placement > Core Placement and
Optimization Task > Placement > Placement > Create Placement

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
13
FP Placement

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
14
Script FRAGMENT for Placement

◼ Place_opt
❑ -list_only

❑ -from startStage

❑ -to endStage

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
15
 Clock Tree Synthesize
◼ To perform clock tree synthesis choose Task > Clock tree > Chack Clock Trees

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
16
Clock Tree Synthesis

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
17
Command of CTS
◼ clock_opt
❑ -only_psyn
❑ -fix_hold_all_clocks
❑ -inter_clock_balance
❑ -update_clock_latency
❑ -operating_condition
❑ -only_cts
❑ -optimize_dft
❑ -no_clock_route
❑ -only_hold_time
❑ -area_recovery
❑ -size_only
❑ -in_place_size_only
❑ -power

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
18
Preroute Standard Cells
◼ From Menu bar choose Task > Routing> Create Routing Blockage

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
19
After Prerouting

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
20
Routing from the GUI
◼ Choose Route > Core Routing and Optimization

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
21
Routing Dialog Box

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
22
Command for Routing (2)

◼ route_auto
❑ -max_detail_route_iterations num
❑ -reuse_existing_global_route true | false
❑ -route_nondefault_nets_first true | false
❑ -stop_after_track_assignment true | false
❑ -save_after_global_route true | false
❑ -save_after_track_assignment true | false
❑ -save_after_detail_route true | false
❑ -save_cell_prefix name

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
23
DRC (Design Rule Checking) Box
◼ To check DRC errors, choose Verification > Signoff DRC

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
24
LVS (Layout-Versus-Schematic) Box
◼ To check LVS errors, choose Verification > LVS

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
25
Write Verilog Format Box
◼ Choose Task > Design Planning > Write Floorplan & Verilog > Verilog

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
26
Write .spef Format Box
Choose File > Export > Write Parasitics

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
27
Write .gds Format Box

Synopsys University Courseware

Copyright © 2019 Synopsys, Inc. All rights reserved.
Synopsys Design Flow Tutorial
Lecture - 4
Developed By: Vazgen Melikyan
28