HDL Lecture6

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Professor: Sci.D., Professor

Vazgen Melikyan
Synopsys University Courseware

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Hardware Description Languages
Lecture - 6
1 Developed By: Vazgen Melikyan
Course Overview
 The Role and Classification of HDLs

 1 lecture
 System Verilog
 2 lectures
 SystemC
 3 lectures
 Verilog
 4 lectures
 VHDL
 3 lectures
 Process of Synthesis
 2 lectures

Lecture - 6
Developed By: Vazgen Melikyan
2
Process of Synthesis

Lecture - 6
3 Developed By: Vazgen Melikyan
Process of Synthesis

Lecture - 6
4
Steps of Synthesis
Technology independent
synthesis
Steps of synthesis
Technology dependent
synthesis

Lecture - 6
5
Not Synthesisable Operators
:=== or !==
**
Not synthesisable
operators `time scale and `reset all
directives
assign statement in always

block
Assign values to same

parameter in different
always blocks

Lecture - 6
6
Optimization Methods in Design
Compiler
High level optimization
Method of optimization in DC Logic level optimization
Gate level optimization

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7
High Level Optimization
Resource sharing
Arithmetical optimization
High level optimization
Implementation selection
Operator reordering

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8
Resource Sharing
if(sel==2’b00) y=a+b;
else if(sel==2’b01)
y=c+d;
else if(sel==2’b10)
y=e+f; a 00
c 01
else y=g+h; e 10
.... g 11
sel + y
b 00
d 01
f 10
h 11

Lecture - 6
9
Arithmetical Optimization
 Z1= A+B+C Z2= C+D+B
A
+ B
B
+ Z1 +
C C
+ Z1
A
C
+
D
+ Z2
+ Z2
D
B

Lecture - 6
10
Implementation Selection
Booth multiplier
Walles Tree multiplier
Possible implementations of
Carry-Ripple Adder
operators
Carry Look-Ahead Adder
others

Lecture - 6
11
Operator Reordering
Y=a*b+e+f+g a 
b
+
e +
f + y
g
е
+
f +
g
+ y
a 
b

Lecture - 6
12
Gate Level Optimization

Lecture - 6
13
Inputs and Output of Logic
Synthesis Tool (DC)
.V, .VHDL .db .sdc
DESIGN COMPILER
.v, .ddc, .spef

Lecture - 6
14
Behavioral Verilog Code of EFF
module E_ff(q, data, enable, reset,

clock);
output q;
input data, enable, reset, clock;
reg q;
always @(posedge clock) // whenever the
clock makes a transition to 1
if (reset == 0)
q = 1'b0;
else if (enable==1)
q = data;
else q = q
endmodule

Lecture - 6
15
Synthesized Design View of EFF
from DC

Lecture - 6
16
Gate Level Verilog from DC
module E_ff ( q, data, enable, reset, clock );

input data, enable, reset, clock;
output q;
wire n5, n6;
DFFX1 q_reg ( .D(n5), .CLK(clock), .Q(q) );

AND2X1 U5 ( .IN1(n6), .IN2(reset), .Q(n5) );
MUX21X1 U6 ( .IN1(q), .IN2(data), .S(enable), .Q(n6) );
endmodule

Lecture - 6
17
Full Subtractor
1. A full subtractor has three 1-bit inputs x, y and z (previous borrow) and two
1-bit outputs D (difference) and B (borrow)
2. The logic equations for D and B are as follows:
Select Signal Function
D = x’*y’*z + x’*y*z’ + x*y’*z’ + x*y*z
3’b000 out = a
B = x’*y + x’*z + y*z
3’b001 out = a + b
module subtractor (x, y, z, B, D); 3’b010 out = a – b

input x, y, z;
3’b011 out = a/b
output B, D;
3’b100 out = a % b (remainder)
assign B = !x && !y && z || !x &&
y && !z || x && !y && !z || x && y 3’b101 out = a << 1
&& z;
3’b110 out = a >> 1
assign D = !x && y || !x &&z ||
y&&z; 3’b111 out = (a > b) (magnitude
compare)
endmodule

Lecture - 6
18
Testbench for Subtractor
module stimulus; initial

reg x, y, z; begin
wire B, D; #10 x=0; y = 0; z = 0;
#10 x=0; y = 0; z = 1;
subtractor b1 (x, y, z, B, D);
#10 x=0; y = 1; z = 0;
initial
#10 x=0; y = 1; z = 1;
begin #10 x=1; y = 0; z = 0;
$monitor ($time, "x=%b y=%b z= #10 x=1; y = 0; z = 1;
%b B=%b D=%b",x,y,z,B,D); #10 x=1; y = 1; z = 0;
end #10 x=1; y = 1; z = 1;
end
endmodule

Lecture - 6
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Simulation Results for Subtractor

Lecture - 6
20
Magnitude Comparator
module magnitude_comparator(A, B, A_gt_B, A_lt_B, A_eq_B);

input [3:0] A, B;
output A_gt_B, A_lt_B, A_eq_B;
wire [3:0] x;
assign x[0] = A[0] && B[0] || !A[0] && !B[0],

x[1] = A[1] && B[1] || !A[1] && !B[1],
x[2] = A[2] && B[2] || !A[2] && !B[2],
x[3] = A[3] && B[3] || !A[3] && !B[3],
A_gt_B = A[3]&&!B[3] || x[3]&&A[2]&& !B[2] ||
x[3]&&x[2]&&A[1]&& !B[1] || x[3] && x[2] && x[1] && A[1] && !
B[0],
A_lt_B = !A[3]&&B[3] || x[3] && !A[2] && B[2] || x[3] && x[2]
&& !A[1] && B[1] || x[3] && x[2] && x[1] && !A[0] && B[0],
A_eq_B = x[3] && x[2] && x[1] && x[0];
endmodule

Lecture - 6
21
Testbench for Magnitude
Comparator
module fixture;
reg [3:0] A, B;
wire A_gt_B, A_lt_B, A_eq_B;
magnitude_comparator b1 (A, B, A_gt_B, A_lt_B,

A_eq_B);
initial
begin
$monitor ($time, "A=%d B=%d A_gt_B=%b A_lt_B=%b
A_eq_B=%b", A, B, A_gt_B, A_lt_B, A_eq_B);
end
initial
begin
#10 A = 3; B = 5;
#10 A = 0; B = 2;
#10 A = 9; B = 0;
#10 A = 7; B = 7;
end
endmodule

Lecture - 6
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Simulation Results for Magnitude
Comparator

Lecture - 6
23
ALU
 Using a case statement design an 8-function ALU that takes 4-bit inputs a and b and a 3-bit input
signal select, and gives a 5-bit output out. The ALU implements the following functions based on
a 3-bit input signal select. Ignore any overflow or underflow bits.
module alu (a, b, select, out);
Select Signal Function
input [3:0] a, b;
input [2:0] select; 3’b000 out = a
output [4:0] out;
reg [4:0] out; 3’b001 out = a + b
always @(select or a or b)
begin 3’b010 out = a – b
case (select)
3'b000 : out = a; 3’b011 out = a/b
3'b001 : out = a + b;
3'b010 : out = a - b; 3’b100 out = a % b
3'b011 : out = a/b; (remainder)
3'b100 : out = a % b;
3'b101 : out = a <<1; 3’b101 out = a << 1
3'b110 : out = a >>1;
3'b111 : out = (a > b); 3’b110 out = a >> 1
default : out = 5'bxxxxx;
endcase 3’b111 out = (a > b)
end (magnitude
endmodule compare)

Lecture - 6
24
Testbench for ALU
module stimulus; initial

reg [3:0] a,b; begin
#10 select=3'b000;
reg [2:0] select;
#10 select=3'b001;
wire [4:0] out;
#10 select=3'b010;
alu alu_test (a, b, select, out); #10 select=3'b011;
Initial #10 select=3'b100;
begin a=4'b1001; b=4'b1101; end #10 select=3'b101;
#10 select=3'b110;
#10 select=3'b111;
end
endmodule

Lecture - 6
25
Simulation Results for ALU

Lecture - 6
26
Lecture - 6
27

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Hardware Description

Professor: Sci.D., Professor

Synopsys University Courseware

 The Role and Classification of HDLs

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

Synopsys University Courseware

assign statement in always

Assign values to same

Synopsys University Courseware

High level optimization

Method of optimization in DC Logic level optimization

Gate level optimization

Synopsys University Courseware

High level optimization

Synopsys University Courseware

Synopsys University Courseware

 Z1= A+B+C Z2= C+D+B

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Walles Tree multiplier

Carry Look-Ahead Adder

Synopsys University Courseware

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Synopsys University Courseware

.V, .VHDL .db .sdc

.v, .ddc, .spef

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module E_ff(q, data, enable, reset,

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module E_ff ( q, data, enable, reset, clock );

DFFX1 q_reg ( .D(n5), .CLK(clock), .Q(q) );

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module subtractor (x, y, z, B, D); 3’b010 out = a – b

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module stimulus; initial

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module magnitude_comparator(A, B, A_gt_B, A_lt_B, A_eq_B);

assign x[0] = A[0] && B[0] || !A[0] && !B[0],

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magnitude_comparator b1 (A, B, A_gt_B, A_lt_B,

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module stimulus; initial

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