VLSI Physical Design with Timing Analysis

Lecture – 50: Crosstalk Analysis

Bishnu Prasad Das

Department of Electronics and Communication Engineering

1
 Contents
• Introduction
• Crosstalk delay analysis
• Crosstalk avoidance techniques

2
 Introduction
• In deep submicron technologies, crosstalk plays an important role
in the signal integrity of the design.

• The crosstalk noise refers to unintentional coupling of activity

between two or more signals.

3
 Introduction
• Causes of crosstalk noise:
– Increasing number of metal layers
– Vertically dominant metal aspect ratio
– Larger number of interacting devices and interconnects
– Higher routing density due to finer geometry
– Faster waveforms due to higher frequencies
– Lower supply voltage

4
 Introduction
• It is caused by the capacitive coupling between neighboring
signals on the die.

– The affected signal is called the victim, and

– The affecting signals are termed as aggressors.

• A net can be a victim as well as an aggressor.

5
 Introduction
Example of coupled interconnect

J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach. 2009.

6
 Introduction
• Broadly, there are two types of noise effects caused by crosstalk

– Glitch: noise caused on a steady victim signal due to coupling

of switching activity of neighboring aggressors

– Timing: Crosstalk delta delay caused by coupling of the

switching activity of the victim with the
switching activity of the aggressors.

7
 Crosstalk Glitch Analysis
• A steady signal net can have a glitch (positive or negative) due to
charge transferred by the switching aggressors through the
coupling capacitances.

8
 Crosstalk Glitch Analysis
UNAND0 switches and charges its output net (labeled Aggressor).

Some of the charge is also transferred to the victim net through

the coupling capacitance Cc and results in a positive glitch.

The steady value on the victim net (in this case, 0 or low) is
restored because the transferred charge is dissipated through the
pull-down stage of the driving cell INV2.

J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach. 2009.

9
 Capacitive coupling to a floating line
• Assume that the voltage at node X
experiences a step change equal to ∆VX.

• This step appears on node Y attenuated

by the capacitive voltage divider.

𝐶𝑋𝑌
– ∆𝑉𝑌 = ∆𝑉𝑋
𝐶𝑌 + 𝐶𝑋𝑌

10
 Capacitive coupling to a driven line

Driven line Y with interferer X

Voltage response for different rise times of Vx

(0 t0 2.5 V)

Digital Integrated Circuits A Design PerspectiveJM Rabaey, A. Chandrakasan and B. Nikolic Prentice Hall, 2003

11
 Crosstalk Glitch Analysis
• The magnitude of the glitch caused is dependent upon a variety
of factors, such as

– Coupling capacitance between the aggressor net and victim

– Slew of the aggressor net

– Victim net grounded capacitance

– Victim net driving strength

12
 Crosstalk Glitch Analysis
• Types of Glitches:
– Rise and Fall Glitches

– Overshoot and Undershoot

Glitches

J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach. 2009.

13
 Crosstalk delay analysis
• The capacitance extraction for a typical net in a nanometer design
consists of contributions from many neighboring conductors.

• When the neighboring nets are

– steady (or not switching), the inter-signal capacitances can be

treated as grounded.

– switching, the charging current through the cou-

pling capacitance impacts the timing of the net.
14
 Crosstalk delay analysis
• An example to show the crosstalk impact:

J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach. 2009.

15
 Crosstalk delay analysis
• The capacitive charge required from the driving cell in various
scenarios is different:
1. Aggressor net steady

2. Aggressor switching in the same direction

3. Aggressor switching in the opposite direction

16
 Crosstalk delay analysis
1. Aggressor net steady:

– The driving cell(NAND) for the net N1

provides the charge for Cg and Cc to
be charged to Vdd.

– The total charge is (Cg + Cc)*Vdd.

J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach. 2009.

17
 Crosstalk delay analysis

In this scenario, no crosstalk is considered from the aggressor nets.

J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach. 2009.

18
 Crosstalk delay analysis
2. Aggressor switching in the same direction:

– The driving cell is aided by the

aggressor switching in the same
direction.

J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach. 2009.

19
 Crosstalk delay analysis
• If the slew of the aggressor net is faster than that of N1,
– The actual charge required can be even smaller than (Cg * Vdd)
since the aggressor net can also provide a charging current for Cg.

J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach. 2009.

20
 Crosstalk delay analysis
• The reduction in delay is labeled as negative crosstalk delay.

• This scenario is normally considered for min path analysis.

J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach. 2009.

21
 Crosstalk delay analysis
3. Aggressor switching in the opposite direction:

– The coupling capacitance is charged from

-Vdd to Vdd.

– The charge on coupling capacitance

changes by (2 * Cc * Vdd) before and after the
transitions.

J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach. 2009.

22
 Crosstalk delay analysis
• This results in a larger delay for the switching net N1.

J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach. 2009.

23
 Crosstalk delay analysis
• The increase in delay is labeled as positive crosstalk delay.

• This scenario is normally considered for max path analysis.

J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach. 2009.

24
 Crosstalk delay analysis
• The following four types of crosstalk delay contributions are
computed for every cell and interconnect in the design:
1. Positive rise delay (rise edge moves forward in time)

2. Negative rise delay (rise edge moves backward in time)

3. Positive fall delay (fall edge moves forward in time)

4. Negative fall delay(fall edge moves backward in time)

25
 STA
• The STA with crosstalk analysis verifies the design with the worst-
case crosstalk delays for the data path and the clock paths.

J. Bhasker and R. Chadha, Static timing analysis for nanometer designs: A practical approach. 2009.

26
 Setup Analysis
• The worst condition for setup check is

– Both the launch clock path and the data path have positive
crosstalk.

– The capture clock path has negative crosstalk.

27
 Setup Analysis
The worst case setup (or max path) analysis assumes that:
Path Crosstalk Reason
Launch clock path positive crosstalk delay The data is launched late
Data path positive crosstalk delay Data takes longer for the data to
reach the destination
Capture clock path negative crosstalk delay The data is captured by the
capture flip-flop early

28
 Hold Analysis
• The worst condition for hold check is

– Both the launch clock path and the data path have negative
crosstalk.

– The capture clock path has positive crosstalk.

29
 Hold Analysis
• There is one important difference between the hold and setup analyses:
– The launch and capture clock edge are normally the same edge for
the hold analysis.
– The common clock portion cannot have different crosstalk
contributions.
– Therefore, Worst-case hold analysis omits
common clock path crosstalk.

30
 Hold Analysis
The worst-case hold (or min path) analysis for STA with crosstalk assumes:
Path Crosstalk Reason
Launch clock path negative crosstalk delay The data is launched early
(not including the common path)
Data path negative crosstalk delay Data reaches the destination early
Capture clock path positive crosstalk delay the data is captured by the
(not including the common path) capture flipflop late

31
 Noise Avoidance Techniques
• Shielding
• Wire spacing
• Fast slew rate
• Maintain good stable supply Fig: Cross section of routing layers, illustrating the use of
shielding to reduce capacitive cross-talk.
• Guard ring
• Deep n-well
• Isolating a block
Digital Integrated CircuitsA Design PerspectiveJM Rabaey, A. Chandrakasan and B. Nikolic Prentice Hall, 2003

32
Thank You

33