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Crosstalk and Noise

This document discusses crosstalk and noise in digital VLSI designs. It outlines sources of noise such as increasing metal layers and routing density. Two main types of noise effects are glitch and timing delay caused by signal coupling. Glitch magnitude depends on factors like coupling capacitance and slew rates. Glitch only affects designs if its magnitude is larger than input thresholds. Noise can be reduced through techniques like wire shielding, spacing, and isolating blocks.

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Omar Abd Elrhman
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61 views5 pages

Crosstalk and Noise

This document discusses crosstalk and noise in digital VLSI designs. It outlines sources of noise such as increasing metal layers and routing density. Two main types of noise effects are glitch and timing delay caused by signal coupling. Glitch magnitude depends on factors like coupling capacitance and slew rates. Glitch only affects designs if its magnitude is larger than input thresholds. Noise can be reduced through techniques like wire shielding, spacing, and isolating blocks.

Uploaded by

Omar Abd Elrhman
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Crosstalk and Noise in digital VLSI [1]

Eng. Omar Abdelrahman Ismail

[1] Static Timing Analysis for Nanometer Designs A Practical Approach book
Contents
- Overview
- Sources of Noise
- Types of noise effects
- Crosstalk due to glitch
- Types of glitch
- Factors that effect on glitch
- Is glitch effects badly on the design all time?
- Noise avoidance techniques
-
Overview
In deep submicron technologies, noise plays an important role in the signal integrity of the
design.
Noise refers to undesired or unintentional effects affecting the proper operation of the chip. In
nanometer technologies, the noise can impact in terms of functionality or in terms of timing of
the devices.
The crosstalk noise refers to unintentional coupling of activity between two or more signals
which can be modeled as coupling capacitance between two or more wire traces.

Sources of Noise
- Increasing number of metal layers
- Vertically dominant metal aspect ratio
This means that the wires are thin and tall unlike the wide and thin in the earlier process
geometries. Thus, a greater proportion of the capacitance is comprised of sidewall
coupling capacitance which maps into wire-to-wire capacitance between neighboring
wires.
- Higher routing density due to finer geometry
- Larger number of interacting devices and interconnects
Thus, greater number of active standard cells and signal traces are packed in the same
silicon area causing a lot more interactions.
- Faster waveforms due to higher frequencies
Fast edge rates cause more current spikes as well as greater coupling impact on the
neighboring traces and cells.
- Lower supply voltage
The supply voltage reduction leaves little margin for noise.

Types of noise effects


There are two types of noise effects caused by crosstalk:
1- glitch which refers to noise caused on a steady victim (the affected signals) signal due to
coupling of switching activity of neighboring aggressors (the affecting signals).
2- change in timing (crosstalk delta delay), caused by coupling of switching activity of the
victim with the switching activity of the aggressors.

Crosstalk due to glitch


A steady signal net can have a glitch (positive or negative) due to charge transferred by the
switching aggressors through the coupling capacitances.
Types of glitch
1- Rise glitch
2- Fall glitch
3- Overshoot glitch
4- Undershoot glitch

Figure 1 shows the different between glitch types.

Figure 1

Factors that effect on glitch


The magnitude of the glitch caused is dependent upon a variety of factors, some of these
factors are:

1- Coupling capacitance between the aggressor net and victim


The greater the coupling capacitance, the larger the magnitude of the glitch.
2- Slew of the aggressor net
The faster the slew at the aggressor net, the larger the magnitude of glitch. In general,
faster slew is because of higher output drive strength for the cell driving the aggressor
net.
3- Victim net grounded capacitance
The smaller the grounded capacitance on the victim net, the larger the magnitude of the
glitch.
4- Victim net driving strength
The smaller the output drive strength of the cell driving the victim net, the larger the
magnitude of the glitch.
Is glitch have the effect on the design all time?
Depending on glitch’s magnitude and width, glitch can’t affect badly on the design. For
example, if the input of inverter is steady low and a rise glitch affects on it but its magnitude is
lower than DC input margin due to DC transfer characteristic of this cell as shown in figure 2,
that is not affect on the inverter output.

Figure 2

Figure 3 shows the difference between safe and potentially hazardous glitches.

Figure 3
Noise avoidance techniques
1- Shielding of wires
This method requires that shield wires are placed on either side of the critical signals,
the shields are connected to power or ground rails.
2- Wire spacing
3- Maintain good stable supply
4- Guard ring
5- Deep n-well
6- Isolating a block
In a hierarchical design flow, routing halos can be added to the boundary of the blocks

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