SN 74 HC 164

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SN54HC164, SN74HC164
SCLS115G – DECEMBER 1982 – REVISED SEPTEMBER 2015
SNx4HC164 8-Bit Parallel-Out Serial Shift Registers

1 Features 3 Description
•
1 Wide Operating Voltage Range of 2 V to 6 V These 8-bit shift registers feature AND-gated serial
inputs and an asynchronous clear (CLR) input. The
• Outputs Can Drive Up to 10 LSTTL Loads gated serial (A and B) inputs permit complete control
• Low Power Consumption, 80-μA Maximum ICC over incoming data; a low at either input inhibits entry
• Typical tpd = 20 ns of the new data and resets the first flip-flop to the low
• ±4-mA Output Drive at 5 V level at the next clock (CLK) pulse. A high-level input
enables the other input, which then determines the
• Low Input Current of 1-μA Maximum state of the first flip-flop. Data at the serial inputs can
• AND-Gated (Enable/Disable) Serial Inputs be changed while CLK is high or low, provided the
• Fully Buffered Clock and Serial Inputs minimum set-up time requirements are met. Clocking
occurs on the low-to-high-level transition of CLK.
• Direct Clear
• On Products Compliant to MIL-PRF-38535, Device Information(1)
All Parameters Are Tested Unless Otherwise PART NUMBER PACKAGE BODY SIZE (NOM)
Noted. On All Other Products, Production SOIC (14) 8.65 mm × 3.91 mm
Processing Does Not Necessarily Include Testing PDIP (14) 19.30 mm × 6.35 mm
of All Parameters. SN74HC164
SO (14) 10.30 mm × 5.30 mm
TSSOP (14) 5.00 mm × 4.40 mm
2 Applications
CDIP (14) 19.94 mm × 6.92 mm
• Programable Logic Controllers
SN54HC164 CFP (14) 9.21 mm × 6.29 mm
• Appliances LCCC (14) 9.39 mm × 9.39 mm
• Video Display Systems
(1) For all available packages, see the orderable addendum at
• Output Expander the end of the data sheet.
Logic Diagram (Positive Logic)

8
CLK
1 C1 C1 C1 C1 C1 C1 C1 C1
A
2 1D 1D 1D 1D 1D 1D 1D 1D
B
R R R R R R R R
9
CLR
3 4 5 6 10 11 12 13
QA QB QC QD QE QF QG QH
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SCLS115G – DECEMBER 1982 – REVISED SEPTEMBER 2015 www.ti.com
Table of Contents
1 Features .................................................................. 1 8 Parameter Measurement Information ................ 13
2 Applications ........................................................... 1 9 Detailed Description ............................................ 14
3 Description ............................................................. 1 9.1 Overview ................................................................. 14
4 Revision History..................................................... 2 9.2 Functional Block Diagram ....................................... 14
5 Device Comparison Table..................................... 3 9.3 Feature Description................................................. 14
9.4 Device Functional Modes........................................ 14
6 Pin Configuration and Functions ......................... 4
7 Specifications......................................................... 6 10 Application and Implementation........................ 15
10.1 Application Information.......................................... 15
7.1 Absolute Maximum Ratings ...................................... 6
10.2 Typical Application ............................................... 15
7.2 ESD Ratings ............................................................ 6
7.3 Recommended Operating Conditions....................... 6 11 Power Supply Recommendations ..................... 17
7.4 Thermal Information .................................................. 7 12 Layout................................................................... 17
7.5 Electrical Characteristics, TA = 25°C ........................ 7 12.1 Layout Guidelines ................................................. 17
7.6 Electrical Characteristics, TA = –55°C to 125°C ....... 7 12.2 Layout Example .................................................... 17
7.7 Electrical Characteristics, TA = –55°C to 85°C ......... 8 13 Device and Documentation Support ................. 18
7.8 Timing Requirements, TA = 25°C.............................. 8 13.1 Documentation Support ........................................ 18
7.9 Timing Requirements, TA = –55°C to 125°C ............ 9 13.2 Related Links ........................................................ 18
7.10 Timing Requirements, TA = –55°C to 85°C ............ 9 13.3 Community Resources.......................................... 18
7.11 Switching Characteristics, TA = 25°C.................... 10 13.4 Trademarks ........................................................... 18
7.12 Switching Characteristics, TA = –55°C to 125°C .. 10 13.5 Electrostatic Discharge Caution ............................ 18
7.13 Switching Characteristics, TA = –55°C to 85°C .... 11 13.6 Glossary ................................................................ 18
7.14 Typical Characteristics .......................................... 12 14 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (October 2013) to Revision G Page
• Added Applications section, Device Information table, Pin Configuration and Functions section, ESD Ratings table,
Thermal Information table, Typical Characteristics section, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section....................................... 1
• Added Military Disclaimer to Features list. ............................................................................................................................. 1
• Added Handling Ratings table. ............................................................................................................................................... 6
Changes from Revision E (November 2010) to Revision F Page
• Updated document to new TI data sheet format. ................................................................................................................... 1

• Removed Ordering Information table. .................................................................................................................................... 1
• Updated operating temperature range. .................................................................................................................................. 6
2 Submit Documentation Feedback Copyright © 1982–2015, Texas Instruments Incorporated
Product Folder Links: SN54HC164 SN74HC164

www.ti.com SCLS115G – DECEMBER 1982 – REVISED SEPTEMBER 2015
5 Device Comparison Table
PART NUMBER PACKAGE BODY SIZE (NOM)

SN74HC164D SOIC (14) 8.65 mm × 3.91 mm
SN74HC164N PDIP (14) 19.30 mm × 6.35 mm
SN74HC164NS SO (14) 10.30 mm × 5.30 mm
SN74HC164PW TSSOP (14) 5.00 mm × 4.40 mm
SN54HC164J CDIP (14) 19.94 mm × 6.92 mm
SN54HC164W CFP (14) 9.21 mm × 6.29 mm
SN54HC164FK LCCC (14) 9.39 mm × 9.39 mm
Copyright © 1982–2015, Texas Instruments Incorporated Submit Documentation Feedback 3

6 Pin Configuration and Functions
D, N, NS, J, W, or PW Package
14-Pin SOIC, PDIP, SO, CDIP, CFP, or TSSOP
Top View
A 1 14 VCC
B 2 13 QH
QA 3 12 QG
QB 4 11 QF
QC 5 10 QE
QD 6 9 CLR
GND 7 8 CLK
Pin Functions
PIN
SOIC, PDIP, SO, I/O DESCRIPTION
CDIP, CFP, or NAME
TSSOP NO.
1 A I Gated Serial Input 1
2 B I Gated Serial Input 2
3 QA O Parallel Output
4 QB O Parallel Output
5 QC O Parallel Output
6 QD O Parallel Output
7 GND - Ground
8 CLK I Clock
9 CLR I Clear 1 Active-Low
10 QE O Parallel Output
11 QF O Parallel Output
12 QG O Parallel Output
13 QH O Parallel Output
14 VCC — Power

FK Package
20-Pin LCCC
Top View
VCC
QH
NC
B
A
3 2 1 20 19
QA 4 18 QG
NC 5 17 NC
QB 6 16 QF
NC 7 15 NC
QC 8 14 QE
9 10 11 12 13
QD
GND
CLK
CLR
NC
NC – No internal connection
Pin Functions
PIN
I/O DESCRIPTION
LCCC NO. NAME
1 NC — No Connect
2 A I Gated Serial Input 1
3 B I Gated Serial Input 2
4 QA O Parallel Output
5 NC — No Connect
6 QB O Parallel Output
7 NC — No Connect
8 QC O Parallel Output
9 QD O Parallel Output
10 GND — Ground
11 NC — No Connect
12 CLK I Clock
13 CLR I Clear 1 Active-Low
14 QE O Parallel Output
16 QF O Parallel Output
18 QG O Parallel Output
19 QH O Parallel Output
20 VCC — Power

7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNITS
VCC Supply voltage −0.5 7 V
(2)
IIK Input clamp current VI < 0 or VI > VCC ±20 mA
IOK Output clamp current (2) VO < 0 or VO > VCC ±20 mA
IO Continuous output current VO = 0 to VCC ±25 mA
Continuous current through VCC or GND ±50 mA
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
SN54HC164 SN74HC164
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 2 5 6 2 5 6 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 4.5 V 3.15 3.15 V
VCC = 6 V 4.2 4.2
VCC = 2 V 0.5 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35 1.35 V
VCC = 6 V 1.8 1.8
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
VCC = 2 V 1000 1000
Input transition rise and fall
Δt/Δv (2) VCC = 4.5 V 500 500 ns
time
VCC = 6 V 400 400
TA Operating free-air temperature –55 125 –40 125 °C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
(2) If this device is used in the threshold region (from VIL max = 0.5 V to VIH min = 1.5 V), there is a potential to go into the wrong state from
induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device;
however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes.

7.4 Thermal Information

SN54HC164 SN74HC164
J W FK D N NS PW
THERMAL METRIC (1) (CDIP) (CFP) (LCCC) (SOIC) (PDIP) (SO) (TSSOP) UNIT
14 14 20 14 14 14 14
PINS PINS PINS PINS PINS PINS PINS
RθJA Junction-to-ambient thermal
— — — 86 80 76 113 °C/W
resistance
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics, TA = 25°C

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
2V 1.9 1.998
IOH = –20 μA 4.5 V 4.4 4.499
VOH VI = VIH or VIL 6V 5.9 5.999 V
IOH = –4 mA 4.5 V 3.98 4.3
IOH = –5.2 mA 6V 5.48 5.8
2V 0.002 0.1
IOL = 20 μA 4.5 V 0.001 0.1
VOL VI = VIH or VIL 6V 0.001 0.1 V
IOL = 4 mA 4.5 V 0.17 0.26
IOL = 5.2 mA 6V 0.15 0.26
II VI = VCC or 0 6V ±0.1 ±100 nA
ICC VI = VCC or 0 IO = 0 6V 8 µA
2 V to
Ci 3 10 pF
6V
7.6 Electrical Characteristics, TA = –55°C to 125°C

Recommended
SN54HC164
PARAMETER TEST CONDITIONS VCC SN74HC164 UNIT
MIN TYP MAX MIN TYP MAX
2V 1.9 1.9
IOH = –20 μA 4.5 V 4.4 4.4
VOH VI = VIH or VIL 6V 5.9 5.9 V
IOH = –4 mA 4.5 V 3.7 3.7
IOH = –5.2 mA 6V 5.2 5.2
2V 0.1 0.1
IOL = 20 μA 4.5 V 0.1 0.1
VOL VI = VIH or VIL 6V 0.1 0.1 V
IOL = 4 mA 4.5 V 0.4 0.4
IOL = 5.2 mA 6V 0.4 0.4
II VI = VCC or 0 6V ±1000 ±1000 nA
ICC VI = VCC or 0 IO = 0 6V 160 160 µA
2 V to
Ci 10 10 pF
6V

7.7 Electrical Characteristics, TA = –55°C to 85°C

SN74HC164
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP MAX
2V 1.9
IOH = –20 μA 4.5 V 4.4
VOH VI = VIH or VIL 6V 5.9 V
IOH = –4 mA 4.5 V 3.84
IOH = –5.2 mA 6V 5.34
2V 0.1
IOL = 20 μA 4.5 V 0.1
VOL VI = VIH or VIL 6V 0.1 V
IOL = 4 mA 4.5 V 0.33
IOL = 5.2 mA 6V 0.33
II VI = VCC or 0 6V ±1000 nA
ICC VI = VCC or 0 IO = 0 6V 80 µA
2 V to
Ci 10 pF
6V
7.8 Timing Requirements, TA = 25°C

PARAMETER VCC MIN NOM MAX UNIT
2V 6
fclock Clock frequency 4.5 V 31 MHz
6V 36
2V 100
CLR low 4.5 V 20
6V 17
tw Pulse duration ns
2V 80
CLK high or low 4.5 V 16
6V 14
2V 100
Data 4.5 V 20
6V 17
tsu Setup time before CLK↑ ns
2V 100
CLR inactive 4.5 V 20
6V 17
2V 5
th Hold time, data after CLK↑ 4.5 V 5 ns
6V 5

7.9 Timing Requirements, TA = –55°C to 125°C

RECOMMENDED
SN54HC164
PARAMETER VCC SN74HC164 UNIT
MIN NOM MAX MIN NOM MAX
2V 4.2 4.2
fclock Clock frequency 4.5 V 21 21 MHz
6V 25 25
2V 150 125
CLR low 4.5 V 30 25
6V 25 21
2V 120 120
CLK high or low 4.5 V 24 24
6V 20 20
2V 150 125
Data 4.5 V 30 25
6V 25 25
2V 150 125
CLR inactive 4.5 V 30 25
6V 25 25
2V 5 5
th Hold time, data after CLK↑ 4.5 V 5 5 ns
6V 5 5
7.10 Timing Requirements, TA = –55°C to 85°C

SN74HC164
PARAMETER VCC UNIT
MIN NOM MAX
2V 5
fclock Clock frequency 4.5 V 25 MHz
6V 28
2V 125
CLR low 4.5 V 25
6V 21
2V 100
CLK high or low 4.5 V 20
6V 18
2V 125
Data 4.5 V 25
6V 21
2V 125
CLR inactive 4.5 V 25
6V 21
2V 5
th Hold time, data after CLK↑ 4.5 V 5 ns
6V 5

7.11 Switching Characteristics, TA = 25°C

over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 3)
PARAMETER FROM (INPUT) TO (OUTPUT) VCC MIN TYP MAX UNIT
2V 6 10
fmax 4.5 V 31 54 MHz
6V 36 62
2V 140 205
tPHL CLR Any Q 4.5 V 28 41 ns
6V 24 35
2V 115 175
tpd CLK Any Q 4.5 V 23 35
6V 20 30
2V 38 75
tt 4.5 V 8 15 ns
6V 6 13
7.12 Switching Characteristics, TA = –55°C to 125°C

RECOMMENDED
FROM SN54HC164
PARAMETER TO (OUTPUT) VCC SN74HC164 UNIT
(INPUT)
MIN TYP MAX MIN TYP MAX
2V 4.2 4.2
fmax 4.5 V 21 21 MHz
6V 25 25
2V 295 255
tPHL CLR Any Q 4.5 V 59 51 ns
6V 51 46
2V 265 220
tpd CLK Any Q 4.5 V 53 44
6V 45 38
2V 110 110
tt 4.5 V 22 22 ns
6V 19 19

7.13 Switching Characteristics, TA = –55°C to 85°C

SN74HC164
PARAMETER FROM (INPUT) TO (OUTPUT) VCC UNIT
MIN TYP MAX
2V 5
fmax 4.5 V 25 MHz
6V 28
2V 255
tPHL CLR Any Q 4.5 V 51 ns
6V 46
2V 220
tpd CLK Any Q 4.5 V 44
6V 38
2V 95
tt 4.5 V 19 ns
6V 16
CLR
Serial Inputs
CLK
QA
QB
QC
QD
Outputs
QE
QF
QG
QH
Clear Clear
Figure 1. SN74HC164 Example Timing Diagram

7.14 Typical Characteristics

TA = 25°C
120
110
100
90
80
70
tpd (ns)
60
50
40
30
20
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VCC (V) C001
Figure 2. Propagation Delay vs Supply Voltage at TA = 25°C

8 Parameter Measurement Information

VCC
High-Level
50% 50%
Pulse
From Output Test 0V
Under Test Point tw
CL = 50 pF VCC
(see Note A) Low-Level
Pulse 50% 50%
0V
LOAD CIRCUIT VOLTAGE WAVEFORMS
PULSE DURATIONS
VCC
Input 50% 50%
0V
tPLH tPHL
VCC In-Phase VOH
Reference 50% 90% 90%
Output 50% 50%
Input 10% 10%
0V VOL
tr tf
tsu th
tPHL tPLH
Data VCC VOH
90% 90% Out-of-Phase 90% 90%
Input 50% 50% 50% 50%
10% 10% 0 V Output 10% 10%
VOL
tr tf tf tr
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

SETUP AND HOLD AND INPUT RISE AND FALL TIMES PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A. CL includes probe and test-fixture capacitance.

B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C. For clock inputs, fmax is measured when the input duty cycle is 50%.
D. The outputs are measured one at a time with one input transition per measurement.
E. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms

9 Detailed Description
9.1 Overview
The SN74HC164 is an 8-bit shift register with 2 serial inputs (A and B) connected through an AND gate, as well
as an asynchronous clear (CLR). The device requires a high signal on both A and B in order to set the input data
line high; a low signal on either input will set the input data line low. Data at A and B can be changed while CLK
is high or low, provided that the minimum set-up time requirements are met.
The CLK pin of the SN74HC164 is triggered on a positive or rising-edge signal, from LOW to HIGH. Upon a
positive-edge trigger, the device will store the result of the (A ● B) input data line in the first register and
propagate each register’s data to the next register. The data of the last register, QH, will be discarded at each
clock trigger. If a low signal is applied to the CLR pin of the SN74HC164, the device will set all registers to a
value of 0 immediately.
9.2 Functional Block Diagram
8
CLK
1 C1 C1 C1 C1 C1 C1 C1 C1
A
2 1D 1D 1D 1D 1D 1D 1D 1D
B
R R R R R R R R
9
CLR
3 4 5 6 10 11 12 13
QA QB QC QD QE QF QG QH
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
9.3 Feature Description

The HC164 has a wide operating voltage range of 2 V to 6 V, outputs that can drive up to 10 LSTTL loads and
Low Power Consumption, 80-μA maximum I. It is typically tpd = 20 ns and has ±4-mA output drive at 5 V with low
input current of 1-μA maximum. It also has AND-gated (enable/disable) serial inputs a fully buffered clock and
serial inputs as well as a direct clear.
9.4 Device Functional Modes

Table 1 lists the functional modes of the SNx4HC164.
Table 1. Function Table (1) (2)

INPUTS OUTPUTS
CLR CLK A B QA QB ... QH
L X X X L L L
H L X X QA0 QB0 QH0
H ↑ H H H QAn QGn
H ↑ L X L QAn QGn
H ↑ X L L QAn QGn
(1) QA0, QB0, QH0 = the level of QA, QB, or QH, respectively, before the
indicated steady-state input conditions were established.
(2) QAn, QGn = the level of QA or QG before the most recent ↑ transition
of CLK: indicates a 1-bit shift.

10 Application and Implementation

10.1 Application Information
The SNx4HC164 is an 8-bit shift register that can be used as a deserializer in order to reduce the number of
GPIO's needed when driving multiple LED's. In order to correctly display the proper output in the LED's a sink
MOSFET was added to prevent the LED's from lighting up until the correct data or the proper clock signal has
been achieved.
10.2 Typical Application
Data SN74HC164 Vcc

Enable 0.1 µF
Vcc 14
A1
D QA 3
Data B2
QB 4
QC 5
µCU
QD 6
«
8 CLK QE 10
«
9 CLR
QF 11
GND
«
7
QG 12
«
QH 13
LED ON/OFF
GND
Figure 4. Typical Application Diagram
10.2.1 Design Requirements

Ensure that the incoming clock rising edge meets the criteria in Recommended Operating Conditions.
10.2.2 Detailed Design Procedure

Ensure that input and output voltages do not exceed ratings in Absolute Maximum Ratings.
Input voltage threshold information can be found in Recommended Operating Conditions.
Detailed timing requirements can be found in Timing Requirements, TA = 25°C.

Typical Application (continued)

10.2.3 Application Curve
120
110
100
90
80
70
tpd (ns)
60
50
40
30
20
10
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
VCC (V) C001
Figure 5. Propagation Delay vs Supply Voltage at TA = 25°C

11 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin must have a good bypass capacitor in order to prevent power disturbance. For devices with a
single supply, a 0.1-μF capacitor is recommended and if there are multiple VCC pins then a 0.01-μF or 0.022-μF
capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different
frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power pin as possible for best results.
12 Layout
12.1 Layout Guidelines

Reflections and matching are closely related to loop antenna theory, but different enough to warrant their own
discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This is primarily due to the
change of width of the trace. At the apex of the turn, the trace width is increased to 1.414 times its width. This
upsets the transmission line characteristics, especially the distributed capacitance and self–inductance of the
trace — resulting in the reflection. It is a given that not all PCB traces can be straight, and so they will have to
turn corners. Figure 6 shows progressively better techniques of rounding corners. Only the last example
maintains constant trace width and minimizes reflections.
12.2 Layout Example

WORST BETTER BEST
2W
1W min.
W
Figure 6. Trace Example

13 Device and Documentation Support
13.1 Documentation Support

13.1.1 Related Documentation
For related docunmentation, see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
13.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN54HC164 Click here Click here Click here Click here Click here
SN74HC164 Click here Click here Click here Click here Click here
13.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM
www.ti.com 6-Apr-2024
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
5962-8416201VCA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8416201VC Samples
& Green A
SNV54HC164J
5962-8416201VDA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8416201VD Samples
& Green A
SNV54HC164W
84162012A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 84162012A Samples
& Green SNJ54HC
164FK
8416201CA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8416201CA Samples
& Green SNJ54HC164J
SN54HC164J ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SN54HC164J Samples
& Green
SN74HC164DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 HC164 Samples
SN74HC164DRG3 ACTIVE SOIC D 14 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 HC164 Samples
SN74HC164DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 Samples
SN74HC164N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 SN74HC164N Samples
SN74HC164NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 125 SN74HC164N Samples
SN74HC164NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 Samples
SN74HC164PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 HC164 Samples
SN74HC164PWRE4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 Samples
SN74HC164PWRG4 ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 HC164 Samples
SNJ54HC164FK ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 84162012A Samples
& Green SNJ54HC
164FK
SNJ54HC164J ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8416201CA Samples
& Green SNJ54HC164J
Addendum-Page 1
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
SNJ54HC164W ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8416201DA Samples
& Green SNJ54HC164W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HC164, SN54HC164-SP, SN74HC164 :
Addendum-Page 2
• Catalog : SN74HC164, SN54HC164

• Military : SN54HC164
• Space : SN54HC164-SP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC164DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC164DRG3 SOIC D 14 2500 330.0 16.8 6.5 9.5 2.1 8.0 16.0 Q1
SN74HC164DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC164DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HC164NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74HC164NSR SO NS 14 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1
SN74HC164PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC164PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HC164PWRG4 TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
Pack Materials-Page 1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HC164DR SOIC D 14 2500 356.0 356.0 35.0
SN74HC164DRG3 SOIC D 14 2500 364.0 364.0 27.0
SN74HC164DRG4 SOIC D 14 2500 356.0 356.0 35.0
SN74HC164DRG4 SOIC D 14 2500 340.5 336.1 32.0
SN74HC164NSR SO NS 14 2000 356.0 356.0 35.0
SN74HC164NSR SO NS 14 2000 356.0 356.0 35.0
SN74HC164PWR TSSOP PW 14 2000 356.0 356.0 35.0
SN74HC164PWR TSSOP PW 14 2000 356.0 356.0 35.0
SN74HC164PWRG4 TSSOP PW 14 2000 356.0 356.0 35.0
TUBE
T - Tube
height L - Tube length
W - Tube
width
B - Alignment groove width

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-8416201VDA W CFP 14 25 506.98 26.16 6220 NA
84162012A FK LCCC 20 55 506.98 12.06 2030 NA
SN74HC164N N PDIP 14 25 506 13.97 11230 4.32
SN74HC164N N PDIP 14 25 506 13.97 11230 4.32
SN74HC164NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74HC164NE4 N PDIP 14 25 506 13.97 11230 4.32
SNJ54HC164FK FK LCCC 20 55 506.98 12.06 2030 NA
SNJ54HC164W W CFP 14 25 506.98 26.16 6220 NA
GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4229370\/A\
www.ti.com
PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]
1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
7 8
B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]
C SEATING PLANE
.308-.314
[7.83-7.97]
AT GAGE PLANE
.015 GAGE PLANE

[0.38]
0 -15 14X .008-.014

TYP [0.2-0.36]
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A
1 14
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
7 8
SYMM
LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X
.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING
METAL
SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X
4214771/A 05/2017
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2024, Texas Instruments Incorporated

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SNx4HC164 8-Bit Parallel-Out Serial Shift Registers

Logic Diagram (Positive Logic)

Changes from Revision F (October 2013) to Revision G Page

Changes from Revision E (November 2010) to Revision F Page

• Updated document to new TI data sheet format. ................................................................................................................... 1

2 Submit Documentation Feedback Copyright © 1982–2015, Texas Instruments Incorporated

Product Folder Links: SN54HC164 SN74HC164

5 Device Comparison Table

PART NUMBER PACKAGE BODY SIZE (NOM)

Copyright © 1982–2015, Texas Instruments Incorporated Submit Documentation Feedback 3

6 Pin Configuration and Functions

4 Submit Documentation Feedback Copyright © 1982–2015, Texas Instruments Incorporated

Product Folder Links: SN54HC164 SN74HC164

Copyright © 1982–2015, Texas Instruments Incorporated Submit Documentation Feedback 5

7.2 ESD Ratings

7.3 Recommended Operating Conditions

6 Submit Documentation Feedback Copyright © 1982–2015, Texas Instruments Incorporated

Product Folder Links: SN54HC164 SN74HC164

7.4 Thermal Information

7.5 Electrical Characteristics, TA = 25°C

7.6 Electrical Characteristics, TA = –55°C to 125°C

Copyright © 1982–2015, Texas Instruments Incorporated Submit Documentation Feedback 7

7.7 Electrical Characteristics, TA = –55°C to 85°C

7.8 Timing Requirements, TA = 25°C

8 Submit Documentation Feedback Copyright © 1982–2015, Texas Instruments Incorporated

Product Folder Links: SN54HC164 SN74HC164

7.9 Timing Requirements, TA = –55°C to 125°C

7.10 Timing Requirements, TA = –55°C to 85°C

Copyright © 1982–2015, Texas Instruments Incorporated Submit Documentation Feedback 9

7.11 Switching Characteristics, TA = 25°C

7.12 Switching Characteristics, TA = –55°C to 125°C

10 Submit Documentation Feedback Copyright © 1982–2015, Texas Instruments Incorporated

Product Folder Links: SN54HC164 SN74HC164

7.13 Switching Characteristics, TA = –55°C to 85°C

Figure 1. SN74HC164 Example Timing Diagram

Copyright © 1982–2015, Texas Instruments Incorporated Submit Documentation Feedback 11

7.14 Typical Characteristics

Figure 2. Propagation Delay vs Supply Voltage at TA = 25°C

12 Submit Documentation Feedback Copyright © 1982–2015, Texas Instruments Incorporated

Product Folder Links: SN54HC164 SN74HC164

8 Parameter Measurement Information

VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and test-fixture capacitance.

Figure 3. Load Circuit and Voltage Waveforms

Copyright © 1982–2015, Texas Instruments Incorporated Submit Documentation Feedback 13

9.2 Functional Block Diagram

9.3 Feature Description

9.4 Device Functional Modes

Table 1. Function Table (1) (2)

14 Submit Documentation Feedback Copyright © 1982–2015, Texas Instruments Incorporated

Product Folder Links: SN54HC164 SN74HC164

10 Application and Implementation

10.2 Typical Application

Data SN74HC164 Vcc

10.2.1 Design Requirements

10.2.2 Detailed Design Procedure

Copyright © 1982–2015, Texas Instruments Incorporated Submit Documentation Feedback 15