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SN5414, SN54LS14, SN7414, SN74LS14

SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016

SNx414 and SNx4LS14 Hex Schmitt-Trigger Inverters

1 Features 3 Description
•
1 Operation From Very Slow Edges Each circuit in SNx414 and SNx4LS14 functions as
an inverter. However, because of the Schmitt-Trigger
• Improved Line-Receiving Characteristics action, they have different input threshold levels for
• High Noise Immunity positive-going (VT+) and negative-going (VT–) signals.
These circuits are temperature compensated and can
2 Applications be triggered from the slowest of input ramps and still
• HVAC Gateways give clean, jitter-free output signals.
• Residential Ductless Air Conditioning Outdoor
Units Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
• Robotic Controls
SOIC (14) 4.90 mm × 3.91 mm
• Industrial Stepper Motors
SN7414, SSOP (14) 6.20 mm × 5.30 mm
• Power Meter and Power Analyzers SN74LS14 PDIP (14) 19.30 mm × 6.35 mm
• Digital Input Modules for Factory Automation
SO (14) 10.30 mm × 5.30 mm
CDIP (14) 19.56 mm × 6.67 mm
SN5414,
CFP (14) 9.21 mm × 5.97 mm
SN54LS14
LCCC (20) 8.89 mm × 8.89 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Logic Diagram (Positive Logic)

A Y
Copyright © 2016, Texas Instruments Incorporated

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN5414, SN54LS14, SN7414, SN74LS14
SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 13
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 13
3 Description ............................................................. 1 9 Application and Implementation ........................ 14
4 Revision History..................................................... 2 9.1 Application Information............................................ 14
9.2 Typical Application .................................................. 14
5 Pin Configuration and Functions ......................... 3
9.3 System Examples ................................................... 16
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4 10 Power Supply Recommendations ..................... 17
6.2 ESD Ratings.............................................................. 4 11 Layout................................................................... 17
6.3 Recommended Operating Conditions....................... 4 11.1 Layout Guidelines ................................................. 17
6.4 Thermal Information .................................................. 4 11.2 Layout Example .................................................... 17
6.5 Electrical Characteristics........................................... 5 12 Device and Documentation Support ................. 18
6.6 Switching Characteristics .......................................... 5 12.1 Related Links ........................................................ 18
6.7 Typical Characteristics .............................................. 6 12.2 Receiving Notification of Documentation Updates 18
7 Parameter Measurement Information .................. 9 12.3 Community Resources.......................................... 18
7.1 Series SN5414 and SN7414 Devices ....................... 9 12.4 Trademarks ........................................................... 18
7.2 Series SN54LS14 and SN74LS14 Devices ............ 11 12.5 Electrostatic Discharge Caution ............................ 18
12.6 Glossary ................................................................ 18
8 Detailed Description ............................................ 13
8.1 Overview ................................................................. 13 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram ....................................... 13
Information ........................................................... 18

4 Revision History
Changes from Revision B (February 2002) to Revision C Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
• Deleted Ordering Information table; see the Package Option Addendum at the end of the data sheet ............................... 1
• Changed Package thermal impedance, RθJA, values in Thermal Information table From: 86°C/W To: 90.1°C/W (D),
From: 96°C/W To: 105.4°C/W (DB), From: 80°C/W To: 54.9°C/W (N), and From: 76°C/W To: 88.8°C/W (NS)................... 4

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5 Pin Configuration and Functions

D, DB, N, NS, J, or W Package FK Package

14-Pin SOIC, SSOP, PDIP, SO, CDIP, or CFP 20-Pin LCCC
Top View Top View

VCC
NC
1Y

1A

6A
1A 1 14 VCC

1Y 2 13 6A

20

19
2A 3 12 6Y
2A 4 18 6Y
2Y 4 11 5A
NC 5 17 NC
3A 5 10 5Y
2Y 6 16 5A
3Y 6 9 4A
NC 7 15 NC
GND 7 8 4Y
3A 8 14 5Y

10

12

13
11
9
Not to scale

Not to scale

3Y

GND

NC

4Y

4A
NC – No internal connection

Pin Functions
PIN
SOIC, SSOP, TVSOP, CDIP, I/O DESCRIPTION
NAME LCCC
PDIP,TSSOP, CFP
1A 1 2 I Channel 1 input
1Y 2 3 O Channel 1 output
2A 3 4 I Channel 2 input
2Y 4 6 O Channel 2 output
3A 5 8 I Channel 3 input
3Y 6 9 O Channel 3 output
4A 9 13 I Channel 4 input
4Y 8 12 O Channel 4 output
5A 11 16 I Channel 5 input
5Y 10 14 O Channel 5 output
6A 13 19 I Channel 6 input
6Y 12 18 O Channel 6 output
GND 7 10 — Ground
1, 5, 7,
NC — — No internal connection
11, 15, 17
VCC 14 20 — Power supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply voltage, VCC (2) 7 V
SNx414 5.5
Input voltage V
SNx4LS14 7
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage values are with respect to network ground terminal.

6.2 ESD Ratings

VALUE UNIT
Electrostatic Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±1500
V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±2000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
SN5414, SN54LS14 4.5 5 5.5
VCC Supply voltage V
SN7414, SN74LS14 4.75 5 5.25
SN5414, SN7414 –0.8
IOH High-level output current mA
SN54LS14, SN74LS14 –0.4
SN5414, SN7414 16
IOL Low-level output current SN54LS14 4 mA
SN74LS14 8
SN5414, SN54LS14 –55 125
TA Operating free-air temperature °C
SN7414, SN74LS14 0 70

6.4 Thermal Information

SNx414, SNx4LS14
THERMAL METRIC (1) D (SOIC) DB (SSOP) N (PDIP) NS (SO) UNIT
14 PINS 14 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance (2) 90.1 105.4 54.9 88.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 50.3 57.3 42.5 46.5 °C/W
RθJB Junction-to-board thermal resistance 44.3 52.7 34.7 47.5 °C/W
ψJT Junction-to-top characterization parameter 17.9 22.5 27.8 16.8 °C/W
ψJB Junction-to-board characterization parameter 44.1 52.2 34.6 47.2 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The package termal impedance is calculated in accordance with JESD 51-7.

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6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS (1) MIN TYP (2) MAX UNIT
SNx414 1.5 1.7 2
VT+ VCC = 5 V V
SNx4LS14 1.4 1.6 1.9
SNx414 0.6 0.9 1.1
VT– VCC = 5 V V
SNx4LS14 0.5 0.8 1
Hysteresis
VCC = 5 V 0.4 0.8 V
(VT+ – VT–)
VCC = MIN, II = –12 mA, SNx414 –1.5
VIK V
VCC = MIN, II = –18 mA, SNx4LS14 –1.5
VCC = MIN, VI = 0.6 V, IOH = –0.8 mA, SNx414 2.4 3.4
VOH V
VCC = MIN, VI = 0.5 V, IOH = –0.4 mA, SNx4LS14 2.4 3.4
VCC = MIN, VI = 2 V, IOL = 16 mA, SNx414 0.2 0.4
VOL IOL = 4 mA, SNx4LS14 0.25 0.4 V
VCC = MIN, VI = 1.9 V
IOL = 8 mA, SN74LS14 0.35 0.5
SNx414 –0.43
IT+ VCC = 5 V, VI = VT+ mA
SNx4LS14 –0.14
SNx414 –0.56
IT– VCC = 5 V, VI = VT– mA
SNx4LS14 –0.18
VCC = MAX, VI = 5.5 V, SNx414 1
II mA
VCC = MAX, VI = 7 V, SNx4LS14 0.1
VCC = MAX, VIH = 2.4 V, SNx414 40
IIH µA
VCC = MAX, VIH = 2.7 V, SNx4LS14 20
SNx414 –0.8 –1.2
IIL VCC = MAX, VIL = 0.4 V mA
SNx4LS14 –0.4
SNx414 –18 –55
IOS (3) VCC = MAX mA
SNx4LS14 –20 –100
SNx414 22 36
ICCH VCC = MAX mA
SNx4LS14 8.6 16
SNx414 39 60
ICCL VCC = MAX mA
SNx4LS14 12 21

(1) For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
(2) All typical values are at VCC = 5 V and TA = 25°C.
(3) Not more than one output should be shorted at a time.

6.6 Switching Characteristics

VCC = 5 V, TA = 25°C, and over operating free-air temperature range (unless otherwise noted; see Figure 20)
PARAMETER FROM (INPUT) TO (OUTPUT) TEST CONDITIONS MIN TYP MAX UNIT
RL = 400 Ω and CL = 15 pF, or
tPLH A Y 15 22 ns
RL = 2 kΩ and CL = 15 pF
RL = 400 Ω and CL = 15 pF, or
tPHL A Y 15 22 ns
RL = 2 kΩ and CL = 15 pF

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6.7 Typical Characteristics

6.7.1 SNx414 Circuits

Data for temperatures below 0°C and above 70°C and supply voltage below 4.75 V and above 5.25 V are
applicable for SN5414 only.

1.70 0.90
VCC = 5 V
VCC = 5 V

V T– – Negative-Going Threshold Voltage – V

V T+ – Positive-Going Threshold Voltage – V

1.69 0.89

1.68 0.88

1.67 0.87

1.66 0.86

1.65 0.85

1.64 0.84

1.63 0.83

1.62 0.82

1.61 0.81

1.60 0.80
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
TA – Free-Air Temperature –°C TA – Free-Air Temperature –°C

Figure 1. Positive-Going Threshold Voltage Figure 2. Negative-Going Threshold Voltage

vs Free-Air Temperature vs Free-Air Temperature
850
VCC = 5 V VCC = 5 V
840 TA = 25°C
Relative Frequency of Occurence
830
V T+ – V T– – Hysteresis – mV

820

810

800

790

780

770

760

750
–75 –50 –25 0 25 50 75 100 125 740 760 780 800 820 840 860 880 900
TA – Free-Air Temperature –°C VT+ – VT– – Hysteresis – mV

Figure 3. Hysteresis vs Free-Air Temperature Figure 4. Distribution of Units for Hysteresis

2.0 2.0
TA = 25°C TA = 25°C
1.8 1.8
V T+ – VT– – Hysteresis – V

1.6 1.6
Positive-Going Threshold Voltage, VT+
Threshold Voltage -– V

1.4 1.4

1.2 1.2

1.0 1.0

0.8 0.8
Negative-Going Threshold Voltage, VT–
0.6 0.6

0.4 0.4

0.2 0.2

0 0
4.5 4.75 5 5.25 5.5 4.5 4.75 5 5.25 5.5
VT+ – VT– – Hysteresis – mV VCC – Supply Voltage – V

Figure 5. Threshold Voltages vs Supply Voltage Figure 6. Hysteresis vs Supply Voltage

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SNx414 Circuits (continued)

4
VCC = 5 V
TA = 25°C
VT– VT+

VO – Output Voltage – V
2

0
0 0.4 0.8 1.2 1.6 2
VCC – Supply Voltage – V

Figure 7. Output Voltage vs Input Voltage

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6.7.2 SNx4LS14 Circuits

Data for temperatures below 0°C and above 70°C and supply voltage below 4.75 V and above 5.25 V are
applicable for SNx4LS14 only.

1.70 0.90
VCC = 5 V VCC = 5 V

VT– – Negative-Going Threshold Voltage – V

V T+ – Positive-Going Threshold Voltage – V

1.69 0.89

1.68 0.88

1.67 0.87

1.66 0.86

1.65 0.85

1.64 0.84

1.63 0.83

1.62 0.82

1.61 0.81

1.60 0.80
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
TA – Free-Air Temperature –°C TA – Free-Air Temperature –°C

Figure 8. Positive-Going Threshold Voltage Figure 9. Negative-Going Threshold Voltage

vs Free-Air Temperature vs Free-Air Temperature

850
VCC = 5 V VCC = 5 V
840 TA = 25°C

Relative Frequency of Occurence

830
V T+ – VT– – Hysteresis – V

820

810

800

790

780
99% ARE
770 ABOVE
735 mV
760

750
–75 –50 –25 0 25 50 75 100 125 720 740 760 780 800 820 840 860 880
TA – Free-Air Temperature –°C VT+ – VT– – Hysteresis – mV

Figure 10. Hysteresis vs Free-Air Temperature Figure 11. Distribution of Units for Hysteresis
2.0 4
VCC = 5 V
TA = 25°C
1.8 TA = 25°C
VT– VT+
1.6
Positive-Going Threshold Voltage, VT+ 3
VO – Output Voltage – V
Threshold Voltage – V

1.4

1.2

1.0 Negative-Going Threshold Voltage, VT– 2

0.8
Hysteresis, VT+ – VT–
0.6
1
0.4

0.2

0 0
4.5 4.75 5 5.25 5.5 0 0.4 0.8 1.2 1.6 2
VCC – Supply Voltage – V VI – Input Voltage – V

Figure 12. Threshold Voltages and Hysteresis Figure 13. Output Voltage vs Input Voltage
vs Supply Voltage

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7 Parameter Measurement Information

7.1 Series SN5414 and SN7414 Devices
Test VCC
Point VCC

RL
RL
From Output Test
From Output Under Test Point
Under Test CL
CL

Figure 14. Load Circuit For Figure 15. Load Circuit For
2-State Totem-Pole Outputs Open-Collector Outputs
VCC High-Level
Test RL 1.5 V 1.5 V
Pulse
Point S1
From Output tw
Under Test
Low-Level
CL 1.5 V 1.5 V
Pulse
1 kΩ

S2

Figure 16. Load Circuit For 3-State Outputs Figure 17. Voltage Waveforms Pulse Durations
3V 3V
Timing
1.5 V Input 1.5 V 1.5 V
Input
0V 0V
th
tsu tPLH tPHL
3V In-Phase
Data VOH
1.5 V 1.5 V Output 1.5 V 1.5 V
Input
0V
VOL

tPHL tPLH

Out-of-Phase VOH
Output 1.5 V 1.5 V
VOL

Figure 18. Voltage Waveforms Figure 19. Voltage Waveforms

Setup and Hold Times Propagation Delay Times

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Series SN5414 and SN7414 Devices (continued)

Output 3V
Control
(low-level 1.5 V 1.5 V
enabling) 0V
tPZL tPLZ

Waveform 1 ≈1.5 V
1.5 V
VOL + 0.5 V
VOL

tPZH tPHZ
VOH
Waveform 2 VOH – 0.5 V
1.5 V
≈1.5 V

A. CL includes probe and jig capacitance.

B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the
output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open
for tPZL.
E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω ; tr and tf ≤ 7
ns for Series SN5414 and SN7414 devices and tr and tf ≤ 2.5 ns for Series SN54S14 and SN74S14 devices.
F. The outputs are measured one at a time with one input transition per measurement.

Figure 20. Voltage Waveforms Enable and Disable Times, 3-State Outputs

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7.2 Series SN54LS14 and SN74LS14 Devices

Test VCC
Point VCC

RL
RL
From Output Test
From Output Under Test Point
Under Test CL
CL

Figure 21. Load Circuit For Figure 22. Load Circuit For
2-State Totem-Pole Outputs Open-Collector Outputs
VCC High-Level
Test RL 1.3 V 1.3 V
Pulse
Point S1
From Output tw
Under Test
Low-Level
CL 1.3 V 1.3 V
Pulse
5 kΩ

S2

Figure 23. Load Circuit For 3-State Outputs Figure 24. Voltage Waveforms Pulse Durations
3V 3V
Timing
1.3 V Input 1.3 V 1.3 V
Input
0V 0V
th
tsu tPLH tPHL
3V In-Phase
Data VOH
1.3 V 1.3 V Output 1.3 V 1.3 V
Input
0V
VOL

tPHL tPLH

Out-of-Phase VOH
Output 1.3 V 1.3 V
VOL

Figure 25. Voltage Waveforms Figure 26. Voltage Waveforms

Setup and Hold Times Propagation Delay Times

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Series SN54LS14 and SN74LS14 Devices (continued)

Output 3V
Control
(low-level 1.3 V 1.3 V
enabling)
0V
tPZL tPLZ

Waveform 1 ≈1.5 V
1.3 V
VOL + 0.5 V
VOL
tPZH tPHZ
VOH
Waveform 2 VOH – 0.5 V
1.3 V
≈1.5 V

A. CL includes probe and jig capacitance.

B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the
output control.
D. S1 and S2 are closed for tPLH, tPHL, tPHZ, and tPLZ; S1 is open and S2 is closed for tPZH; S1 is closed and S2 is open
for tPZL.
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO ≈ 50 Ω, tr ≤ 1.5 ns,
tf ≤ 2.6 ns.
G. The outputs are measured one at a time with one input transition per measurement.

Figure 27. Voltage Waveforms Enable and Disable Times, 3-State Outputs

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8 Detailed Description

8.1 Overview
The SNx414 and SNx4LS14 Schmitt-Trigger devices contain six independent inverters. They perform the
Boolean function Y = A in positive logic.
Schmitt-Trigger inputs are designed to provide a minimum separation between positive and negative switching
thresholds. This allows for noisy or slow inputs that would cause problems such as oscillation or excessive
current draw with normal CMOS inputs.

8.2 Functional Block Diagram

A Y
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8.3 Feature Description

The device can operate from very slow transition edge inputs. This device has high noise immunity.

8.4 Device Functional Modes

Table 1 lists the functional modes of the SNx414 and SNx4LS14.

Table 1. Function Table

INPUT A OUTPUT Y
H L
L H

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The SNx414 and SNx4LS14 device is a Schmitt-Trigger input CMOS device that can be used for a multitude of
inverting buffer type functions. The application shown here takes advantage of the Schmitt-Trigger inputs to
produce a delay for a logic input.

9.2 Typical Application

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Figure 28. Simplified Application Schematic

9.2.1 Design Requirements

This device uses CMOS technology. Take care to avoid bus contention because it can drive currents that would
exceed maximum limits. Parallel output drive can create fast edges into light loads, so consider routing and load
conditions to prevent ringing.

9.2.2 Detailed Design Procedure

This circuit is designed around an RC network that produces a slow input to the second inverter. The RC time
constant (τ) is calculated from: τ = RC.
The delay time for this circuit is from tdelay(min) = –ln |1 – VT+(min) / VCC| τ to tdelay(max) = –ln |1 – VT+(max) / VCC| τ. It
must be noted that the delay is consistent for each device, but because the switching threshold is only ensured
between the minimum and maximum value, the output pulse length varies between devices. These values must
be calculated by using the minimum and maximum ensured VT+ values in the Electrical Characteristics.
The resistor value must be chosen such that the maximum current to and from the SNx414/SNx4LS14 is 8 mA at
5-V VCC.

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Typical Application (continued)

9.2.3 Application Curve

VCC

VT+(max)
Voltage

VT+ Typical

VT+
VT+(min)
VT
(max)
tdelay (max) ln | 1 |W
VCC VC
VT (min)
t delay (min) ln | 1 |W VOUT
VCC

0.0
t0 t0 + 2 t0 + 22 t0 + 32 t0 + 42 t0 + 52
Time
Figure 29. Ideal Capacitor Voltage and Output Voltage With Positive Switching Threshold

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9.3 System Examples

Here are some examples of various applications using the SNx414 and SNx4LS14 device.

VT+
TTL System Input VT–
CMOS

Sine-Wave
Oscillator
Output

Figure 30. TTL System Interface For Slow Input Figure 31. Pulse Shaper
Waveforms
0.1 Hz to 10 MHz

330Ω
VT+

VT–
Input
Input

Output

Figure 32. Multivibrator Figure 33. Threshold Detector

Open-Collector
Output Input

Input A Output

VT+
Point A

Output

Figure 34. Pulse Stretcher

16 Submit Documentation Feedback Copyright © 1983–2016, Texas Instruments Incorporated

Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14

 SN5414, SN54LS14, SN7414, SN74LS14
www.ti.com SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. The VCC terminal must have a good bypass capacitor to prevent power
disturbance. TI recommends using a 0.1-µF capacitor on the VCC terminal, and must be placed as close as
possible to the pin for best results.

11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices, inputs must never float. In many cases, functions or parts of functions of
digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only
three of the four buffer gates are used. Such inputs must not be left unconnected because the undefined
voltages at the outside connections result in undefined operational states. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they are tied to GND or
VCC, whichever makes more sense or is more convenient. Floating outputs are generally acceptable, unless the
part is a transceiver.

11.2 Layout Example

Vcc
Input

Unused Input Output Output

Unused Input

Input

Figure 35. Layout Diagram

Copyright © 1983–2016, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14
SN5414, SN54LS14, SN7414, SN74LS14
SDLS049C – DECEMBER 1983 – REVISED NOVEMBER 2016 www.ti.com

12 Device and Documentation Support

12.1 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.

Table 2. Related Links

TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY
DOCUMENTS SOFTWARE COMMUNITY
SN5414 Click here Click here Click here Click here Click here
SN54LS14 Click here Click here Click here Click here Click here
SN7414 Click here Click here Click here Click here Click here
SN74LS14 Click here Click here Click here Click here Click here

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

18 Submit Documentation Feedback Copyright © 1983–2016, Texas Instruments Incorporated

Product Folder Links: SN5414 SN54LS14 SN7414 SN74LS14

 PACKAGE OPTION ADDENDUM

www.ti.com 4-Sep-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-9665801Q2A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9665801Q2A
SNJ54LS
14FK
5962-9665801QCA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9665801QC Samples
& Green A
SNJ54LS14J
5962-9665801QDA ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9665801QD Samples
& Green A
SNJ54LS14W
5962-9665801VDA ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9665801VD Samples
& Green A
SNV54LS14W
JM38510/31302BCA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 31302BCA
M38510/31302BCA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 31302BCA
SN5414J ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SN5414J Samples
& Green
SN54LS14J ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SN54LS14J Samples
& Green
SN7414D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7414 Samples

SN7414DG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7414 Samples

SN7414DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 7414 Samples

SN7414N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN7414N Samples

SN7414NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 SN7414 Samples

SN74LS14D ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS14 Samples

SN74LS14DBR ACTIVE SSOP DB 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS14 Samples

SN74LS14DE4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS14 Samples

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 4-Sep-2022

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SN74LS14DG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS14 Samples

SN74LS14DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS14 Samples

SN74LS14DRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS14 Samples

SN74LS14DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 LS14 Samples

SN74LS14N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74LS14N Samples

SN74LS14NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type 0 to 70 SN74LS14N Samples

SN74LS14NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 74LS14 Samples

SNJ5414J ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SNJ5414J Samples
& Green
SNJ5414W ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SNJ5414W Samples
& Green
SNJ54LS14FK ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 9665801Q2A
SNJ54LS
14FK
SNJ54LS14J ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9665801QC Samples
& Green A
SNJ54LS14J
SNJ54LS14W ACTIVE CFP W 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-9665801QD Samples
& Green A
SNJ54LS14W

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 4-Sep-2022

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN5414, SN54LS14, SN54LS14-SP, SN7414, SN74LS14 :

• Catalog : SN7414, SN74LS14, SN54LS14

• Military : SN5414, SN54LS14
• Space : SN54LS14-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN7414DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN7414NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74LS14DBR SSOP DB 14 2000 330.0 16.4 8.35 6.6 2.4 12.0 16.0 Q1
SN74LS14DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74LS14NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN7414DR SOIC D 14 2500 356.0 356.0 35.0
SN7414NSR SO NS 14 2000 356.0 356.0 35.0
SN74LS14DBR SSOP DB 14 2000 356.0 356.0 35.0
SN74LS14DR SOIC D 14 2500 356.0 356.0 35.0
SN74LS14NSR SO NS 14 2000 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-9665801Q2A FK LCCC 20 1 506.98 12.06 2030 NA
5962-9665801QDA W CFP 14 1 506.98 26.16 6220 NA
5962-9665801VDA W CFP 14 1 506.98 26.16 6220 NA
SN7414D D SOIC 14 50 506.6 8 3940 4.32
SN7414DG4 D SOIC 14 50 506.6 8 3940 4.32
SN7414N N PDIP 14 25 506 13.97 11230 4.32
SN7414N N PDIP 14 25 506 13.97 11230 4.32
SN74LS14D D SOIC 14 50 506.6 8 3940 4.32
SN74LS14DE4 D SOIC 14 50 506.6 8 3940 4.32
SN74LS14DG4 D SOIC 14 50 506.6 8 3940 4.32
SN74LS14N N PDIP 14 25 506 13.97 11230 4.32
SN74LS14N N PDIP 14 25 506 13.97 11230 4.32
SN74LS14NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74LS14NE4 N PDIP 14 25 506 13.97 11230 4.32
SNJ5414W W CFP 14 1 506.98 26.16 6220 NA
SNJ54LS14FK FK LCCC 20 1 506.98 12.06 2030 NA
SNJ54LS14W W CFP 14 1 506.98 26.16 6220 NA

Pack Materials-Page 3
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
 MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38
0,65 0,15 M
0,22
28 15

0,25
0,09
5,60 8,20
5,00 7,40

Gage Plane

1 14 0,25

A 0°–ā8° 0,95
0,55

Seating Plane

2,00 MAX 0,05 MIN 0,10

PINS **
14 16 20 24 28 30 38
DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90

A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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