VLSI Physical Design with Timing Analysis

Lecture – 29: Introduction to Placement

Bishnu Prasad Das

Department of Electronics and Communication Engineering

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 Contents
• Introduction

• Levels of placement

• Problem formulation

• Design style-specific placement problems

• Classification of placement algorithms

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 Introduction to placement
• Physical design flow:

Placement

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 Levels of placement
• The placement of the block occurs at three different levels:

– System level placement

– Board level placement

– Chip level placement

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 Levels of placement
• System level placement:

– Place all the PCBs together so that the area occupied is minimal.

– The system might malfunction due to overheating of some

components.

– So, the heat generated by each of the PCBs

should be dissipated properly.

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 Levels of placement
• Board level placement:

– Involves arranging all the chips and solid-state devices on a

PCB within a fixed area.

– The components are typically in fixed, rectangular blocks, and

some blocks may already be pre-placed.

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 Levels of placement
• Board level placement:
– There is no specific limit on the number of routing layers in the PCB.
– The primary objectives of board-level placement algorithms are:
1. Minimizing the number of routing layers to optimize signal
routing.
2. Meeting system performance requirements,
especially for high-performance circuits.

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 Levels of placement
• Board level placement:

– Heat dissipation should be uniform across the board.

– Chips generating maximum heat should not be placed too

close to each other to avoid overheating.

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 Levels of placement
• Chip level placement:
– A key distinction from board-level placement is the

• limited number of routing layers available for connections within

a chip.

• Fabricated only on one side of the substrate

⇒ some ‘bad’ placements may be unroutable.

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 Levels of placement
• Chip level placement:

– Accurate determination of routing areas in chip-level

placement is crucial.

– The main objective is to find the smallest possible area for a

placement that is routable.

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 Problem Formulation
• Given

– A set of blocks with well-defined shapes, Pin locations, A netlist

• The placement problem can be stated as follows:

– construct a layout indicating the positions of each block such that

• all the nets can be routed and

• the total layout area is minimized.

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 Problem Formulation
• Performance (timing) driven placement problem:

– The main objective is to minimize the total delay of the

system.

– This is achieved by minimizing the length of the critical paths.

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 Problem Formulation
• The quality of a placement is based on several factors:

– layout area.

– completion of routing, and

– circuit performance.

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 Problem Formulation

Picture source: Naveed A. Sherwani, Algorithms for VLSI Physical Design Automation

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 Problem Formulation
• Let B1, B2,…Bn be the blocks to be placed on the chip.

• Bi is associated with height hi, width wi.

• Denote the estimated length of net Ni, 1 ≤ i ≤ m.

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 Problem Formulation
• The placement problem is to find iso-oriented rectangles for each
of these blocks on the plane denoted by R = {R1, R2,…Rn} such
that:

1. No two rectangles overlap, i.e., Ri ∩ Rj = ϕ, 1 ≤ i,j ≤ n.

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 Problem Formulation
2. Placement is routable, i.e., Q j; 1 ≤ j ≤ k, is sufficient to route
all the nets. Where,

• Q = {Q1, Q2,…Qk} represent rectangular

empty areas allocated for routing between blocks.

3. The total area of the rectangle bounding

R and Q is minimized.

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 Problem Formulation

4. The total wire length, that is, σ𝒎

𝒊=𝟏 Li is minimized.

Where,

• N = {N1, N2,…Nm} be the set of nets representing the

interconnection between different blocks.

• Li is the length of the net Ni.

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 Problem Formulation
5. In the case of high-performance circuits, the length of
longest net max {Li | i = 1,..,m} is minimized.

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 Design style-specific placement problems
• Full custom design style:

– The placement problem is same as the packing problem.

– No restrictions on block placement, except that no two blocks may

overlap.

– Irregular block shapes can lead to unused areas.

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 Design style-specific placement problems
• Standard cells:
– Simpler than full custom placement, as cells have a uniform height.
– Cells are placed in rows. Minimizing layout area is equivalent to
• Minimizing the summation of channel heights
• Minimizing the width of the widest row.
– All rows should have equal widths to reduce
overall area.

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 Design style-specific placement problems
• Standard cells:

– Total area includes cell row and routing (channel) area.

– With over-the-cell routing, channels in standard cells have

almost disappeared, leading to channel-less designs.

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 Design style-specific placement problems
• Gate arrays:

– Partitioning and placement are essentially the same in this design style.

– Placement algorithm assigns subcircuits/gates to slots on the gate array.

– Goal: Assign each block to a slot, ensuring

• no two blocks share the same slot, and

• the placement is routable.

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 Classification of placement algorithms
Partitioning

Based on the process: Based on output: Based on input:

Simulation-Based Algorithms Deterministic Algorithms Constructive Placement
Partitioning-Based Algorithms Probabilistic Algorithms Iterative Improvement
Other Placement Algorithms

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 Classification based on input
– Constructive placement:
• Input consists of a set of blocks along with the netlist.
• The algorithm finds the locations of blocks.
– Iterative improvement:
• Start with an initial placement.
• modify the initial placement in search of a
better placement.

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 Classification based on output
• Deterministic placement algorithms:

– Functions on the basis of fixed connectivity rules or

– Determine the placement by solving simultaneous equations

that are deterministic.

– Always produce the same result for a

particular placement problem.

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 Classification based on output
• Probabilistic placement algorithms:

– works by randomly examining configurations.

– may produce a different result for the same problem.

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 Classification based on process
• Simulation-based algorithms:
– Simulation-based algorithms simulate some natural
phenomenon.
– There are three major algorithms in this class:
• simulated annealing
• simulated evolution
• force-directed placement

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 Classification based on process
• Partitioning-based algorithms:

– The netlist and the layout are divided into smaller sub-netlists
and sub-regions.

– This process is repeated until each sub-netlist and sub-region

is small enough to be handled optimally.

– Examples include Min-cut placement.

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 Classification based on process
• Other placement algorithms:
– The algorithms which use clustering and other approaches are
classified under ‘other’ placement algorithms.
– Examples include:
• Cluster Growth
• Quadratic Assignment
• Resistive Network Optimization

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Thank You

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