HIGH POWER INVERTERS

TWO LEVEL INVERTERS

NAME : U D AYA B H A S K E R M A N T H AT I
D E S I G N AT I O N : A S S O C I AT E P R O F E S S O R
D E PA R T M E N T: E L E C T R I C A L E N G I N E E R I N G
CONTENT
Introduction
Principle of Operation
Classification of Inverters
Half Bridge Inverters
Full Bridge Inverters
Applications
3-Ph,2-Level VSI Schemes
PWM switching Techniques
Problems

2
INTRODUCTION
An a.c. output is synthesized from a d.c. input by closing and opening the
switches in an appropriate sequence.

Switching transition times must be accommodated in the control of the

switches. Overlap of switch ‘ON’ times will result in a short circuit, sometimes
called a shoot through fault, across the DC voltage source.

The current waveform in the load depends on the load components. For the
resistive load, the current waveform matches the shape of the output voltage.

An inductive load will have a current that has more of a sinusoidal quality than
the voltage because of the filtering property of the inductance.

3
Classification of Inverters
1. Single phase inverters and 2. Three phase inverters

An inverter is called a voltage fed inverter (VFI) if the input

voltage remains constant.

A current fed inverter (CFI) if the input current is

maintained constant.

A variable dc linked inverter if the input voltage is

controllable.

4
Low and medium power applications, square wave or quasi square
wave voltage may be acceptable. For high power applications, low
distorted sinusoidal waveforms are required.
Applications: 1. Adjustable speed a.c. motor drives.
2.Uninterruptable power supplies,
3. Induction heating.
4. Running A.C. appliances from an automobile battery
5. Electric Vehicles
6. Control and Protection
Typical 1-ph o/p’s are: i) 220V/380V at 50Hz
ii) 120V/208V at 60Hz
iii) 115V/200V at 400Hz
Inverters use PWM control signals for producing an AC output voltage.

5
 Half Bridge Inverter
The voltage across the load at any given instant
is dependent on the switch position. Two levels
either Vdc or 0V. As the o/p voltage swings b/w
0 and Vdc, it contains a finite non-zero average
value.
For inductive loads, the internal body diode of
the IGBT provides the inductive energy free
wheeling path.
Battery,
Fuel Cell, rms output voltage
solar, other
The instantaneous output voltage can be
DC source
expressed in F.S. as

6
 For n=1, the rms value of fundamental component ,

For RL load, the instantaneous load current

Fundamental output power,

7
Total Harmonic Distortion (THD): It is a measure of closeness in shape
between a waveform and its fundamental component

Distortion Factor (DF): It is a measure of effectiveness in reducing unwanted

harmonics without having to specify the values of a second order load filter

DF of an individual (or nth) harmonic component

8
Square Wave Inverter
Switches Closed O/P voltage
S1 and S2 +Vdc
S3 and S4 -Vdc
S1 and S3 0
S2 and S4 0

+Vdc, -Vdc , 0

9
Square Wave Inverter
+Vdc and –Vdc produces a square wave voltage across the load. Although this
alternating output is non sinusoidal, it may be an adequate a.c. waveform for
some applications.

A full bridge inverter must be capable of carrying both positive and negative
currents for RL loads.

10
11
PERFORMANCE PARAMETERS
OF INVERTERS
Frequency Modulation Ratio (mf)

Increasing the carrier frequency increases the frequency at which the harmonics
occur.
A disadvantage of high switching frequency is higher losses in the switches used
to implement the inverter.
Amplitude Modulation Ratio (ma)

If ma≤1, the amplitude of the fundamental frequency of the output voltage V1

is linearly proportional to ma. i.e. V1= maVdc
ma can be varied to change the amplitude of the output. If ma>1, the
amplitude of the o/p increases with ma, but not linearly.

12
PWM SWITCHING TECHNIQUES
1. Unipolar voltage switching
2. Bipolar voltage switching
The uni polar switching results in a better o/p voltage waveform and better
frequency response. Since the effective switching frequency of the output
voltage waveform is doubled and the ripple is reduced.

13
Uni polar Switching

The triangular carrier waveform is compared with two reference

signals which are positive and negative signal.

14
Bipolar Switching

15
Unipolar voltage switching scheme has better harmonic profile
compare to bipolar voltage switching.
The output is switched either from high to zero and low to zero,
rather than between high and low as in bipolar switching

16
3-PHASE, 2-LEVEL VOLTAGE
SOURCE INVERTERS
Objectives of PWM Techniques:
1. One must be able to exercise control over the magnitude and
frequency of the fundamental component to suit the control objectives.
2. The spectral performance (THD) should be acceptable.
3. Good utilization of DC supplies voltage possibly a high voltage gain.

17
PWM Switching Techniques
1. Quasi Square wave PWM
2. Multiple Pulse PWM
3. Selective Harmonic Elimination Techniques
4. Sine-Triangle Modulation
5. Space Vector Modulation

18
Sine-Triangle Modulation

19
Space Vector PWM
1. Space Vector PWM refers to a special switching scheme of the six
power transistors of a 3-Phase power converter.
2. It generates minimum harmonic distortion to the currents in the
windings of a 3-phase AC motor.
3. It also provides more efficient use of supply voltage in comparison
with the sinusoidal modulation method.

20
 Space Vector Modulation of
Tw0-level Inverter

7 & 8 states are known as NULL VECTORS and the others

are known as ACTIVE VECTORS
21
Space Vector Calculations

22
Advantages of Space Vector
Modulation
1. The switching is automatic
2. No need of sector identification.
3.Depends only on the magnitudes of
instantaneous three phase reference voltages.

23
A single phase half bridge inverter has a resistive
load of R =2.4 Ohm and DC input voltage is 48V.
Determine a) the rms output voltage at the
fundamental frequency b) the output power c)
the average and peak currents of each transistor
d) the peak reverse blocking voltage of each
transistor d) the total THD f) Distortion Factor

24
 The full-bridge inverter is used to produce a 60Hz voltage across a
series RL load using bipolar PWM. The dc input to the bridge is
100V, the amplitude modulation ration is 0.8 and the frequency
modulation ratio is 21. The load has a resistance of R= 100Ohm and
series inductance L =20mH. Determine a) the amplitude of the 60Hz
component of the output voltage and load current b) the power
absorbed by the load resistor and c) the THD of the load current.
Fourier co-efficients (Vn/VDC) are as follows:
ma= 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
n=1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1
n = mf 0.6 0.71 0.82 0.92 1.01 1.08 1.15 1.2 1.24 1.27
n = mf 0.32 0.27 0.22 0.17 0.13 0.09 0.06 0.03 0.02 0
±2

25
THANK YOU

26
MULTI LEVEL INVERTER
TOPOLOGIES

Dr. Udaya Bhasker M

Associate Professor, EED
 Introduction
Introduction
❖Levels that were obtained from earlier inverters were
+VDC, 0, -VDC.
❖One of the basic problems in power conversion is the
harmonic content in the output voltage and current.
❖Harmonics can be minimized either by increasing the
number of voltage levels or by using appropriate
modulation techniques.
❖In this presentation, different PWM Techniques has
been used for comparison purpose.
❖These multi-level inverters are useful in Renewable
energy integrated with grid, electric drives, etc.
 Introduction
❖ MULTILEVEL INVERTERS involves utilizing a higher number
of active semiconductor switches to perform the power
conversion in small voltage steps.
❖ Multilevel inverter (MLI)
✓Produces high power and high output voltage.
✓Eliminates the need for step-up transformer and
reduce harmonics produced by the inverter.
✓Has the advantage of clamping the voltages, which
prevents the need of fast switching.
✓Can be used in reactive power compensation.
✓Can also be used in renewable energy application,
adjustable speed motor drives, etc..,
✓ High power medium voltage drives, MV of 3300V a 9-
level inverter can be used.
 Harmonic Issues

❖ The total harmonic distortion (THD): It is a measure of

closeness in shape between the waveform and its
fundamental components and it is defined as

❖ Harmonics is undesirable and may result

– Pulsating torque
– Heating in motors
– Oscillations
– Interference
– Failure or damage of electric components in power system
 Objective
• To get seven level output voltage using
cascaded multilevel inverter.
• To compare different modulation techniques.
• To minimize the THD value of the output.
Types of MLIs:
o Flying Capacitor Multilevel Inverter
o Neutral Point Voltage Clamping inverter
o Cascaded H-bridge Multilevel Inverter
Flying-Capacitor Multilevel Inverters
Features:
❖Requires large number of
capacitors. For m-level inverter
(m-1)(m-2)/2 capacitors are
required.
❖Selection of the switch
combination is complicated.
❖Therefore, the switching
frequency needs to be higher
than the fundamental frequency.
 Diode-Clamped Multilevel Inverters

Features:
❖Requires different voltage ratings for blocking diodes.
❖Unequal switching device rating. Switching Switching conditions Output
❖Needs capacitor voltage balancing Symbols S11 S12 S13 S14 Voltage
❖Requires (m-1) DC-link Capacitors
❖(m-1)(m-2) Clamping Diodes P ON ON OFF OFF Vdc/2

O OFF ON ON OFF 0

N OFF OFF ON ON Vdc/2

 Cascaded H-Bridge Multilevel inverter

1. The H-bridge cells are normally connected in cascade

on their ac side to achieve medium voltage operation
and low harmonic distortion.
2. The inverter phase voltage VAN may not be
necessarily equal the load phase voltage VAO.
3. CHB requires a number of isolated DC supplies, each
of which feeds an H-bridge power cell.
4. The number of voltage levels in a CHB can be found
from m =(2H+1)
H: number of H-bridge cells per phase leg
m: is always an odd number.
…cont’d
Conducting Output
Switches Voltage (VAB)
S1 and S4 +Vdc
S2 and S3 -Vdc
S1 and S2 or
0
S3 and S4
…cont’d
• The rule here is the switching has to be
diagonal i.e. (S1 and S2) or (S2 and S3) to
prevent short circuit
• when the switch is turned on, it may conduct
or not conduct a current, depending on the
direction of the output current.
 Cascaded multi-level inverter with
two sources
➢ Two cascaded H-bridges are considered with two independent sources.
➢ These two source inverter has levels: +2VDC, +VDC, 0, -VDC, -2VDC as shown in
following figure.
Waveforms
• The total output voltage (Vo) is expressed by
the following Fourier series with odd
harmonics as

• The Fourier coefficients are

➢Amplitude modulation (Mi) index is expressed
as the ratio of fundamental component of Vo
to that of a square wave of amplitude 2VDC.

➢Certain harmonics can be eliminated by

proper selection of α1 and α2.
➢For eliminating mth harmonic using the delay
angles and maintaining particular amplitude
modulation index (Mi), following equations
are required:

Solve the above equations by iterative method.

H-Bridge Cascaded Multilevel inverter

The proposed inverter is 7-level Cascaded Multilevel Inverter

(CMLI).
❖Consists of a series of H-bridges.
❖The function is to synthesize several SDCS.
❖Does not require any clamping and flying capacitors.
Main Features:
✓It is well suited for renewable harvesting
✓Least number of Components
✓Easy to implement since each H-bridge has the same
structure.

Conducting Output Voltage

Switches (VAB)
S1 and S4 +Vdc
S2 and S3 -Vdc
S1 and S2 or
0
S3 and S4
 HIGH POWER INVERTERS
MULTI LEVEL INVERTERS

NAME : U D AYA B H A S K E R M A N T H AT I
D E S I G N AT I O N : A S S O C I AT E P R O F E S S O R
D E PA R T M E N T: E L E C T R I C A L E N G I N E E R I N G
Cascaded H-Bridge Inverter
The H-bridge cells are normally connected in cascade on their ac side
to achieve medium voltage operation and low harmonic distortion.
The inverter phase voltage VAN may not be necessarily equal the
load phase voltage VAO.
CHB requires a number of isolated DC supplies, each of which feeds
an H-bridge power cell.

The number of voltage levels in a CHB can be found from m =(2H+1)

H: number of H-bridge cells per phase leg
m: is always an odd number.

2
Comparison Table
m: number of levels

S.No. CHB Diode Clamp NPC FC

1 m = (2H+1) Nsw = 6(m-1) (m-1) DC –link
H:number of H-bridge Capacitors
cells per phase
2 Nsw= 6(m-1) Clamping Diodes Capacitors per phase
3(m-1)(m-2) (m-1)(m-2)/2
DC capacitors (m-1) Phase redundancies

3
Diode-Clamped Multilevel Inverters
It employs clamping diodes and cascaded DC-
capacitors to produce AC voltage waveforms with
multiple levels.
It has the advantage of using a single DC source
rather than multiple sources. The DC input voltage
of the inverter is normally split by two cascaded
DC capacitors, providing a floating neutral point.
In this circuit, the DC voltage source is connected
to a pair of series capacitors each charged to
Vdc/2.
4
 Diode-Clamped Multilevel Inverters

Features:
❖Requires different voltage ratings for blocking diodes.
❖Unequal switching device rating. Switching Switching conditions Output
❖Needs capacitor voltage balancing Symbols S11 S12 S13 S14 Voltage
❖Requires (m-1) DC-link Capacitors
❖3(m-1)(m-2) Clamping Diodes P ON ON OFF OFF Vdc/2

O OFF ON ON OFF 0

N OFF OFF ON ON Vdc/2

The inverter leg ‘A’ is composed of four active switches S1
to S4 with four anti parallel diodes D1 to D4.

The DC bus capacitor is split into two, providing a neutral

point ‘Z’. The diodes connected to the neutral point, Dz1
and Dz2 are the clamping diodes.

When s2 and s3 are ON, the inverter output terminal ‘A’ is

connected to the neutral point through one of the
clamping diodes.

6
For each of these circuits, two switches
are open and the voltage of the source
divides between the two, thus reducing
the voltage stress across each switch
compared to the H-bridge circuit.

The output is the difference of the

voltages between each half bridge,
resulting in the three levels.

More output voltage levels are achieved

with additional capacitors and switches.
7
Flying-Capacitor Multilevel Inverters
Features:
❖Requires large number of
capacitors. For m-level inverter (m-
1)(m-2)/2 capacitors are required.
❖Selection of the switch
combination is complicated.
❖Therefore, the switching
frequency needs to be higher
than the fundamental frequency.
Flying capacitor MLI
It requires capacitor to be pre
charged.
They are called flying capacitor MLI,
because the capacitors float w.r.to
earth’s potential.
Every inverter limb consists of cells
connected in inward nested series.
An inverter with N cell will have 2N
switches and (N+1) different voltage
levels.
9
Switching Strategy
To synthesize sinusoidal waveform at the output, switching
strategy needs to be defined. Every voltage is applied at
output with a certain electrical angle. Careful application of
the angle gives low harmonic distortion and required
amplitude at the output. More than one switching
strategies are available for a single voltage level. Three
conditions to be followed for right choice
1. For every change in the state, only one switch shift
should be allowed.
2. Capacitors voltage balance should be maintained
3. All the switching devices be used equally.

10
 SELECTIVE HARMONIC ELIMIATION
➢Some selected harmonics could be eliminated from
the inverter output voltage by introducing notches at
suitable time instants in the pole voltage waveform.
➢The notch angles to be calculated offline using
digital computer and later used for generating the
switching sequence.
➢The notch angle information for all three phases
taken together can be converted into a matrix of
switching word for the inverter.
➢The switching word information is then converted
into gate control signals for the inverter switches.
11
SPACE VECTOR MODULATION
The switching state redundancy is a common phenomenon in multilevel
converters. It provides a great flexibility for switching pattern design, especially
for SVM schemes.

During each time period of the phase voltages six discrete time instants can be
identified, when one of the phase voltages have maximum positive or negative
instantaneous magnitude.

At these six discrete instants, these vectors are aligned along the phase axes
having maximum instantaneous voltage.

The magnitude of these voltage vectors is 1.5 times the peak magnitude of
individual phase voltage.

12
Vector A+ B+ C+ A- B- C- VAB VBC VCA
V0={000} OFF OFF OFF ON ON ON 0 0 0
V1={100} ON OFF OFF OFF ON ON +VDC 0 -VDC
V2={110} ON ON OFF OFF OFF ON 0 +VDC -VDC
V3={010} OFF ON OFF ON OFF ON -VDC +VDC 0
V4={011} OFF ON ON ON OFF OFF -VDC 0 +VDC
V5={001} OFF OFF ON ON ON OFF 0 -VDC +VDC
V6={101} ON OFF ON OFF ON OFF +VDC -VDC 0
V7={111} ON ON ON OFF OFF OFF 0 0 0

13
 rd
3 harmonic PWM Technique
THIPWM: It is a modification over the SPWM technique, wherein deliberately
some amount of third harmonic voltage is introduced in the pole voltage
waveform.
Resultant waveform is compared with the high frequency triangular carrier
waveform. However, the third harmonic component of pole voltage will not
appear in the load phase and line voltages.

Higher output voltage is achieved without compromising on the quality of the

output waveform.

The fundamental voltage output can be higher than a simple SPWM inverter.

14
THANK YOU

15
 HIGH POWER INVERTERS
DIODE CLAMPED MULTI LEVEL
INVERTER

NAME : U D AYA B H A S K E R M A N T H AT I
D E S I G N AT I O N : A S S O C I AT E P R O F E S S O R
D E PA R T M E N T: E L E C T R I C A L E N G I N E E R I N G
Comparison Table
m: number of levels

S.No. CHB Diode Clamp NPC FC

1 m = (2H+1) Nsw = 6(m-1) (m-1) DC –link
H:number of H-bridge Capacitors
cells per phase
2 Nsw= 6(m-1) Clamping Diodes Capacitors per phase
3(m-1)(m-2) (m-1)(m-2)/2
DC capacitors (m-1) Phase redundancies

2
 Diode-Clamped Multilevel Inverters
1. It employs clamping diodes and cascaded DC-link
capacitors to produce AC voltage waveforms with
multiple levels.

2. It has the advantage of using a single DC source rather

than multiple sources. The DC input voltage of the
inverter is normally split by two cascaded DC capacitors,
providing a floating neutral point.

3. The DC voltage source is connected to a pair of series

capacitors each charged to Vdc/2.
3
 Three level Diode-Clamped MLI

Features:
❖Requires different voltage ratings for blocking diodes.
❖Unequal switching device rating.
❖Needs capacitor voltage balancing
The inverter leg ‘A’ is composed of four active switches S1
to S4 with four anti parallel diodes D1 to D4.

The DC bus capacitor is split into two, providing a neutral

point ‘Z’. The diodes connected to the neutral point, Dz1
and Dz2 are the clamping diodes.

When s2 and s3 are ON, the inverter output terminal ‘A’ is

connected to the neutral point through one of the
clamping diodes.

5
For each of these circuits, two switches
are open and the voltage of the source
divides between the two, thus reducing
the voltage stress across each to half of
the source voltage.

The output is the difference of the

voltages between each half bridge,
resulting in the three levels.

6
Gating Pulses to Three level
Inverter

7
8
9
Topoloy of the Diode-Clamped Inverter for
I) Two Level, II) Three-level III) Four-level
and IV) Five-Level Inverter

10
Schematic of the n-level diode-
clamped converter

Line Voltage waveform for an n-level DCMLI

11
Calculate the number of active switches,
clamping diodes and DC-Link capacitors
with the voltage levels of 3,4,5 and 6 using
DCMLI

12
THANK YOU

13
 HIGH POWER INVERTERS
DIODE CLAMPED MULTI LEVEL
INVERTER

NAME : U D AYA B H A S K E R M A N T H AT I
D E S I G N AT I O N : A S S O C I AT E P R O F E S S O R
D E PA R T M E N T: E L E C T R I C A L E N G I N E E R I N G
Comparison Table
m: number of levels

S.No. CHB Diode Clamp NPC FC

1 m = (2H+1) Nsw = 6(m-1) (m-1) DC –link
H:number of H-bridge Capacitors
cells per phase
2 Nsw= 6(m-1) Clamping Diodes Capacitors per phase
3(m-1)(m-2) (m-1)(m-2)/2
DC capacitors (m-1) Phase redundancies

2
 Diode-Clamped Multilevel Inverters
1. It employs clamping diodes and cascaded DC-link
capacitors to produce AC voltage waveforms with
multiple levels.

2. It has the advantage of using a single DC source rather

than multiple sources. The DC input voltage of the
inverter is normally split by two cascaded DC capacitors,
providing a floating neutral point.

3. The DC voltage source is connected to a pair of series

capacitors each charged to Vdc/2.
3
 Three level Diode-Clamped MLI

Features:
❖Requires different voltage ratings for blocking diodes.
❖Unequal switching device rating.
❖Needs capacitor voltage balancing
The inverter leg ‘A’ is composed of four active switches S1
to S4 with four anti parallel diodes D1 to D4.

The DC bus capacitor is split into two, providing a neutral

point ‘Z’. The diodes connected to the neutral point, Dz1
and Dz2 are the clamping diodes.

When s2 and s3 are ON, the inverter output terminal ‘A’ is

connected to the neutral point through one of the
clamping diodes.

5
For each of these circuits, two switches
are open and the voltage of the source
divides between the two, thus reducing
the voltage stress across each to half of
the source voltage.

The output is the difference of the

voltages between each half bridge,
resulting in the three levels.

6
Gating Pulses to Three level
Inverter

7
8
9
Topoloy of the Diode-Clamped Inverter for
I) Two Level, II) Three-level III) Four-level
and IV) Five-Level Inverter

10
Schematic of the n-level diode-
clamped converter

Line Voltage waveform for an n-level DCMLI

11
Calculate the number of active switches,
clamping diodes and DC-Link capacitors
with the voltage levels of 3,4,5 and 6 using
DCMLI

12
Switching Strategy
To synthesize sinusoidal waveform at the output, switching
strategy needs to be defined. Every voltage is applied at
output with a certain electrical angle. Careful application of
the angle gives low harmonic distortion and required
amplitude at the output. More than one switching
strategies are available for a single voltage level. Three
conditions to be followed for right choice
1. For every change in the state, only one switch shift
should be allowed.
2. Capacitors voltage balance should be maintained
3. All the switching devices be used equally.

13
 Modulation Techniques
❖The main aim of modulation strategy of MLI’s is to
synthesize the output voltage as close as possible to
sinusoidal waveform.
❖It is possible to control the output voltage as well as
it’s harmonic content by using appropriate modulation
techniques
❖Many possible PWM Techniques
✓Fundamental Switching Frequency
▪SHE
▪SVC
✓High Switching Frequency such as Carrier-based
PWM and SVM
 Carrier–based sinusodal PWM
In this modulation technique sinusoidal reference
signal is compared to multiple triangular carrier signals
to produce gating signals
➢Requires (m-1) triangular carrier signals
➢The output will follow shape and frequency of
reference signal.
❖THD can be improved by adjustment of carrier signals.
❖The adjustment may be
▪Level Shifting and/or
▪Phase Shifting
❖In this modulation technique both amplitude and
frequency can be controlled.
 Carrier–based sinusodal PWM
❖In-phase Disposition: All carrier signals will have
the same phase and level-shifted.
❖Phase Opposition Disposition: All carriers are
level-shifted and all carriers above zero have and all
the other carrier signals have different phase which
1800 phase-shifted
❖Alternate Phase Opposition Disposition: Every
carrier signals level-shifted and are 1800 phase-
shifted with neighboring carrier Signal.
17
18
19
 In-phase Disposition
Carrier Signals and Reference Signals
3
Carrier Signal-1
Carrier Signal-2
Carrier Signal-3
2 Carrier Signal-4
Carrier Signal-5
Carrier Signal-6
1 VrefA
Vref/Vcarrier(V)

VrefB
VrefC

-1

-2

-3
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time(Sec)
 …cont’d Output Phase Voltage
100
Va(V)

-100
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

100
Line to Line Voltage
Vab(V)Vb(V)

200
0

-1000
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

100
-200
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Vc(V)

0
200
 Phase Opposition Disposition
Carrier andPhase
Reference Signals
Oppostion Disposition(POD)
3

1
Vref/Vcarrier(V)

-1

-2

-3
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time(Sec)
 …cont’d
Output Phase Voltage
100
Van(V)

-100
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
100
Output Line to Line Voltage
Vbn(V)

200
0
Vab(V)

0
-100
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
100
-200
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
Vcn(V)

0
200
 Alternate Phase Opposition
Disposition
Carrier Signals and Reference Signals
3
Carrier Signal-1
Carrier Signal-2
Carrier Signal-3
2 Carrier Signal-4
Carrier Signal-5
Carrier Signal-6
1 VrefA
VrefB
Vref/Vcarrier(V)

VrefC

-1

-2

-3
0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02
Time(Sec)
…cont’d
Phase to Phase Voltage
Output Phase Voltage
100
Van(V)

-100
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

100

Line to Line Voltage

Vbn(V)

0
200

-100
Vab

00 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

100
-200
Vcn(V)

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04

0 Time
200
-100
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
c
 FFT Analysis
In-Phase Disposition Phase Opposition Disposition
Fundamental (50Hz) = 154.9 , THD= 11.11%
Fundamental (50Hz) = 154.7 , THD= 16.39%
0.8 0.8

0.7 0.7
Mag (% of Fundamental)

Mag (% of Fundamental)
0.6 0.6

0.5 0.5
0.4 0.4
0.3
0.3
0.2
0.2
0.1
0.1
0
0 100 200 300 400 500 600 700 800 900 1000 0
Frequency (Hz) 0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)

Phase Opposition Disposition

Fundamental (50Hz) = 154.4 , THD= 15.33%
1

0.8
Mag (% of Fundamental)

0.6

0.4

0.2

0
0 100 200 300 400 500 600 700 800 900 1000
Frequency (Hz)
THANK YOU

27
 HIGH POWER INVERTERS
ELIMINATION OF COMMON MODE
VOLTAGE OF 3 LEVEL DCMLI

NAME : U D AYA B H A S K E R M A N T H AT I
D E S I G N AT I O N : A S S O C I AT E P R O F E S S O R
D E PA R T M E N T: E L E C T R I C A L E N G I N E E R I N G
CONTENTS
DEFINITION
DRAWBACKS
MITIGATION TECHNIQUES

2
COMMON MODE VOLTAGE
Definition: It is the voltage between neutral point of the load and
system ground.
It is produced at the time of operation in output terminal of inverter,
which are essentially zero sequence voltage superimposed with
switching noise which will appear at rectifier, inverter & motor
terminals.

3
Vag,Vbg, Vcg: Voltage between Ground to Phase
Vng: Voltage between Ground to Phase
Neutral Point Voltage variation results in generation of CMV three times
the fundamental frequency.

4
Drawbacks
The motor operates near rated speed under no load conditions, at
which the common-mode voltage reaches its highest level.
It damages the motor insulation system.
Premature failure of winding insulation.
It increases the cost.
Increases drive size and weight and high operating cost due to
transformer losses.

5
MITIGATION OF CMV
Some extra hardware circuitry such as isolation transformer OR Phase
shifting transformer, active passive filters, common mode choke & dual
active bridge configuration can mitigate CMV
THD increase with controlling CMV.

6
Choke is sufficient high such that
the DC current is ripple free.

The neutral of the filter capacitor is grounded directly or through and RC

grounding network. In a three phase balanced system, the neutral points of
the capacitor and stator winding should have the same potential.

7
8
THANK YOU

9
 HIGH POWER INVERTERS
ACTIVE-NEUTRAL-POINT-CLAMPED
MULTILEVEL INVERTER

NAME : U D AYA B H A S K E R M A N T H AT I
D E S I G N AT I O N : A S S O C I AT E P R O F E S S O R
D E PA R T M E N T: E L E C T R I C A L E N G I N E E R I N G
INTRODUCTION
The voltage balancing across the floating capacitors is achieved by
using a proper selection of redundant switching states, and the
neutral-point voltage is controlled by the classical DC offset injection.

It combines the flexibility of the multilevel floating capacitor converter

with NPC converter to generate multilevel voltages.

2
Balancing Voltage of DC-Bus
Capacitors

3
Effects of Neutral Point voltage
Oscillation

4
Advantages
It has lower current THD compared with the NPC under the same
switching frequency while the losses are higher.

5
Nsw = 6(m-1)
Clamping Diodes
3(m-1)(m-2)
DC capacitors (m-1)

6
Active-Neutral-Point-Clamped
five-level Inverter

7
8
THANK YOU