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The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum
extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL
WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF
MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether
in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising
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consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action
brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same.
Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. You may not
reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and
conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and
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http://www.xilinx.com/warranty.htm#critapps.
© Copyright 2006–2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included
herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

Revision History
The following table shows the revision history for this document.

Date Version Revision


12/05/06 1.0 Initial release.
02/26/07 1.1 Added Spartan-3AN platform.
04/02/07 1.2 Added Spartan-3A DSP platform.
02/14/08 1.3 Updated for latest package offerings. Updated and corrected descriptions and figures
throughout. Updated links for new xilinx.com navigation.
06/25/08 1.4 Added and updated links to design files. Updated banking rules in I/O section. Added
reference to XAPP459 in “Using Large-Swing Signals”.
01/21/09 1.5 Updated document to refer to Extended Spartan-3A family. Corrected column headers
CLKA and CLKB in Table 4-14 on page 181. Clarified DCM “Output Alignment” on
page 131. Added section “Spartan-3A and Spartan-3A DSP FPGA Dual-Range
VCCAUX” on page 353.

Spartan-3 Generation FPGA User Guide www.xilinx.com UG331 (v1.8) June 13, 2011

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