STM32C011x4/x6: Arm Cortex - M0+ 32-Bit MCU, 32 KB Flash, 6 KB RAM, 2 X USART, Timers, ADC, Comm. I/Fs, 2-3.6 V

STM32C011x4/x6
Arm®Cortex®-M0+ 32-bit MCU, 32 KB flash, 6 KB RAM,

2 x USART, timers, ADC, comm. I/Fs, 2-3.6 V
Datasheet - production data
Features
• Includes ST state-of-the-art patented
technology
• Core: Arm® 32-bit Cortex®-M0+ CPU,
SO8N
frequency up to 48 MHz (4.9 × 6 mm)
WLCSP12 TSSOP20 UFQFPN20
(1.70 × 1.42 mm) (6.4 × 4.4 mm) (3 × 3 mm)
• -40°C to 85°C/105°C/125°C operating
temperature
• Memories • Communication interfaces
– Up to 32 Kbytes of flash memory with – One I2C-bus interface supporting Fast-
protection mode Plus (1 Mbit/s) with extra current
– 6 Kbytes of SRAM with hardware parity sink; supporting SMBus/PMBus™ and
check wake-up from Stop mode
• CRC calculation unit – Two USARTs with master/slave
synchronous SPI; one supporting ISO7816
• Reset and power management
interface, LIN, IrDA capability, auto baud
– Voltage range: 2.0 V to 3.6 V rate detection and wake-up feature
– Power-on / power-down reset (POR/PDR) – One SPI (24 Mbit/s) with 4- to 16-bit
– Programmable brownout reset (BOR) programmable bitframe, multiplexed with
– Low-power modes: I²S interface; two extra SPIs through
Sleep, Stop, Standby, Shutdown USARTs
• Clock management • Development support: serial wire debug (SWD)
– 4 to 48 MHz crystal oscillator • All packages ECOPACK 2 compliant
– 32 kHz crystal oscillator with calibration
– Internal 48 MHz RC oscillator (±1 %) Table 1. Device summary
– Internal 32 kHz RC oscillator (±5 %) Reference Part number
• Up to 18 fast I/Os
STM32C011x4 STM32C011F4, STM32C011J4
– All mappable on external interrupt vectors
– All 5 V-tolerant STM32C011x6
STM32C011F6, STM32C011J6,
STM32C011D6
• 3-channel DMA controller with flexible mapping
• 12-bit, 0.4 µs ADC (up to 13 ext. channels)
– Conversion range: 0 to 3.6 V
• 8 timers: 16-bit for advanced motor control,
four 16-bit general-purpose, two watchdogs,
SysTick timer
• Calendar RTC with alarm
January 2024 DS13866 Rev 4 1/92

This is information on a product in full production. www.st.com
Contents STM32C011x4/x6
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 Arm® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Memory protection unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.3 Embedded flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.6 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . . . . 13
3.7 Power supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.7.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.7.5 Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.8 Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.10 General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.12 DMA request multiplexer (DMAMUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.13.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 18
3.13.2 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . 19
3.14 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.14.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.15 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.15.1 Advanced-control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15.2 General-purpose timers (TIM3, 14, 16, 17) . . . . . . . . . . . . . . . . . . . . . . 21
3.15.3 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.15.4 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/92 DS13866 Rev 4

STM32C011x4/x6 Contents
3.15.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.16 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.17 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.18 Universal synchronous/asynchronous receiver transmitter (USART) . . . 24
3.19 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.20 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.20.1 Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4 Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 26
5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 36
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 36
5.3.4 Embedded voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.6 Wake-up time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
5.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.3.9 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
5.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3.14 NRST input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.3.15 Analog-to-digital converter characteristics . . . . . . . . . . . . . . . . . . . . . . . 64
DS13866 Rev 4 3/92

4
Contents STM32C011x4/x6
5.3.16 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

5.3.17 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
5.3.18 Characteristics of communication interfaces . . . . . . . . . . . . . . . . . . . . . 70
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.1 Device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.2 SO8N package information (O7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3 WLCSP12 package information (B0EK) . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.4 TSSOP20 package information (YA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.5 UFQFPN20 package information (A0A5) . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.6.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
7 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4/92 DS13866 Rev 4

STM32C011x4/x6 List of tables
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. STM32C011x4/x6 family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Access status versus readout protection level and execution modes. . . . . . . . . . . . . . . . . 12
Table 4. Interconnect of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Internal voltage reference calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 7. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 9. USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10. SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 11. Terms and symbols used in the pin assignment table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 12. Pin assignment and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. Port A alternate function mapping (AF0 to AF7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 14. Port A alternate function mapping (AF8 to AF15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 15. Port B alternate function mapping (AF0 to AF7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 16. Port B alternate function mapping (AF8 to AF15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 17. Port C alternate function mapping (AF0 to AF7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 18. Port C alternate function mapping (AF8 to AF15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 19. Port F alternate function mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 20. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 21. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 22. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 23. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 24. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 25. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 26. Embedded internal voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 27. Current consumption in Run mode from flash memory at different die temperatures . . . . 39
Table 28. Current consumption in Run mode from SRAM at different die temperatures . . . . . . . . . . 40
Table 29. Typical current consumption in Run depending on code executed . . . . . . . . . . . . . . . . . . 41
Table 30. Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 31. Current consumption in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 32. Current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 33. Current consumption in Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 34. Current consumption of peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 35. Low-power mode wake-up times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 36. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 37. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 38. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 39. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 40. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 41. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 42. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 43. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 44. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 45. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 46. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 47. Electrical sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 48. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
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List of tables STM32C011x4/x6
Table 49. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 50. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 51. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 52. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 53. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 54. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 55. ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 56. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 57. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 58. IWDG min/max timeout period at 32 kHz LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 59. Minimum I2CCLK frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 60. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 61. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 62. I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 63. USART (SPI mode) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Table 64. SO8N -Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Table 65. WLCSP12 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Table 66. WLCSP12 - Example of PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 67. TSSOP20 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 68. UFQFPN20 – Mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 69. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 70. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6/92 DS13866 Rev 4

STM32C011x4/x6 List of figures
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 2. Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3. STM32C011JxM SO8N pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 4. STM32C011DxY WLCSP12 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 5. STM32C011FxP TSSOP20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 6. STM32C011FxU UFQFPN20 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 7. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 8. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 9. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 10. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 11. VREFINT vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 12. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 13. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 14. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 15. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 16. HSI48 frequency versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 17. I/O input characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 18. I/O AC characteristics definition(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 19. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 20. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 21. ADC typical connection diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 22. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 23. SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 24. SPI timing diagram - master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 25. I2S slave timing diagram (Philips protocol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 26. I2S master timing diagram (Philips protocol). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 27. USART timing diagram in SPI master mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Figure 28. USART timing diagram in SPI slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Figure 29. SO8N -Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 30. SO8N - Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 31. WLCSP12 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 32. WLCSP12 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 33. WLCSP12 package marking example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 34. TSSOP20 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 35. TSSOP20 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 36. UFQFPN20 – Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 37. UFQFPN20 – Footprint example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DS13866 Rev 4 7/92

7
Introduction STM32C011x4/x6
1 Introduction
This document provides information on STM32C011x4/x6 microcontrollers, such as

description, functional overview, pin assignment and definition, electrical characteristics,
packaging, and ordering codes.
For information on the device errata with respect to the datasheet and reference manual,
refer to the STM32C011x4/x6 errata sheet ES0569.
Information on memory mapping and control registers is the subject of the reference manual
RM0490.
Information on Arm®(a) Cortex®-M0+ core is available from the www.arm.com website.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
8/92 DS13866 Rev 4

STM32C011x4/x6 Description
2 Description
The STM32C011x4/x6 mainstream microcontrollers are based on high-performance

Arm® Cortex®-M0+ 32-bit RISC core operating at up to 48 MHz frequency. Offering a high
level of integration, they are suitable for a wide range of applications in consumer, industrial
and appliance domains and ready for the Internet of Things (IoT) solutions.
The devices incorporate a memory protection unit (MPU), high-speed embedded memories
(6 Kbytes of SRAM and up to 32 Kbytes of flash program memory with read and write
protection), DMA, an extensive range of system functions, enhanced I/Os, and peripherals.
The devices offer standard communication interfaces (one I2Cs, one SPI / one I2S, and two
USARTs), one 12-bit ADC (2.5 MSps) with up to 15 channels, a low-power RTC, an
advanced control PWM timer, four general-purpose 16-bit timers, two watchdog timers, and
a SysTick timer.
The devices operate within ambient temperatures from -40 to 125°C and with supply
voltages from 2.0 V to 3.6 V. Optimized dynamic consumption combined with power-saving
modes allows the design of low-power applications.
The devices are housed in packages with 8 to 20 pins.
Table 2. STM32C011x4/x6 family device features and peripheral counts

STM32C011_
Peripheral
_J4 _J6 _D6 _F4 _F6
Flash memory (Kbyte) 16 32 32 16 32
SRAM (Kbyte) 6 with parity
Advanced control 1 (16-bit)
Timers
General-purpose 4 (16-bit)
SysTick 1
Watchdog 2
SPI [I2S](1) 1 [1] + 2 extra through USARTs
interfaces
Comm.
I2C 1
USART 2
RTC / RNG / AES / VREFBUF Yes / No / No / No
GPIOs (all 5V-tolerant) 6 10 18
DMA channels 3
Wakeup pins 2 4
12-bit ADC channels (external + internal) 5+2 7+2 13 + 2
Max. CPU frequency 48 MHz
Operating voltage 2.0 to 3.6 V
Operating temperature (2) Ambient: -40 to 85 °C / -40 to 105 °C / -40 to 125 °C
Package SO8N WLCSP12 UFQFPN20
Bootloader USART1, I2C1

1. The number in brackets denotes the count of SPI interfaces configurable as I2S interface.
2. Depends on order code. Refer to Section 7: Ordering information for details.
DS13866 Rev 4 9/92

25
Description STM32C011x4/x6
Figure 1. Block diagram
SWCLK POWER
DMAMUX
SWDIO SWD Voltage
as AF
VCORE regulator
DMA
VDDIO1
CPU VDDA VDD/VDDA
CORTEX-M0+ Flash memory VSS/VSSA
Bus matrix
I/F VDD
fmax = 48 MHz up to 32 KB SUPPLY
SUPERVISION
POR
SRAM Reset POR/BOR
6 KB Parity Int NRST
NVIC IOPORT
T sensor
HSI48
RC 48 MHz
GPIOs LSI RC 32 kHz XTAL OSC

PA[14:0] Port A 4-48 MHz
HSE
decoder
PB[7,6] Port B IWDG
PC[15,14] Port C RCC LSE LSE OSCX_IN

XTAL 32 kHz
Reset & clock control OSCX_OUT
CRC
PF[2] Port F
AHB
System and RTC_OUT

RTC RTC_REFIN
peripheral
EXTI clocks RTC_TS
from peripherals AHB-to-APB

APB
13x IN ADC I/F 4 channels

TIM1
BKIN, ETR input as AF
TIM3 4 ch., ETR as AF

MOSI/SD SYSCFG
APB
MISO/MCK TIM14 1 channel as AF

SCK/CK SPI1/I2S
NSS/WS as AF
PWRCTRL TIM16 &
TIMER 17
16/17 1 channel as AF
IRTIM IR_OUT
WWDG
RX, TX, CTS, RTS

DBGMCU USART1 as AF
RX, TX, CTS, RTS
USART2 as AF
I2C1 SCL, SDA, SMBA,

as AF
Power domain of analog blocks : VDD VDDA VDDIO1

MSv65922V4
10/92 DS13866 Rev 4

STM32C011x4/x6 Functional overview
3 Functional overview
3.1 Arm® Cortex®-M0+ core with MPU

The Cortex-M0+ is an entry-level 32-bit Arm Cortex processor designed for a broad range of
embedded applications. It offers significant benefits to developers, including:
• a simple architecture, easy to learn and program
• ultra-low power, energy-efficient operation
• excellent code density
• deterministic, high-performance interrupt handling
• upward compatibility with Cortex-M processor family
• platform security robustness, with integrated Memory Protection Unit (MPU).
The Cortex-M0+ processor is built on a highly area- and power-optimized 32-bit core, with a
2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy
efficiency through a small but powerful instruction set and extensively optimized design,
providing high-end processing hardware including a single-cycle multiplier.
The Cortex-M0+ processor provides the exceptional performance expected of a modern
32-bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.
Owing to embedded Arm core, the STM32C011x4/x6 devices are compatible with Arm tools
and software.
The Cortex-M0+ is tightly coupled with a nested vectored interrupt controller (NVIC)
described in Section 3.13.1.
3.2 Memory protection unit

The memory protection unit (MPU) is used to manage the CPU accesses to memory to
prevent one task to accidentally corrupt the memory or resources used by any other active
task.
The MPU is especially helpful for applications where some critical or certified code has to be
protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-
time operating system). If a program accesses a memory location that is prohibited by the
MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can
dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.3 Embedded flash memory

STM32C011x4/x6 devices feature up to 32 Kbytes of embedded flash memory available for
storing code and data.
DS13866 Rev 4 11/92

25
Functional overview STM32C011x4/x6
Flexible protections can be configured thanks to option bytes:

• Readout protection (RDP) to protect the whole memory. Three levels are available:
– Level 0: no readout protection
– Level 1: memory readout protection: the flash memory cannot be read from or
written to if either debug features are connected, boot in RAM or bootloader is
selected
– Level 2: chip readout protection: debug features (Cortex-M0+ serial wire), boot in
RAM and bootloader selection are disabled. This selection is irreversible.
Table 3. Access status versus readout protection level and execution modes
User execution Debug, boot from RAM or boot

Protection from system memory (loader)
Area
level
Read Write Erase Read Write Erase
Main 1 Yes Yes Yes No No No

memory 2 Yes Yes Yes N/A N/A N/A
System 1 Yes No No Yes No No
memory 2 Yes No No N/A N/A N/A
Option 1 Yes Yes Yes Yes Yes Yes
bytes 2 Yes No No N/A N/A N/A
• Write protection (WRP): the protected area is protected against erasing and
programming. Two areas per bank can be selected, with 2-Kbyte granularity.
3.4 Embedded SRAM

STM32C011x4/x6 devices have 6 Kbytes of embedded SRAM with parity. Hardware parity
check allows memory data errors to be detected, which contributes to increasing functional
safety of applications.
The memory can be read/write-accessed at CPU clock speed, with 0 wait states.
3.5 Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot
options:
• boot from main flash memory
• boot from system memory
• boot from embedded SRAM
The boot pin is shared with a standard GPIO and can be enabled through the boot selector
option bit. The boot loader is located in system memory. It manages the flash memory
reprogramming through one of the following interfaces:
• USART on pins PA9/PA10
• I2C-bus on pins PB6/PB7
12/92 DS13866 Rev 4

If the BOOT0 pin selects the boot from the main flash memory of which the first location is
empty, the flash memory empty checker forces the boot from the system memory. The
system memory contains an embedded bootloader that then configures some of the GPIOs
out of their by-default high-Z state. Refer to AN2606 for more details on the bootloader and
on the GPIO configuration when booting from the system memory.
3.6 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at link
time and stored at a given memory location.
3.7 Power supply management
3.7.1 Power supply schemes

The STM32C011x4/x6 devices require 2.0 V to 3.6 V operating supply voltage (VDD).
Several different power supplies are provided to specific peripherals:
• VDD = 2.0 V (1.96 V) to 3.6 V
VDD is the external power supply for the internal regulator and the system analog such
as reset, power management and internal clocks. It is provided externally through
VDD/VDDA pin.
The minimum voltage of 2.0 V corresponds to power-on reset release threshold
VPOR(max). Once this threshold is crossed and power-on reset is released, the
functionality is guaranteed down to power-down reset threshold VPDR(min) of 1.96 V.
• VDDA = 2.0 V (1.96 V) (ADC) to 3.6 V
VDDA is the analog power supply for the A/D converter. VDDA voltage level is identical to
VDD voltage as it is provided externally through VDD/VDDA pin.
• VDDIO1 = VDD
VDDIO1 is the power supply for the I/Os. VDDIO1 voltage level is identical to VDD voltage
as it is provided externally through VDD/VDDA pin.
• VREF+ is the analog peripheral input reference voltage.
VREF+ is internally connected with VDD.
• VCORE is an internal supply for digital peripherals, SRAM and flash memory. It is
produced by an embedded linear voltage regulator. On top of VCORE, the flash memory
is also powered from VDD.
DS13866 Rev 4 13/92

25
Figure 2. Power supply overview
VDDA domain
VREF+
VDDA A/D converter
VSSA
VDDIO1
I/O ring VDDIO1 domain
Reset block VDD domain

Temp. sensor
HSI48
Standby circuitry
VSS (Wakeup logic, VCORE domain
VSS/VSSA IWDG)
VDD LSE 32 kHz Core
VDD/VDDA VCORE
Voltage regulator SRAM
Digital
peripherals
Flash memory
RTC domain
RTC
MSv65923V2
3.7.2 Power supply supervisor

The device has an integrated power-on/power-down (POR/PDR) reset active in all power
modes except Shutdown and ensuring proper operation upon power-on and power-down. It
maintains the device in reset when the supply voltage is below VPOR/PDR threshold, without
the need for an external reset circuit. Brownout reset (BOR) function allows extra flexibility. It
can be enabled and configured through option bytes, by selecting one of four thresholds for
rising VDD and other four for falling VDD.
3.7.3 Voltage regulator

An embedded linear voltage regulator supplies most of the digital circuitry in the device.
In Standby and Shutdown modes, the regulator is powered down and its output set in high-
impedance state, such as to bring its current consumption close to zero.
3.7.4 Low-power modes

By default, the device is in Run mode after system or power reset. It is up to the user to
select one of the low-power modes described below:
• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
• Stop mode
In Stop mode, the device achieves the lowest power consumption while retaining the
SRAM and register contents. All clocks in the VCORE are stopped. The HSE and HSI48
14/92 DS13866 Rev 4

oscillators stop. The HSI48 can be restarted by a peripheral with wake-up capability
requiring HSI48.
The LSE and LSI can be kept running. The RTC can remain active (Stop mode with
RTC, Stop mode without RTC).
The event of exiting Stop mode enables the HSI48 oscillator and select HSISYS as
system clock.
• Standby mode
The Standby mode is used to achieve the lowest power consumption, with POR/PDR
always active in this mode. The regulator is switched off to power down VCORE domain.
The HSI48 RC oscillator and the HSE crystal oscillator are also powered down. The
RTC is switched off.
For each I/O, the software can determine whether a pull-up, a pull-down or no resistor
shall be applied to that I/O during Standby mode.
Upon entering Standby mode, register contents are lost, except for 16-bit backup
registers whose contents are kept.
The device exits Standby mode upon external reset event (NRST pin), IWDG reset
event, wake-up event (WKUP pin, configurable rising or falling edge), or when a failure
is detected on LSE (CSS on LSE).
• Shutdown mode
The Shutdown mode allows to achieve the lowest power consumption. The internal
regulator is switched off to power down the VCORE domain. The HSI48 and LSI RC-
oscillators and HSE crystal oscillator are also powered down. The RTC is off.
The BOR is not available in Shutdown mode. No power voltage monitoring is possible
in this mode.
SRAM and register contents are lost.
The device exits Shutdown mode upon external reset event (NRST pin), or wake-up
event (WKUP pin, configurable rising or falling edge).
3.7.5 Reset mode

During and upon exiting reset, the Schmitt triggers of I/Os are disabled so as to reduce
power consumption. In addition, when the reset source is internal, the built-in pull-up
resistor on NRST pin is deactivated.
3.8 Interconnect of peripherals

Several peripherals have direct connections between them. This allows autonomous
communication between peripherals, saving CPU resources thus power supply
consumption. In addition, these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep and Stop
modes.
DS13866 Rev 4 15/92

25
Table 4. Interconnect of peripherals
Interconnect
Interconnect source Interconnect action Run Sleep Stop
destination
TIMx Timer synchronization or chaining Y Y -

ADCx Conversion triggers Y Y -
TIMx
DMA Memory-to-memory transfer trigger Y Y -
ADCx TIM1 Timer triggered by analog watchdog Y Y -
RTC TIM16 Timer input channel from RTC events Y Y -
All clock sources (internal and Clock source used as input channel for
TIM14,16,17 Y Y -
external) RC measurement and trimming
CSS
RAM (parity error) TIM1,16,17 Timer break Y Y -
CPU (hard fault) TIM1,16,17 Timer break Y - -

TIM1,3 External trigger Y Y -
GPIO
ADC Conversion external trigger Y Y -
3.9 Clocks and startup

The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
• Clock prescaler: to get the best trade-off between speed and current consumption,
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
• Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
• Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
• System clock source: the following clock sources can deliver SYSCLK system clock:
– 4-48 MHz high-speed oscillator with external crystal or ceramic resonator (HSE).
The HSE can also be configured in bypass mode for an external clock.
– 48 MHz high-speed internal RC oscillator (HSI48), trimmable by software.
– 32.768 kHz low-speed oscillator with external crystal (LSE), supporting two drive
capability modes. The LSE can also be configured in bypass mode for using an
external clock.
– 32 kHz low-speed internal RC oscillator (LSI) with ±5% accuracy, also used to
clock an independent watchdog.
16/92 DS13866 Rev 4

• Peripheral clock sources: several peripherals (I2S, USART1, I2C1, ADC) can
operate with a clock source independent of the system clock.
• Clock security system (CSS): in the event of HSE or LSE clock failure, the system
clock is automatically switched to HSI48 or LSI, respectively. If enabled, a software
interrupt is generated. The CCS feature can be enabled by software.
• Clock output:
– MCO and MCO2 (microcontroller clock output) provides one of the internal
clocks for external use by the application.
– LSCO (low speed clock output) provides LSI or LSE in all low-power modes.
Several prescalers allow the application to configure AHB and APB domain clock
frequencies, 48 MHz at maximum.
3.10 General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function (AF). Most of
the GPIO pins are shared with special digital or analog functions.
Through a specific sequence, this special function configuration of I/Os can be locked, such
as to avoid spurious writing to I/O control registers.
3.11 Direct memory access controller (DMA)

The direct memory access (DMA) controller is a bus master and system peripheral with
single-AHB architecture.
With 3 channels, it performs data transfers between memory-mapped peripherals and/or
memories, to offload the CPU.
Each channel is dedicated to managing memory access requests from one or more
peripherals. The unit includes an arbiter for handling the priority between DMA requests.
Main features of the DMA controller:
• Single-AHB master
• Peripheral-to-memory, memory-to-peripheral, memory-to-memory and peripheral-to-
peripheral data transfers
• Access, as source and destination, to on-chip memory-mapped devices such as flash
memory, SRAM, and AHB and APB peripherals
• All DMA channels independently configurable:
– Each channel is associated either with a DMA request signal coming from a
peripheral, or with a software trigger in memory-to-memory transfers. This
configuration is done by software.
– Priority between the requests is programmable by software (four levels per
channel: very high, high, medium, low) and by hardware in case of equality (such
as request to channel 1 has priority over request to channel 2).
– Transfer size of source and destination are independent (byte, half-word, word),
emulating packing and unpacking. Source and destination addresses must be
aligned on the data size.
DS13866 Rev 4 17/92

25
– Support of transfers from/to peripherals to/from memory with circular buffer

management
– Programmable number of data to be transferred: 0 to 216 - 1
• Generation of an interrupt request per channel. Each interrupt request originates from
any of the three DMA events: transfer complete, half transfer, or transfer error.
3.12 DMA request multiplexer (DMAMUX)

The DMAMUX request multiplexer enables routing a DMA request line between the
peripherals and the DMA controller. Each channel selects a unique DMA request line,
unconditionally or synchronously with events from its DMAMUX synchronization inputs.
DMAMUX may also be used as a DMA request generator from programmable events on its
input trigger signals.
3.13 Interrupts and events

The device flexibly manages events causing interrupts of linear program execution, called
exceptions. The Cortex-M0+ processor core, a nested vectored interrupt controller (NVIC)
and an extended interrupt/event controller (EXTI) are the assets contributing to handling the
exceptions. Exceptions include core-internal events such as, for example, a division by zero
and, core-external events such as logical level changes on physical lines. Exceptions result
in interrupting the program flow, executing an interrupt service routine (ISR) then resuming
the original program flow.
The processor context (contents of program pointer and status registers) is stacked upon
program interrupt and unstacked upon program resume, by hardware. This avoids context
stacking and unstacking in the interrupt service routines (ISRs) by software, thus saving
time, code and power. The ability to abandon and restart load-multiple and store-multiple
operations significantly increases the device’s responsiveness in processing exceptions.
3.13.1 Nested vectored interrupt controller (NVIC)

The configurable nested vectored interrupt controller is tightly coupled with the core. It
handles physical line events associated with a non-maskable interrupt (NMI) and maskable
interrupts, and Cortex-M0+ exceptions. It provides flexible priority management.
The tight coupling of the processor core with NVIC significantly reduces the latency between
interrupt events and start of corresponding interrupt service routines (ISRs). The ISR
vectors are listed in a vector table, stored in the NVIC at a base address. The vector
address of an ISR to execute is hardware-built from the vector table base address and the
ISR order number used as offset.
If a higher-priority interrupt event happens while a lower-priority interrupt event occurring
just before is waiting for being served, the later-arriving higher-priority interrupt event is
served first. Another optimization is called tail-chaining. Upon a return from a higher-priority
ISR then start of a pending lower-priority ISR, the unnecessary processor context
unstacking and stacking is skipped. This reduces latency and contributes to power
efficiency.
18/92 DS13866 Rev 4

Features of the NVIC:

• Low-latency interrupt processing
• 4 priority levels
• Handling of a non-maskable interrupt (NMI)
• Handling of 32 maskable interrupt lines
• Handling of 10 Cortex-M0+ exceptions
• Later-arriving higher-priority interrupt processed first
• Tail-chaining
• Interrupt vector retrieval by hardware
3.13.2 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller adds flexibility in handling physical line events and
allows identifying wake-up events at processor wake-up from Stop mode.
The EXTI controller has a number of channels, of which some with rising, falling or rising,
and falling edge detector capability. Any GPIO and a few peripheral signals can be
connected to these channels.
The channels can be independently masked.
The EXTI controller can capture pulses shorter than the internal clock period.
A register in the EXTI controller latches every event even in Stop mode, which allows the
software to identify the origin of the processor's wake-up from Stop mode or, to identify the
GPIO and the edge event having caused an interrupt.
3.14 Analog-to-digital converter (ADC)

A native 12-bit analog-to-digital converter is embedded into STM32C011x4/x6 devices. The
ADC has up to 13 external channels and 2 internal channels (temperature sensor, voltage
reference). It performs conversions in single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
The ADC frequency is independent from the CPU frequency, allowing maximum sampling
rate of 2.5 MSps even with a low CPU speed. An auto-shutdown function guarantees that
the ADC is powered off except during the active conversion phase.
The ADC can be served by the DMA controller. It can operate in the whole VDD supply
range.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions with timers.
3.14.1 Temperature sensor

The temperature sensor (TS) generates a voltage VTS that varies linearly with temperature.
The temperature sensor is internally connected to an ADC input to convert the sensor
output voltage into a digital value.
DS13866 Rev 4 19/92

25
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor may
vary from part to part due to process variation, the uncalibrated internal temperature sensor
is suitable only for relative temperature measurements.
To improve the accuracy of the temperature sensor, each part is individually factory-
calibrated by ST. The resulting calibration data are stored in the part’s engineering bytes,
accessible in read-only mode.
Table 5. Temperature sensor calibration values

Calibration value name Description Memory address
TS ADC raw data acquired at a

TS_CAL1 temperature of 30 °C (± 5 °C), 0x1FFF7568-0x1FFF7569
VDDA = VREF+ = 3.0 V (± 10 mV)
3.14.2 Internal voltage reference (VREFINT)

The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC. VREFINT is internally connected to an ADC input. The VREFINT voltage is individually
precisely measured for each part by ST during production test and stored in the part’s
engineering bytes. It is accessible in read-only mode.
Table 6. Internal voltage reference calibration values

Calibration value name Description Memory address
Raw data acquired at a

VREFINT temperature of 30 °C (± 5 °C), 0x1FFF756A-0x1FFF756B
VDDA = VREF+ = 3.0 V (± 10 mV)
3.15 Timers and watchdogs

The device includes an advanced-control timer, four general-purpose timers, two low-power
timers, two watchdog timers and a SysTick timer. Table 7 compares features of the
advanced-control, general-purpose and basic timers.
Table 7. Timer feature comparison

Maximum DMA Capture/ Comple-
Counter Counter Prescaler
Timer Timer type operating request compare mentary
resolution type factor
frequency generation channels outputs
Advanced- Up, down, Integer from 4

TIM1 16-bit 48 MHz Yes 3
control up/down 1 to 216 +2 internal
General- Up, down, Integer from
TIM3 16-bit 48 MHz Yes 4 -
purpose up/down 1 to 216
General- Integer from
TIM14 16-bit Up 48 MHz No 1 -
purpose 1 to 216
TIM16 General- Integer from
16-bit Up 48 MHz Yes 1 1
TIM17 purpose 1 to 216
20/92 DS13866 Rev 4

3.15.1 Advanced-control timer (TIM1)

The advanced-control timer can be seen as a three-phase PWM unit multiplexed on 6
channels. It has complementary PWM outputs with programmable inserted dead-times. It
can also be seen as a complete general-purpose timer. The four independent channels can
be used for:
• input capture
• output compare
• PWM output (edge or center-aligned modes) with full modulation capability (0-100%)
• one-pulse mode output
On top of these, there are two internal channels that can be used.
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs
disabled, so as to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIMx timers (described in
Section 3.15.2) using the same architecture, so the advanced-control timers can work
together with the TIMx timers via the Timer Link feature for synchronization or event
chaining.
3.15.2 General-purpose timers (TIM3, 14, 16, 17)

There are four synchronizable general-purpose timers embedded in the device (refer to
Table 7 for comparison). Each general-purpose timer can be used to generate PWM outputs
or act as a simple timebase.
• TIM3
This is a full-featured general-purpose timer with 16-bit auto-reload up/downcounter
and 16-bit prescaler.
It has four independent channels for input capture/output compare, PWM or one-pulse
mode output. It can operate in combination with other general-purpose timers via the
Timer Link feature for synchronization or event chaining. It can generate independent
DMA request and support quadrature encoders. Its counter can be frozen in debug
mode.
• TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. It has one
channel for input capture/output compare, PWM output or one-pulse mode output. Its
counter can be frozen in debug mode.
• TIM16, TIM17
These are general-purpose timers featuring:
– 16-bit auto-reload upcounter and 16-bit prescaler
– 1 channel and 1 complementary channel
All channels can be used for input capture/output compare, PWM or one-pulse mode
output. The timers can operate together via the Timer Link feature for synchronization
or event chaining. They can generate independent DMA request. Their counters can
be frozen in debug mode.
3.15.3 Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 32 kHz internal RC (LSI).
DS13866 Rev 4 21/92

25
Independent of the main clock, it can operate in Stop and Standby modes. It can be used
either as a watchdog to reset the device when a problem occurs, or as a free-running timer
for application timeout management. It is hardware- or software-configurable through the
option bytes. Its counter can be frozen in debug mode.
3.15.4 System window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked by the
system clock. It has an early-warning interrupt capability. Its counter can be frozen in debug
mode.
3.15.5 SysTick timer

This timer is dedicated to real-time operating systems, but it can also be used as a standard
down counter.
Features of SysTick timer:
• 24-bit down counter
• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source
3.16 Real-time clock (RTC)

The devices embed an RTC located in the RTC domain and supplied from VCORE.
The RTC is an independent BCD timer/counter.
Features of the RTC:
• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
• Automatic correction for 28, 29 (leap year), 30, and 31 days of the month
• Programmable alarm
• On-the-fly correction from 1 to 32767 RTC clock pulses, usable for synchronization with
a master clock
• Reference clock detection - a more precise second-source clock (50 or 60 Hz) can be
used to improve the calendar precision
• Digital calibration circuit with 0.95 ppm resolution, to compensate for quartz crystal
inaccuracy
• Timestamp feature to save a calendar snapshot, triggered by an event on the
timestamp pin
• Multiple clock sources and references:
– a 32.768 kHz external crystal (LSE)
– an external resonator or oscillator (LSE)
– the internal low-power RC oscillator (LSI, with typical frequency of 32 kHz)
– the high-speed external clock (HSE) divided by 32
The RTC operates in Run, Sleep, and Stop mode.
22/92 DS13866 Rev 4

RTC events (Alarm, Timestamp) can generate an interrupt and wake the device up from the
low-power modes.
3.17 Inter-integrated circuit interface (I2C)

The devices embed one I2C peripheral. Refer to Table 8 for the features.
The I2C peripheral handles communication between the microcontroller and the serial
I2C-bus. It controls all I2C-bus-specific sequencing, protocol, arbitration and timing.
Features of the I2C peripheral:
• I2C-bus specification and user manual rev. 5 compatibility:
– Slave and master modes, multimaster capability
– Standard-mode (Sm), with a bitrate up to 100 kbit/s
– Fast-mode (Fm), with a bitrate up to 400 kbit/s
– Fast-mode Plus (Fm+), with a bitrate up to 1 Mbit/s and extra output drive I/Os
– 7-bit and 10-bit addressing mode, multiple 7-bit slave addresses
– Programmable setup and hold times
– Clock stretching
• SMBus specification rev 3.0 compatibility:
– Hardware PEC (packet error checking) generation and verification with ACK
control
– Command and data acknowledge control
– Address resolution protocol (ARP) support
– Host and device support
– SMBus alert
– Timeouts and idle condition detection
• PMBus rev 1.3 standard compatibility
• Independent clock: a choice of independent clock sources allowing the I2C-bus
communication speed to be independent of the PCLK reprogramming
• Wake-up from Stop mode on address match
• Programmable analog and digital noise filters
• 1-byte buffer with DMA capability
Table 8. I2C implementation

I2C features(1) I2C1
Standard-mode (up to 100 kbit/s) X

Fast-mode (up to 400 kbit/s) X
Fast-mode Plus (up to 1 Mbit/s) with extra output drive I/Os X
Programmable analog and digital noise filters X
SMBus/PMBus hardware support X
Independent clock X
Wake-up from Stop mode on address match X
1. X: supported
DS13866 Rev 4 23/92

25
3.18 Universal synchronous/asynchronous receiver transmitter

(USART)
The devices embed two universal synchronous/asynchronous receivers/transmitters that
communicate at speeds of up to 6 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 DE signals,
multiprocessor communication mode, synchronous SPI communication and single-wire half-
duplex communication mode. Some can also support SmartCard communication (ISO
7816), IrDA SIR ENDEC, LIN Master/Slave capability and auto baud rate feature, and have
a clock domain independent of the CPU clock, which allows them to wake up the MCU from
Stop mode. The wake-up events from Stop mode are programmable and can be:
• start bit detection
• any received data frame
• a specific programmed data frame
All USART interfaces can be served by the DMA controller.
Table 9. USART implementation

USART modes/features(1) USART1 USART2
Hardware flow control for modem X X

Continuous communication using DMA X X
Multiprocessor communication X X
SPI emulation master/slave (synchronous mode) X X
Smartcard mode X -
Single-wire half-duplex communication X X
IrDA SIR ENDEC block X -
LIN mode X -
Dual clock domain and wake-up from Stop mode X -
Receiver timeout interrupt X -
Modbus communication X -
Auto baud rate detection X -
Driver Enable X X
1. X: supported
3.19 Serial peripheral interface (SPI)

The devices contain one SPI running at up to 24 Mbits/s in master and slave modes. It
supports half-duplex, full-duplex and simplex communications. A 3-bit prescaler gives eight
master mode frequencies. The frame size is configurable from 4 bits to 16 bits. The SPI
peripherals support NSS pulse mode, TI mode and hardware CRC calculation.
The SPI peripherals can be served by the DMA controller.
The I2S interface mode of the SPI peripheral (if supported, see the following table) supports
four different audio standards can operate as master or slave, in half-duplex communication
24/92 DS13866 Rev 4

mode. It can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data
resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to
192 kHz can be set by an 8-bit programmable linear prescaler. When operating in master
mode, it can output a clock for an external audio component at 256 times the sampling
frequency.
Table 10. SPI/I2S implementation

SPI features(1) SPI1
Hardware CRC calculation X

Rx/Tx FIFO X
NSS pulse mode X
2S
I mode X
TI mode X
1. X = supported.
3.20 Development support
3.20.1 Serial wire debug port (SW-DP)

An Arm SW-DP interface is provided to allow a serial wire debugging tool to be connected to
the MCU.
DS13866 Rev 4 25/92

25
Pinouts, pin description and alternate functions STM32C011x4/x6
4 Pinouts, pin description and alternate functions
Figure 3. STM32C011JxM SO8N pinout
Top view
PB7/PC14-OSCX_IN 1 8 PB6/PA14-BOOT0/PC15-OSCX_OUT
VDD/VDDA 2 7 PA13
VSS/VSSA 3 6 PA12[PA10]
PA0/PA1/PA2/PF2-NRST 4 5 PA11[PA9]/PA8
MSv65924V2
Figure 4. STM32C011DxY WLCSP12 ballout
1 2 3 4
Top view
PC15-
A PB6 OSCX
_OUT
PC14-
B PA13
OSCX_IN
PA14- VDD/
C BOOT0 VDDA
PA11
D [PA9]/ PB7
PA8
PA12
VSS/
E [PA10]/
VSSA
PA7
PF2-
PA3/PA4/ NRST/
F PA5/PA6 PA0/PA1/
PA2
MSv65925V1
26/92 DS13866 Rev 4

STM32C011x4/x6 Pinouts, pin description and alternate functions
Figure 5. STM32C011FxP TSSOP20 pinout
Top view
PB7 1 20 PB6
PC14-OSCX_IN 2 19 PA14-BOOT0
PC15-OSCX_OUT 3 18 PA13
VDD/VDDA 4 17 PA12[PA10]
VSS/VSSA 5 16 PA11[PA9]
PF2-NRST 6 15 PA8
PA0 7 14 PA7
PA1 8 13 PA6
PA2 9 12 PA5
PA3 10 11 PA4
MSv65926V1
Figure 6. STM32C011FxU UFQFPN20 pinout

PC14-OSCX_IN
Top view PA14-BOOT0

PA13
PB7
PB6
20
19
18
17
16
PC15-OSCX_OUT 1 15 PA12 [PA10]

VDD/VDDA 2 14 PA11 [PA9]
VSS/VSSA 3 UFQFPN20 13 PA8
PF2-NRST 4 12 PA7
PA0 5 11 PA6
10
6
7
8
9
PA1
PA2
PA3
PA4
PA5
DS13866 Rev 4 27/92

29
Pinouts, pin description and alternate functions STM32C011x4/x6
Table 11. Terms and symbols used in the pin assignment table
Column Symbol Definition
Terminal name corresponds to its by-default function at reset, unless otherwise specified in
Pin name
parenthesis under the pin name.
S Supply pin
Pin type I Input only pin
I/O Input / output pin
FT 5 V tolerant I/O
RST Reset pin with embedded weak pull-up resistor
Options for FT I/Os
I/O structure
_f I/O, Fm+ capable
_a I/O, with analog switch function
Note Upon reset, all I/Os are set as analog inputs, unless otherwise specified.
Alternate
Functions selected through GPIOx_AFR registers
Pin functions
functions Additional
Functions directly selected/enabled through peripheral registers
functions
Table 12. Pin assignment and description
Pin
I/O structure
Pin name
Pin type
Alternate Additional
Note
UFQFPN20
WLCSP12
TSSOP20
(function upon functions functions

SO8N
reset)
USART1_TX, TIM1_ETR, TIM1_BKIN2, IR_OUT,

PC14-OSCX_IN
1 B3 2 20 I/O FT_f - USART2_RTS_DE_CK, TIM17_CH1, TIM3_CH2, OSCX_IN
(PC14)
I2C1_SDA, EVENTOUT
PC15-
8 A4 3 1 OSCX_OUT I/O FT - OSC32_EN, OSC_EN, TIM1_ETR, TIM3_CH3 OSCX_OUT
(PC15)
2 C4 4 2 VDD/VDDA S - - - -
3 E4 5 3 VSS/VSSA S - - - -
RST, (1)
4 F3 6 4 PF2-NRST I/O MCO, TIM1_CH4 NRST
FT
4 F3 7 5 PA0 I/O FT_a - USART2_CTS, TIM16_CH1, USART1_TX, TIM1_CH1 ADC_IN0, WKUP1
SPI1_SCK/I2S1_CK, USART2_RTS_DE_CK,
4 F3 8 6 PA1 I/O FT_a - TIM17_CH1, USART1_RX, TIM1_CH2, I2C1_SMBA, ADC_IN1
EVENTOUT
28/92 DS13866 Rev 4

STM32C011x4/x6 Pinouts, pin description and alternate functions
Table 12. Pin assignment and description (continued)
Pin
I/O structure
Pin name
Pin type
Alternate Additional
Note
UFQFPN20
WLCSP12
TSSOP20
(function upon functions functions

SO8N
reset)
SPI1_MOSI/I2S1_SD, USART2_TX, TIM16_CH1N, ADC_IN2,

4 F3 9 7 PA2 I/O FT_a -
TIM3_ETR, TIM1_CH3 WKUP4,LSCO
- F1 10 8 PA3 I/O FT_a - USART2_RX, TIM1_CH1N, TIM1_CH4, EVENTOUT ADC_IN3
ADC_IN4, RTC_TS,
SPI1_NSS/I2S1_WS, USART2_TX, TIM1_CH2N,
- F1 11 9 PA4 I/O FT_a - RTC_OUT1,
TIM14_CH1, TIM17_CH1N, EVENTOUT
WKUP2
SPI1_SCK/I2S1_CK, USART2_RX, TIM1_CH3N,
- F1 12 10 PA5 I/O FT_a - ADC_IN5
TIM1_CH1, EVENTOUT
SPI1_MISO/I2S1_MCK, TIM3_CH1, TIM1_BKIN,
- F1 13 11 PA6 I/O FT_a - ADC_IN6
TIM16_CH1
SPI1_MOSI/I2S1_SD, TIM3_CH2, TIM1_CH1N,
- E2 14 12 PA7 I/O FT_a - ADC_IN7
TIM14_CH1, TIM17_CH1
MCO, USART2_TX, TIM1_CH1, EVENTOUT,
SPI1_NSS/I2S1_WS, TIM1_CH2N, TIM1_CH3N,
5 D1 15 13 PA8 I/O FT_a - ADC_IN8
TIM3_CH3, TIM3_CH4, TIM14_CH1, USART1_RX,
MCO2
(2) MCO, USART1_TX, TIM1_CH2, TIM3_ETR,
- - - - PA9 I/O FT_f -
I2C1_SCL, EVENTOUT
(2) USART1_RX, TIM1_CH3, MCO2, TIM17_BKIN,
- - - - PA10 I/O FT_f -
I2C1_SDA, EVENTOUT
(2) SPI1_MISO/I2S1_MCK, USART1_CTS, TIM1_CH4,
5 D1 16 14 PA11 [PA9] I/O FT_a ADC_IN11
TIM1_BKIN2
(2) SPI1_MOSI/I2S1_SD, USART1_RTS_DE_CK,
6 E2 17 15 PA12 [PA10] I/O FT_a ADC_IN12
TIM1_ETR, I2S_CKIN
(3) SWDIO, IR_OUT, TIM3_ETR, USART2_RX,
7 B1 18 16 PA13 I/O FT_a ADC_IN13
EVENTOUT
SWCLK, USART2_TX, EVENTOUT,
(3)
8 C2 19 17 PA14-BOOT0 I/O FT_a SPI1_NSS/I2S1_WS, USART2_RX, TIM1_CH1, ADC_IN14, BOOT0
MCO2, USART1_RTS_DE_CK
USART1_TX, TIM1_CH3, TIM16_CH1N, TIM3_CH3,
USART1_RTS_DE_CK, USART1_CTS, I2C1_SCL,
I2C1_SMBA, SPI1_MOSI/I2S1_SD,
8 A2 20 18 PB6 I/O FT_f - WKUP3
SPI1_MISO/I2S1_MCK, SPI1_SCK/I2S1_CK,
TIM1_CH2, TIM3_CH1, TIM3_CH2, TIM16_BKIN,
TIM17_BKIN
USART1_RX, TIM1_CH4, TIM17_CH1N, TIM3_CH4,
1 D3 1 19 PB7 I/O FT_f - I2C1_SDA, EVENTOUT, USART2_CTS, TIM16_CH1, RTC_REFIN
TIM3_CH1, I2C1_SCL
1. RST I/O structure when the PF2-NRST pin is configured as reset (input or input/output mode), FT I/O structure when the
PF2-NRST pin is configured as GPIO
2. Pins PA9 and PA10 can be remapped in place of pins PA11 and PA12 (default mapping), using SYSCFG_CFGR1 register.
3. Upon reset, this pin is configured as SWD alternate function, and the internal pull-up on PA13 pin and the internal pull-down
on PA14 pin are activated.
DS13866 Rev 4 29/92

29
Table 13. Port A alternate function mapping (AF0 to AF7)
30/92 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PA0 - USART2_CTS TIM16_CH1 - USART1_TX TIM1_CH1 - -

SPI1_SCK/I2S1_ USART2_RTS_
PA1 TIM17_CH1 - USART1_RX TIM1_CH2 I2C1_SMBA EVENTOUT
CK DE_CK
SPI1_MOSI/I2S1
PA2 USART2_TX TIM16_CH1N TIM3_ETR - TIM1_CH3 - -
_SD
PA3 - USART2_RX TIM1_CH1N - - TIM1_CH4 - EVENTOUT
SPI1_NSS/I2S1_
PA4 USART2_TX TIM1_CH2N - TIM14_CH1 TIM17_CH1N - EVENTOUT
WS
SPI1_SCK/I2S1_
PA5 USART2_RX TIM1_CH3N - - TIM1_CH1 - EVENTOUT
CK
SPI1_MISO/I2S1
PA6 TIM3_CH1 TIM1_BKIN - - TIM16_CH1 - -
_MCK
DS13866 Rev 4
SPI1_MOSI/I2S1
PA7 TIM3_CH2 TIM1_CH1N - TIM14_CH1 TIM17_CH1 - -
_SD
PA8 MCO USART2_TX TIM1_CH1 - - - - EVENTOUT
PA9 MCO USART1_TX TIM1_CH2 TIM3_ETR - - I2C1_SCL EVENTOUT
PA10 - USART1_RX TIM1_CH3 MCO2 - TIM17_BKIN I2C1_SDA EVENTOUT
SPI1_MISO/I2S1
PA11 USART1_CTS TIM1_CH4 - - TIM1_BKIN2 - -
_MCK
SPI1_MOSI/I2S1 USART1_RTS_
PA12 TIM1_ETR - - I2S_CKIN - -
_SD DE_CK
PA13 SWDIO IR_OUT - TIM3_ETR USART2_RX - - EVENTOUT
PA14 SWCLK USART2_TX - - - - - EVENTOUT
STM32C011x4/x6
Table 14. Port A alternate function mapping (AF8 to AF15)
STM32C011x4/x6
Port AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15
SPI1_NSS/I2S1_
PA8 TIM1_CH2N TIM1_CH3N TIM3_CH3 TIM3_CH4 TIM14_CH1 USART1_RX MCO2
WS
SPI1_NSS/I2S1_ USART1_RTS_
PA14 USART2_RX TIM1_CH1 MCO2 - - -
WS DE_CK
Table 15. Port B alternate function mapping (AF0 to AF7)

USART1_RTS_
PB6 USART1_TX TIM1_CH3 TIM16_CH1N TIM3_CH3 USART1_CTS I2C1_SCL I2C1_SMBA
DE_CK
PB7 USART1_RX TIM1_CH4 TIM17_CH1N TIM3_CH4 - - I2C1_SDA EVENTOUT
DS13866 Rev 4
Table 16. Port B alternate function mapping (AF8 to AF15)

SPI1_MOSI/I2S1 SPI1_MISO/I2S1 SPI1_SCK/I2S1_

PB6 TIM1_CH2 TIM3_CH1 TIM3_CH2 TIM16_BKIN TIM17_BKIN
_SD _MCK CK
PB7 - USART2_CTS TIM16_CH1 TIM3_CH1 - - I2C1_SCL -
Table 17. Port C alternate function mapping (AF0 to AF7)

PC14 USART1_TX TIM1_ETR TIM1_BKIN2 - - - - -

PC15 OSC32_EN OSC_EN TIM1_ETR TIM3_CH3 - - - -
Table 18. Port C alternate function mapping (AF8 to AF15)

USART2_RTS_
31/92
PC14 IR_OUT TIM17_CH1 TIM3_CH2 - - I2C1_SDA EVENTOUT

DE_CK
Table 19. Port F alternate function mapping
32/92 Port AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
PF2 MCO TIM1_CH4 - - - - - -

DS13866 Rev 4
STM32C011x4/x6
STM32C011x4/x6 Electrical characteristics
5 Electrical characteristics
5.1 Parameter conditions

Unless otherwise specified, all voltages are referenced to VSS.
Parameter values defined at temperatures or in temperature ranges out of the ordering
information scope are to be ignored.
Packages used for characterizing certain electrical parameters may differ from the
commercial packages as per the ordering information.
5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TA(max) (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25 °C, VDD = VDDA = 3 V. They
are given only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor

The loading conditions used for pin parameter measurement are shown in Figure 7.
5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is described in Figure 8.
Figure 7. Pin loading conditions Figure 8. Pin input voltage
MCU pin MCU pin
C = 50 pF VIN
DS13866 Rev 4 33/92

77
Electrical characteristics STM32C011x4/x6
5.1.6 Power supply scheme
Figure 9. Power supply scheme
RTC
VDD VCORE
VDD/VDDA VDD
Regulator
VDDIO
OUT
Level shifter
Kernel logic
1 x 100 nF IO (CPU, digital and
GPIOs
+ 1 x 4.7 μF IN
logic memories)
VSS
VDDA
VREF+
ADC
VREF-
VSS/VSSA VSSA
MSv57328V1
Caution: Power supply pin pair (VDD/VDDA and VSS/VSSA) must be decoupled with filtering
ceramic capacitors as shown above. These capacitors must be placed as close as possible
to, or below, the appropriate pins on the underside of the PCB to ensure the good
functionality of the device.
5.1.7 Current consumption measurement
Figure 10. Current consumption measurement scheme
IDD
VDD/VDDA
VDD
(VDDA)
MS55840V1
34/92 DS13866 Rev 4

5.2 Absolute maximum ratings

Stresses above the absolute maximum ratings listed in Table 20, Table 21 and Table 22
may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability. The device mission profile
(application conditions) is compliant with the JEDEC JESD47 qualification standard.
All voltages are defined with respect to VSS.
Table 20. Voltage characteristics

Symbol Ratings Min Max Unit
VDD - VSS External supply voltage -0.3 4.0

VIN (1) Input voltage on pin -0.3 VDD + 4.0(2)(3) V
1. VIN maximum must always be respected. Refer to Table 21 for the maximum allowed injected current values.
2. To sustain a voltage higher than 4 V the internal pull-up/pull-down resistors must be disabled.
3. When an FT_a pin is used for interfacing with an analog peripheral (such as ADC), the maximum VIN is 4 V.
Table 21. Current characteristics

Symbol Ratings Max Unit
IVDD/VDDA Current into VDD/VDDA power pin (source) 100

IVSS/VSSA Current out of VSS/VSSA ground pin (sink) 100
Output current sunk by any I/O and control pin 20
IIO(PIN)
Output current sourced by any I/O and control pin 20
mA
(1)
Total output current sunk by sum of all I/Os and control pins 80
∑I(PIN)
Total output current sourced by sum of all I/Os and control pins(1) 80
(1)(2)
IINJ(PIN) Injected current on a FT_xx pin -5 / 0
∑IINJ(PIN) Total injected current (sum of all I/Os and control pins)(3) -25
1. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum
value.
2. A positive injection is induced by VIN > VDDIOx while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer also to Table 20: Voltage characteristics for the maximum allowed input voltage values.
3. When several inputs are submitted to a current injection, the maximum ∑|IINJ(PIN)| is the absolute sum of the negative
injected currents (instantaneous values).
Table 22. Thermal characteristics

Symbol Ratings Value Unit
TSTG Storage temperature range –65 to +150 °C

TJ Maximum junction temperature 130 °C
DS13866 Rev 4 35/92

77
5.3 Operating conditions
5.3.1 General operating conditions
Table 23. General operating conditions

Symbol Parameter Conditions Min Max Unit
VDD (1)
Standard operating voltage - 2.0 3.6 V
VIN I/O input voltage - -0.3 Min (VDD + 3.6, 5.5)(2) V
fPCLK APB clock frequency - - 48 MHz
(4)
Suffix 6 -40 85
TA Ambient temperature(3) Suffix 7 (4)
-40 105 °C
Suffix 3(4) -40 125
Suffix 6(4) -40 105
TJ (4)
Junction temperature Suffix 7 -40 125 °C
Suffix 3(4) -40 130
1. When RESET is released functionality is guaranteed down to VPDR min.
2. For operation with voltage higher than VDD +0.3 V, the internal pull-up and pull-down resistors must be disabled.
3. The TA(max) applies to PD(max). At PD < PD(max) the ambient temperature is allowed to go higher than TA(max) provided
that the junction temperature TJ does not exceed TJ(max). Refer to Section 6.6: Thermal characteristics.
4. Temperature range digit in the order code. See Section 7: Ordering information.
5.3.2 Operating conditions at power-up / power-down

The parameters given in Table 24 are derived from tests performed under the ambient
temperature condition summarized in Table 23.
Table 24. Operating conditions at power-up / power-down

Symbol Parameter Min Max Unit
VDD rise time rate 0 ∞

tVDD µs/V
VDD fall time rate 10 ∞
5.3.3 Embedded reset and power control block characteristics

temperature conditions summarized in Table 23.
Table 25. Embedded reset and power control block characteristics

Symbol Parameter Conditions Min Typ Max Unit
tRSTTEMPO (1) POR temporization when VDD crosses VPOR VDD rising - 270 500 µs
VPOR(1) Power-on reset threshold - 1.9 1.94 1.98 V
VPDR(1) Power-down reset threshold - 1.88 1.92 1.96 V
36/92 DS13866 Rev 4

Table 25. Embedded reset and power control block characteristics (continued)
VDD rising 2.05 2.10 2.18

VBOR1 Brownout reset threshold 1 V
VDD falling 1.95 2.00 2.08
VDD rising 2.20 2.31 2.38
VDD falling 2.10 2.21 2.28
VDD rising 2.50 2.62 2.68
VDD falling 2.40 2.52 2.58
VDD rising 2.80 2.91 3.00
VDD falling 2.70 2.81 2.90
Vhyst_POR_PDR Hysteresis of VPOR and VPDR - - 20 - mV
Vhyst_BOR Hysteresis of VBORx - - 100 - mV
IDD(BOR) (1) BOR consumption - - 2.2 2.5 µA
1. Specified by design – Not tested in production.
5.3.4 Embedded voltage reference

temperature and supply voltage conditions summarized in Table 23: General operating
conditions.
Table 26. Embedded internal voltage reference

VREFINT Internal reference voltage - 1.182 1.212 1.232 V

ADC sampling time when reading
tS_vrefint (1)(2) - 4 - - µs
the internal reference voltage
Start time of reference voltage
tstart_vrefint(2) - - 8 12 µs
buffer when ADC is enable
VREFINT buffer consumption from
IDD(VREFINTBUF)(2) - 9 13.5 23 µA
VDD when converted by ADC
Internal reference voltage spread
∆VREFINT(2) VDD = 3 V - 30 50 mV
over the temperature range
TCoeff Averange temperature coefficient - - 20 70 ppm/°C
ACoeff Long term stability 1000 hours, T = 25 °C - 300 1000 ppm
VDDCoeff Voltage coefficient 3.0 V < VDD < 3.6 V - 250 1200 ppm/V
1. The shortest sampling time can be determined in the application by multiple iterations.
DS13866 Rev 4 37/92

77
Figure 11. VREFINT vs. temperature
V
1.235
1.23
1.225
1.22
1.215
1.21
1.205
1.2
1.195
1.19
1.185
-40 -20 0 20 40 60 80 100 120 °C
Mean Min Max
MSv40169V1
5.3.5 Supply current characteristics

The current consumption is a function of several parameters and factors such as the
operating voltage, ambient temperature, I/O pin loading, device software configuration,
operating frequencies, I/O pin switching rate, program location in memory and executed
binary code.
The current consumption is measured as described in Figure 10: Current consumption
measurement scheme.
Typical and maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode
• All peripherals are disabled except when explicitly mentioned
• The flash memory access time is adjusted with the minimum wait states number,
depending on the fHCLK frequency (refer to the table “Number of wait states according
to CPU clock (HCLK) frequency” available in the RM0490 reference manual).
• When the peripherals are enabled fPCLK = fHCLK
• For flash memory and shared peripherals fPCLK = fHCLK = fHCLKS
Unless otherwise stated, values given in Table 27 through Table 34 are derived from tests
performed under ambient temperature and supply voltage conditions summarized in
Table 23: General operating conditions.
38/92 DS13866 Rev 4

STM32C011x4/x6
Table 27. Current consumption in Run mode from flash memory at different die temperatures
Conditions Typ Max(1)
Symbol Parameter Unit
General(2) fHCLK Fetch 25 85 105 125 25 85 105 125
from(3) °C °C °C °C °C °C °C °C
48 MHz 3.05 3.15 3.25 3.35 3.60 3.80 4.10 4.60
32 MHz 2.10 2.15 2.25 2.35 2.50 2.70 3.00 3.50
24 MHz 1.80 1.85 1.90 2.05 2.10 2.40 2.70 3.20
16 MHz 1.25 1.30 1.35 1.45 1.50 1.70 2.00 2.50
fHCLK = fHSE_bypass 8 MHz 0.655 0.710 0.765 0.865 0.790 1.10 1.40 1.90
( > 32.768 kHz),
4 MHz 0.3654 0.420 0.470 0.570 0.460 0.700 0.980 1.50
fHCLK = fLSE_bypass
( = 32.768 kHz) 2 MHz 0.225 0.270 0.325 0.425 0.290 0.540 0.820 1.40
1 MHz 0.150 0.200 0.250 0.350 0.200 0.450 0.730 1.30
500 kHz 0.115 0.160 0.215 0.315 0.160 0.410 0.690 1.20
DS13866 Rev 4
Supply 125 kHz 0.0875 0.135 0.185 0.285 0.130 0.380 0.650 1.20
Flash
IDD(Run) current in mA
32.768 kHz memory 0.082 0.130 0.180 0.280 0.120 0.370 0.650 1.20
Run mode
48 MHz 3.40 3.50 3.55 3.60 3.90 4.10 4.40 4.90
24 MHz 2.25 2.30 2.35 2.45 2.60 2.80 3.10 3.60
12 MHz 1.45 1.50 1.55 1.65 1.70 1.90 2.20 2.70
fHCLK = fHSI48/HSIDIV 6 MHz 1.05 1.10 1.15 1.20 1.20 1.40 1.70 2.20
( > 32 kHz),
3 MHz 0.855 0.880 0.925 1.00 0.960 1.20 1.50 2.00
fHCLK = fLSI
( = 32 kHz) 1.5 MHz 0.750 0.780 0.825 0.915 0.840 1.10 1.40 1.90
750 kHz 0.700 0.730 0.775 0.865 0.780 1.00 1.30 1.80
Electrical characteristics
375 kHz 0.675 0.705 0.750 0.840 0.760 0.970 1.30 1.80
32 kHz 0.082 0.130 0.180 0.280 0.120 0.370 0.650 1.20
1. Evaluated by characterization – Not tested in production.
2. VDD = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled.
3. Prefetch disabled and cache enabled when fetching from flash memory.
39/92
Table 28. Current consumption in Run mode from SRAM at different die temperatures
40/92
General(2) fHCLK Fetch 25 85 105 125 25 85 105 125
from(3) °C °C °C °C °C °C °C °C
48 MHz 2.80 2.90 2.95 3.05 3.20 3.40 3.70 4.20
32 MHz 1.90 1.95 2.00 2.10 2.20 2.40 2.70 3.20
24 MHz 1.45 1.50 1.55 1.65 1.70 1.90 2.20 2.70
16 MHz 0.990 1.05 1.10 1.20 1.20 1.40 1.70 2.20
fHCLK = fHSE_bypass 8 MHz 0.535 0.585 0.635 0.735 0.630 0.860 1.20 1.70
(>32.768 kHz),
4 MHz 0.305 0.355 0.405 0.505 0.380 0.630 0.900 1.40
fHCLK = fLSE_bypass
(=32.768 kHz) 2 MHz 0.195 0.240 0.295 0.390 0.250 0.500 0.770 1.30
1 MHz 0.135 0.185 0.235 0.335 0.180 0.430 0.710 1.30
500 kHz 0.110 0.155 0.205 0.305 0.150 0.400 0.670 1.20
DS13866 Rev 4
Supply 125 kHz 0.0865 0.135 0.185 0.285 0.130 0.370 0.650 1.20
IDD(Run) current in SRAM mA
Run mode 32.768 kHz 0.082 0.130 0.180 0.280 0.120 0.370 0.640 1.20
48 MHz 3.15 3.20 3.25 3.30 3.50 3.70 3.90 4.40
24 MHz 1.90 1.95 2.00 2.05 2.10 2.30 2.60 3.10
12 MHz 1.30 1.30 1.35 1.45 1.50 1.70 1.90 2.40
fHCLK = fHSI48/HSIDIV 6 MHz 0.965 0.995 1.05 1.15 1.15 1.30 1.60 2.10
( > 32 kHz),
3 MHz 0.810 0.835 0.880 0.970 0.900 1.20 1.40 1.90
fHCLK = fLSI
( = 32 kHz) 1.5 MHz 0.730 0.760 0.800 0.890 0.810 1.10 1.30 1.80
750 kHz 0.690 0.720 0.765 0.855 0.770 0.990 1.30 1.80
375 kHz 0.670 0.700 0.745 0.835 0.750 0.970 1.30 1.80
32 kHz 0.082 0.130 0.180 0.280 0.120 0.370 0.640 1.20
STM32C011x4/x6
2. VDD = 3.0 V for values in Typ columns and 3.6 V for values in Max columns, all peripherals disabled.
3. Code compiled with high optimization for space in SRAM.
Table 29. Typical current consumption in Run depending on code executed

Conditions Typ Typ
Symbol Parameter Unit Unit
Fetch
General(1) Code 25 °C 25 °C
from(2)
Reduced code(3) 3.40 70.8

Coremark 3.15 65.6
Flash
Dhrystone 3.20 66.7
memory
Fibonacci 2.40 50.0
fHCLK = fHSE_bypass = WhileLoop 1.80 37.5
48 MHz Reduced code(3) 2.80 58.3
Coremark 2.70 56.3
Dhrystone SRAM 2.70 56.3
Fibonacci 2.85 59.4
WhileLoop 2.15 44.8
mA μA/MHz
Coremark 1.15 71.9
Flash
Dhrystone 1.15 71.9
memory
Fibonacci 0.835 52.2
Supply WhileLoop 0.645 40.3
fHCLK = fHSE_bypass =
IDD(Run) current in
Run mode
Coremark 0.950 59.4
Fibonacci 1.00 62.5
WhileLoop 0.775 48.4
(3)
Reduced code 0.225 112.5
Coremark 0.210 105.0
Flash
Dhrystone 0.210 105.0
memory
fHCLK = fHSE_bypass = WhileLoop 0.150 75.0
μA μA/MHz
Coremark 0.190 95.0
DS13866 Rev 4 41/92

77
Table 29. Typical current consumption in Run depending on code executed (continued)
Conditions Typ Typ
Symbol Parameter Unit Unit
Fetch
General(1) Code 25 °C 25 °C
from(2)

Coremark 3.50 72.9
Flash
Dhrystone 3.55 74.0
memory
Fibonacci 2.75 57.3
fHCLK = fHSI48/HSIDIV WhileLoop 2.15 44.8
= 48 MHz
(HSIDIV = 1) Reduced code(3) 3.15 65.6
Coremark 3.05 63.5
Fibonacci 3.20 66.7
WhileLoop 2.50 52.1
mA μA/MHz
Coremark 1.40 116.7
Flash
memory
Fibonacci 1.15 95.8
Supply fHCLK = fHSI48/HSIDIV WhileLoop 1.00 83.3
IDD(Run) current in = 12 MHz
(HSIDIV = 4) Reduced code(3) 1.30 108.3
Run mode
Coremark 1.25 104.2
WhileLoop 1.10 91.7
(3)
Flash
memory
fHCLK = fHSI48/HSIDIV WhileLoop 0.745 248.3
= 3 MHz (3) μA μA/MHz
(HSIDIV = 16)
1. VDD = 3.0 V, all peripherals disabled
2. Prefetch and cache enabled when fetching from flash
3. Reduced code used for characterization results provided in Table 27.
42/92 DS13866 Rev 4

STM32C011x4/x6
Table 30. Current consumption in Sleep mode
25 85 105 125 25 85 105 125
General fHCLK
°C °C °C °C °C °C °C °C
48 MHz 1.20 1.20 1.25 1.35 1.50 1.70 2.00 2.50
All peripherals 24 MHz 0.92 0.95 0.99 1.10 1.10 1.30 1.60 2.10
disabled, 12 MHz 0.79 0.81 0.86 0.95 0.91 1.20 1.40 1.90
fHCLK = fHSI48/HSIDIV
6 MHz 0.72 0.75 0.79 0.88 0.82 1.10 1.30 1.80
( > 32 kHz),
fHCLK = fLSI 1.5 MHz 0.67 0.70 0.74 0.83 0.75 0.97 1.30 1.80
( = 32 kHz) 375 kHz 0.66 0.69 0.73 0.82 0.73 0.95 1.30 1.80
32 kHz 0.08 0.13 0.18 0.28 0.12 0.37 0.64 1.20
Flash memory enabled 48 MHz 0.820 0.875 0.930 1.05 1.20 1.40 1.70 2.20
DS13866 Rev 4
32 MHz 0.575 0.630 0.680 0.785 0.800 1.10 1.40 1.90

24 MHz 0.450 0.500 0.555 0.655 0.630 0.880 1.20 1.70
Supply 16 MHz 0.325 0.380 0.430 0.535 0.460 0.710 0.980 1.50
current in
IDD(Sleep) 8 MHz 0.205 0.250 0.305 0.405 0.300 0.540 0.820 1.40 mA
Sleep
mode 2 MHz 0.110 0.160 0.210 0.310 0.170 0.420 0.690 1.20
All peripherals
500 kHz 0.0875 0.135 0.185 0.285 0.130 0.380 0.650 1.20
disabled,
fHCLK = fHSE_bypass 32.768 kHz 0.0805 0.125 0.180 0.280 0.120 0.370 0.640 1.20
( > 32.768 kHz), 48 MHz 0.815 0.870 0.925 1.05 1.20 1.40 1.70 2.20
fHCLK = fLSE_bypass
32 MHz 0.570 0.620 0.675 0.775 0.790 1.10 1.40 1.90
( = 32.768 kHz)
24 MHz 0.445 0.495 0.545 0.650 0.630 0.870 1.20 1.70
Flash memory disabled 16 MHz 0.320 0.375 0.425 0.525 0.460 0.700 0.980 1.50
(flash memory power-
down sleep mode) 8 MHz 0.200 0.245 0.295 0.395 0.290 0.530 0.810 1.40
2 MHz 0.105 0.150 0.205 0.300 0.160 0.410 0.680 1.20
500 kHz 0.0815 0.130 0.180 0.280 0.120 0.370 0.650 1.20
32.768 kHz 0.0745 0.120 0.170 0.270 0.110 0.360 0.630 1.20
43/92

Table 31. Current consumption in Stop mode
44/92
Typ Max(1)
Symbol Parameter Conditions VDD Unit
25 85 105 125 25 85 105 125
°C °C °C °C °C °C °C °C
2V 79.0 125 175 275 110 350 610 1100

2.4 V 79.0 125 175 275 110 350 610 1100
All clocks off
3V 80.0 125 180 275 110 350 610 1100
3.6 V 81.5 130 180 280 110 350 610 1100
2V 70.5 120 170 270 97.0 340 600 1100
All clocks off 2.4 V 72.0 120 170 270 98.0 340 600 1100
Flash memory in power-down stop
mode 3V 73.5 120 170 270 100 340 600 1100
3.6 V 75.0 120 175 270 110 340 600 1100
DS13866 Rev 4
2V 78.0 125 175 275 110 350 610 1100
Supply current RTC enabled and supplied with 2.4 V 78.5 125 175 275 110 350 610 1100
IDD(Stop) µA
in Stop mode LSE bypass (32.768 kHz) 3V 80.0 125 180 275 110 350 610 1100
3.6 V 82.0 130 180 280 110 350 610 1100
2V 71.0 120 170 270 97.0 340 600 1100
RTC enabled and supplied with
LSE bypass (32.768 kHz) 2.4 V 72.5 120 170 270 98.0 340 600 1100
Flash memory in power-down stop 3V 74.0 120 170 270 100 340 600 1100
mode
3.6 V 75.5 120 175 270 110 340 600 1100
2V 605 630 675 765 640 850 1100 1600
2.4 V 605 630 675 765 640 850 1100 1600
HSI Kernel on
3V 605 630 675 765 640 850 1200 1600
STM32C011x4/x6
3.6 V 605 635 680 770 640 850 1200 1600
Table 32. Current consumption in Standby mode
STM32C011x4/x6
Typ Max(1)
Symbol Parameter Conditions VDD 25 85 105 125 25 85 105 125 Unit
°C °C °C °C °C °C °C °C
2V 6.75 7.70 8.55 10.5 7.50 8.90 11.0 16.0
2.4 V 7.05 8.00 8.85 11.0 7.70 9.10 11.0 17.0
All clocks off
3V 7.45 8.45 9.45 12.0 8.20 9.70 12.0 18.0
Supply
current in 3.6 V 7.90 8.95 10.0 12.5 8.70 11.0 13.0 20.0
IDD(Standby) µA
Standby 2V 7.30 8.35 9.20 11.5 8.10 9.50 12.0 17.0
mode IWDG
enabled and 2.4 V 7.65 8.65 9.60 11.5 8.30 9.80 12.0 17.0
clocked by 3V 8.10 9.20 10.0 12.5 8.90 11.0 13.0 19.0
LSI
3.6 V 8.60 9.75 11.0 13.5 9.50 12.0 14.0 21.0
DS13866 Rev 4
Table 33. Current consumption in Shutdown mode

Typ Max(1)
Symbol Parameter Conditions VDD Unit
25 °C 85 °C 105 °C 125 °C 25 °C 85 °C 105 °C 125 °C
2V 9.00 290 835 2350 55 920 2700 7600
Supply
current in All clocks 2.4 V 13.0 320 915 2550 62 970 2900 7900
IDD(Shutdown) nA
Shutdown off 3.0 V 19.0 375 1050 2900 72 1200 3300 8900
mode
3.6 V 31.0 460 1250 3350 95 1400 3800 11000
45/92
I/O system current consumption
The current consumption of the I/O system has two components: static and dynamic.
I/O static current consumption
All the I/Os used as inputs with pull-up or pull-down resistor generate current consumption
when the pin is externally held low or high, respectively. The value of this current
consumption can be simply computed by using the pull-up/pull-down resistors values given
in Table 49: I/O static characteristics.
For the output pins, any pull-up or pull-down device (internal and external) and external load
must also be considered to estimate the current consumption.
Additional I/O current consumption is due to I/Os configured as inputs if an intermediate
voltage level is externally applied. This current consumption is caused by the input Schmitt
trigger circuits used to discriminate the input value. Unless this specific configuration is
required by the application, this supply current consumption can be avoided by configuring
these I/Os in analog mode. This is notably the case of ADC input pins which should be
configured as analog inputs.
Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently,
as a result of external electromagnetic noise. To avoid current consumption related to
floating pins, they must either be configured in analog mode, or forced internally to a definite
digital value. This can be done either by using pull-up/down resistors or by configuring the
pins in output mode.
I/O dynamic current consumption
In addition to the internal peripheral current consumption measured previously (see
Table 34: Current consumption of peripherals), the I/Os used by an application also
contribute to the current consumption. When an I/O pin switches, it uses the current from
the I/O supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive
load (internal and external) of the pin:
I SW = V DDIO1 × f SW × C
where
ISW is the current sunk by a switching I/O to charge/discharge the capacitive load
VDDIO1 is the I/O supply voltage
fSW is the I/O switching frequency
C is the total capacitance seen by the I/O pin: C = CINT+ CEXT + CS
CS is the PCB board capacitance including the pad pin.
The test pin is configured in push-pull output mode and is toggled by software at a fixed
frequency.
46/92 DS13866 Rev 4

On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in the following table. The MCU
is placed under the following conditions:
• All I/O pins are in Analog mode
• The given value is calculated by measuring the difference of the current consumptions:
– when the peripheral is clocked on
– when the peripheral is clocked off
• Ambient operating temperature and supply voltage conditions summarized in Table 20:
Voltage characteristics
• The power consumption of the digital part of the on-chip peripherals is given in the
following table. The power consumption of the analog part of the peripherals (where
applicable) is indicated in each related section of the datasheet.
Table 34. Current consumption of peripherals

Consumption in
Peripheral Bus
µA/MHz
IOPORT bus 0.72
GPIOA 1.64
GPIOB IOPORT 1.64
GPIOC 0.82
GPIOF 0.74
Bus matrix 0.31
All AHB peripherals 8
DMA1 2.64
AHB
FLASH 4.56
SRAM1 0.01
CRC1 0.48
All APB peripherals 30.76
AHB to APB bridge (2) 0.32
TIM3 3.66
RTCAPB 1.13
WWDG1 0.48
USART2 2.01
APB
I2C1 3.44
I2C1 independent clock domain 2.59
DBGMCU1 0.09
PWR 0.3
SYSCFG 0.4
TIM1 5.84
DS13866 Rev 4 47/92

77
Table 34. Current consumption of peripherals (continued)

Consumption in
Peripheral Bus
µA/MHz
SPI1 3.18
SPI1 independent clock domain 1.44
USART1 2.22
USART1 independent clock domain 5.77
TIM14 APB 1.42
TIM16 2.54
TIM17 2.45
ADC1 1.92
ADC1 independent clock domain 0.12
All peripherals 43.56
5.3.6 Wake-up time from low-power modes

The wake-up times given in Table 35 are the latency between the event and the execution of
the first user instruction.
Table 35. Low-power mode wake-up times(1)

Symbol Parameter Conditions Typ Max Unit
Transiting to Run-mode execution in CPU
flash memory powered during Sleep 10 12 clock
Wake-up time
HCLK = HSI48/4 = mode cycles
tWUSLEEP from Sleep to Run
12 MHz Transiting to Run-mode execution in
mode
flash memory not powered during 4.75 5.02 µs
Sleep mode
Transiting to Run-mode execution in

flash memory powered during Stop 2.7 3.1
Clock after mode
Wake-up time wake-up is HCLK Transiting to Run-mode execution in
tWULPSTOP
from Stop mode = HSI48/4 = 12 flash memory not powered during 5.9 6.4
MHz Stop mode
Transiting to Run-mode execution in µs
2.5 2.9
SRAM
Wake-up time Clock after wake-
tWUSTBY from Standby up is HCLK = Transiting to Run mode 23 35
mode HSI48/4 = 12 MHz
Wake-up time Clock after wake-
tWUSHDN from Shutdown up is HCLK = Transiting to Run mode 385 466
mode HSI48/4 = 12 MHz
48/92 DS13866 Rev 4

5.3.7 External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.13. See
Figure 12 for recommended clock input waveform.
Table 36. High-speed external user clock characteristics(1)

User external clock source

fHSE_ext - - 8 48 MHz
frequency
Digital OSC_IN input pin high
VHSEH - 0.7 VDD - VDD
level voltage
V
Digital OSC_IN input pin low
VHSEL - VSS - 0.3 VDD
level voltage
tw(HSEH)/
Digital OSC_IN high or low time - 7 - - ns
tw(HSEL)
Figure 12. High-speed external clock source AC timing diagram
tw(HSEH)
VHSEH
90%
10%
VHSEL
tr(HSE) t
tf(HSE) tw(HSEL)
THSE
MS19214V2
Low-speed external user clock generated from an external source

In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in Section 5.3.13. See
Figure 13 for recommended clock input waveform.
Table 37. Low-speed external user clock characteristics(1)

fLSE_ext User external clock source frequency - - 32.768 1000 kHz
DS13866 Rev 4 49/92

77
Table 37. Low-speed external user clock characteristics(1) (continued)

OSC32_IN input pin high level

VLSEH - 0.7 VDDIO1 - VDDIO1
voltage V
VLSEL OSC32_IN input pin low level voltage - VSS - 0.3 VDDIO1
tw(LSEH)/
OSC32_IN high or low time - 250 - - ns
tw(LSEL)
Figure 13. Low-speed external clock source AC timing diagram
tw(LSEH)
VLSEH
90%
10%
VLSEL
tr(LSE) t
tf(LSE) tw(LSEL)
TLSE
MS19215V2
High-speed external clock generated from a crystal/ceramic resonator

The high-speed external (HSE) clock can be supplied with a 4 to 48 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design
simulation results obtained with typical external components specified in Table 38. In the
application, the resonator and the load capacitors have to be placed as close as possible to
the oscillator pins in order to minimize output distortion and startup stabilization time. Refer
to the crystal resonator manufacturer for more details on the resonator characteristics
(frequency, package, accuracy).
Table 38. HSE oscillator characteristics(1)

Symbol Parameter Conditions(2) Min Typ Max Unit
fOSC_IN Oscillator frequency - 4 - 48 MHz

RF Feedback resistor - - 200 - kΩ
50/92 DS13866 Rev 4

Table 38. HSE oscillator characteristics(1) (continued)

(3)
During startup - - 5.5
VDD = 3 V,
Rm = 30 Ω, - 0.58 -
CL = 10 pF@8 MHz
VDD = 3 V,
Rm = 45 Ω, - 0.59 -
CL = 10 pF@8 MHz
IDD(HSE) HSE current consumption VDD = 3 V, mA

Rm = 30 Ω, - 0.89 -
CL = 5 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω, - 1.14 -
CL = 10 pF@48 MHz
VDD = 3 V,
Rm = 30 Ω, - 1.94 -
CL = 20 pF@48 MHz
Maximum critical crystal
Gm Startup - - 1.5 mA/V
transconductance
tSU(HSE)(4) Startup time VDD is stabilized - 2 - ms
2. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 20 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 14). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2.
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
DS13866 Rev 4 51/92

77
Figure 14. Typical application with an 8 MHz crystal
Resonator with integrated

capacitors
CL1
OSC_IN fHSE
Bias
8 MHz controlled
resonator RF gain
REXT (1) OSC_OUT

CL2
MS19876V1
1. REXT value depends on the crystal characteristics.
Low-speed external clock generated from a crystal resonator

The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal resonator
oscillator. All the information given in this paragraph are based on design simulation results
obtained with typical external components specified in Table 39. In the application, the
resonator and the load capacitors have to be placed as close as possible to the oscillator
pins in order to minimize output distortion and startup stabilization time. Refer to the crystal
resonator manufacturer for more details on the resonator characteristics (frequency,
package, accuracy).
Table 39. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)

LSEDRV = 0
- 500 -
Medium high drive capability
IDD(LSE) LSE current consumption nA
LSEDRV = 1
- 630 -
High drive capability
LSEDRV = 0
- - 1.7
Maximum critical crystal Medium high drive capability
Gmcritmax µA/V
gm LSEDRV = 1
- - 2.7
High drive capability
tSU(LSE)(3) Startup time VDD is stabilized - 2 - s
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is
reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer
Note: For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
52/92 DS13866 Rev 4

Figure 15. Typical application with a 32.768 kHz crystal
Resonator with integrated

capacitors
CL1
OSC32_IN fLSE
32.768 kHz Drive

resonator programmable
amplifier
OSC32_OUT
CL2
MS30253V2
Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
5.3.8 Internal clock source characteristics

The parameters given in Table 40 are derived from tests performed under ambient
temperature and supply voltage conditions summarized in Table 23: General operating
conditions. The provided curves are characterization results, not tested in production.
High-speed internal (HSI48) RC oscillator
Table 40. HSI48 oscillator characteristics

fHSI48 HSI48 Frequency VDD=3.0 V, TA=30 °C 47.92 - 48.40 MHz

HSI48 oscillator frequency TA= 0 to 85 °C -1 - 1 %
∆Temp(HSI)(1) drift over temperature and
VDD full voltage range TA= -40 to 125 °C -2.5 - 2 %
From code 127 to
-8 -6 -4
128
From code 63 to 64
HSI48 oscillator frequency
TRIM(1) From code 191 to -5.8 -3.8 -1.8 %
user trimming step
192
For all other code
0.2 0.3 0.4
increments
DHSI48(2) Duty cycle - 45 - 55 %
tsu(HSI48)(2) HSI48 oscillator start-up time - - 1.4 1.8 μs
HSI48 oscillator stabilization at 1% of target
tstab(HSI48)(2) - 1.5 3.6 μs
time frequency
HSI48 oscillator power
IDD(HSI48)(1) - - 525 570 μA
consumption
1. Based on characterization results, not tested in production
DS13866 Rev 4 53/92

77
Figure 16. HSI48 frequency versus temperature
Frequency [MHz]
Temperature
MS55839V1
Low-speed internal (LSI) RC oscillator
Table 41. LSI oscillator characteristics

VDD = 3.3 V, TA = 25 °C 31.04 32 32.96

fLSI LSI frequency 29.5 kHz
VDD = 2 V to 3.6 V, TA = -40 to 125 °C (1) - 34(1)
tSU(LSI)(2) LSI oscillator start-up time - - 80 130 μs

tSTAB(LSI)(2) LSI oscillator stabilization time 5% of final frequency - 125 180 μs
LSI oscillator power
IDD(LSI)(2) - - 110 180 nA
consumption
5.3.9 flash memory characteristics
Table 42. Flash memory characteristics(1)

tprog Word programming time 64 bits - 85.0 125.0 µs
Row (32 double word) Normal programming - 2.7 4.6

tprog_row
programming time Fast programming - 1.7 2.8
Page (2 Kbyte) programming Normal programming - 21.8 36.6 ms

tprog_page
time Fast programming - 13.7 22.4
tERASE Page (2 Kbyte) erase time - - 22.0 40.0
54/92 DS13866 Rev 4

Table 42. Flash memory characteristics(1) (continued)

Bank (32 Kbyte(2)) Normal programming - 0.4 0.6

tprog_bank s
programming time Fast programming - 0.2 0.4
tME Mass erase time - - 22.1 40.1 ms
Programming - 3.0 -
Average consumption from
IDD(FlashA) Page erase - 3.0 - mA
VDD
Mass erase - 5.0 -
Programming, 2 µs peak
- 7.0 -
IDD(FlashP) Maximum current (peak) duration mA
Erase, 41 µs peak duration - 7.0 -
2. Values provided also apply to devices with less flash memory than one 32 Kbyte bank
Table 43. Flash memory endurance and data retention

Symbol Parameter Conditions Min(1) Unit
NEND Endurance TJ = -40 to +130 °C 10 kcycles

1 kcycle(2) at TA = 85 °C 30
(2)
1 kcycle at TA = 105 °C 15
(2)
1 kcycle at TA = 125 °C 7
tRET Data retention Years
10 kcycles(2) at TA = 55 °C 30
10 kcycles(2) at TA = 85 °C 15
(2)
10 kcycles at TA = 105 °C 10
1. Evaluated by characterization – Not tested in production..
2. Cycling performed over the whole temperature range.
DS13866 Rev 4 55/92

77
5.3.10 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 44. They are based on the EMS levels and classes
defined in application note AN1709.
Table 44. EMS characteristics

Level/
Symbol Parameter Conditions
Class
VDD = 3.3 V, TA = +25 °C,

Voltage limits to be applied on any I/O pin to
VFESD fHSE = fHCLK = 48 MHz, LQFP48, 2B
induce a functional disturbance
conforming to IEC 61000-4-2
Fast transient voltage burst limits to be applied VDD = 3.3 V, TA = +25 °C,
VEFTB through 100 pF on VDD and VSS pins to induce a fHSE = fHCLK = 48 MHz, LQFP48, 4B
functional disturbance conforming to IEC 61000-4-2
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• corrupted program counter
• unexpected reset
• critical data corruption (for example control registers)
56/92 DS13866 Rev 4

Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic interference (EMI)

The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
The following table gives the EMI characteristics for fHSI48 and fHCLK of 48 MHz.
Table 45. EMI characteristics

Max vs. Max vs.
[fHSE/fCPU] [fHSI/fCPU]
Monitored
Symbol Parameter Conditions Unit
frequency band
48 MHz / 48 MHz /
48 MHz 48 MHz
0.1 MHz to 30 MHz 3 3

VDD = 3.6 V, TA = 25 °C, 30 MHz to 130 MHz 5 -2
Peak(1) LQFP48 package dBµV
SEMI 130 MHz to 1 GHz 1 -1
compliant with IEC
61967-2 1 GHz to 2 GHz 7 8
Level(2) 0.1 MHz to 2 GHz 2 2 -
1. Refer to AN1709, section EMI radiated test
2. Refer to AN1709, section EMI level classification
5.3.11 Electrical sensitivity characteristics

Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
DS13866 Rev 4 57/92

77
Table 46. ESD absolute maximum ratings

Maximum
Symbol Ratings Conditions Package Class Unit
value(1)
Electrostatic
TA = +25 °C, conforming to
VESD(HBM) discharge voltage All 1C -2000/+1500
ANSI/ESDA/JEDEC JS-001
(human body model)
V
Electrostatic
TA = +25 °C, conforming to
VESD(CDM) discharge voltage All C2a 500
ANSI/ESDA/JEDEC JS-002
(charge device model)
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
• A supply overvoltage is applied to each power supply pin.
• A current is injected to each input, output and configurable I/O pin.
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 47. Electrical sensitivity

Symbol Parameter Conditions Class
LU Static latch-up class TA = +125 °C conforming to JESD78 II Level A
5.3.12 I/O current injection characteristics

As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDDIO1 (for standard, 3.3 V-capable I/O pins) should be avoided during normal
product operation. However, in order to give an indication of the robustness of the
microcontroller in cases when abnormal injection accidentally happens, susceptibility tests
are performed on a sample basis during device characterization.
Functional susceptibility to I/O current injection

While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out-of-range parameter: ADC error above a certain limit
(higher than 5 LSB TUE), induced leakage current on adjacent pins out of conventional
limits (-5 µA/+0 µA range) or other functional failure (for example reset occurrence or
oscillator frequency deviation).
Negative induced leakage current is caused by negative injection and positive induced
leakage current is caused by positive injection.
58/92 DS13866 Rev 4

Table 48. I/O current injection susceptibility(1)

Functional susceptibility
Symbol Description Unit
Negative Positive
injection injection
Injected current on
IINJ(2) Any IO 5 NA mA
pin
2. The injection current value is applicable when the switchable diode is activated, NA when not activated.
5.3.13 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 49 are derived from tests
performed under the conditions summarized in Table 23: General operating conditions. All
I/Os are designed as CMOS- and TTL-compliant.
For information on GPIO configuration, refer to the application note AN4899 STM32 GPIO
configuration for hardware settings and low-power consumption, available on the ST
website www.st.com.
Table 49. I/O static characteristics

I/O input low level

VIL(1) All 2 V < VDDIO1 < 3.6 V - - 0.3 x VDDIO1 V
voltage
I/O input high level
VIH(1) All 2 V < VDDIO1 < 3.6 V 0.7 x VDDIO1 - - V
voltage
Vhys(2) I/O input hysteresis - - 200 - mV
0 < VIN ≤ VDDIO1 - -70 -
(3) Input leakage
Ilkg VDDIO1 ≤ VIN ≤ VDDIO1 +1 V - 600 - nA
current(3)
VDDIO1 +1 V ≤ VIN - 150 -
Weak pull-up
RPU equivalent resistor VIN = VSS 25 40 55 kΩ
(4)
Weak pull-down
RPD V = VDDIO1 25 40 55 kΩ
equivalent resistor(4) IN
CIO I/O pin capacitance - - 5 - pF
1. Refer to Figure 17: I/O input characteristics.
3. This parameter represents the pad leakage of the I/O itself. The total product pad leakage is provided by the following
formula: ITotal_Ileak_max = 10 μA + [number of I/Os where VIN is applied on the pad] ₓ Ilkg(Max).
4. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
PMOS/NMOS contribution to the series resistance is minimal (~10% order).
DS13866 Rev 4 59/92

77
All I/Os are CMOS- and TTL-compliant (no software configuration required). Their
characteristics cover more than the strict CMOS-technology or TTL parameters, as shown
in Figure 17.
Figure 17. I/O input characteristics
TTL requirement Vih min = 2V
V DDIO
x
>1.62
= 0.7x 6for V DD
IOx
min +0.2
t Vih 9xV DD
IOx
iremen 2o r 0.4
requ x<1.6 >1.62
OS <V DDIO r VDDIOx
on CM for 1.08 x-0
.06 fo
ucti x+
0.05 9xVDDIO
prod DDIO .62 or
0.3
te d in =0 .61xV x<1
Tes <VDDIO
nV ih min r 1.08
ulatio -0.1 fo
n sim xV DDIOx
sed o max =0.43 TTL requirement Vil max = 0.8V
Ba tion Vil 0.3xVdd
on simula ent V il max =
Based S requirem
on CMO
in producti
Tested
MSv37613V1
Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±6 mA, and up to
±15 mA with relaxed VOL/VOH.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 5.2:
• The sum of the currents sourced by all the I/Os on VDDIO1, plus the maximum
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD (see Table 20: Voltage characteristics).
• The sum of the currents sunk by all the I/Os on VSS, plus the maximum consumption of
the MCU sunk on VSS, cannot exceed the absolute maximum rating IVSS (see Table 20:
Voltage characteristics).
Output voltage levels

Unless otherwise specified, the parameters given in the table below are derived from tests
performed under the ambient temperature and supply voltage conditions summarized in
Table 23: General operating conditions. All I/Os are CMOS- and TTL-compliant (FT OR TT
unless otherwise specified).
60/92 DS13866 Rev 4

Table 50. Output voltage characteristics(1)

VOL Output low level voltage CMOS port(2) - 0.4

|IIO| = 8 mA
VOH Output high level voltage VDD ≥ 2.7 V VDD - 0.4 -
VOL(3) Output low level voltage TTL port(2) - 0.4

|IIO| = 8 mA
VOH(3) Output high level voltage VDD ≥ 2.7 V 2.4 -
VOL(3) Output low level voltage All I/Os - 1.3

|IIO| = 20 mA
VOH(3) Output high level voltage VDD- 1.3 - V
VDD ≥ 2.7 V
VOL(3) Output low level voltage |IIO| = 4 mA - 0.45
VOH(3) Output high level voltage VDD ≥ 2.0 V VDD - 0.45 -
|IIO| = 20 mA
- 0.4
VOLFM+ Output low level voltage for an FT I/O VDD ≥ 2.7 V
(3) pin in FM+ mode |IIO| = 10 mA
- 0.4
VDD ≥ 2.0 V
1. The IIO current sourced or sunk by the device must always respect the absolute maximum rating specified inTable 20:
Voltage characteristics . The sum of the currents sourced or sunk by all the I/Os (I/O ports and control pins) must always
respect the absolute maximum ratings ∑IIO.
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 18 and
Table 51, respectively.
Unless otherwise specified, the parameters given are derived from tests performed under
the ambient temperature and supply voltage conditions summarized in Table 23: General
operating conditions.
Table 51. I/O AC characteristics(1)(2)

Speed Symbol Parameter Conditions Min Max Unit
C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 2
C=50 pF, 2 V ≤ VDD ≤ 2.7 V - 0.35
Fmax Maximum frequency MHz
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 3.00
C=10 pF, 2 V ≤ VDD ≤ 2.7 V - 0.45
00
C=50 pF,2.7 V ≤ VDD ≤ 3.6 V - 100.00
C=50 pF, 2 V ≤ VDD ≤ 2.7 V - 225.00
Tr/Tf Output rise and fall time(3) ns
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 75.00
C=10 pF, 2 V ≤ VDD ≤ 2.7 V - 150.00
DS13866 Rev 4 61/92

77
Table 51. I/O AC characteristics(1)(2) (continued)

Speed Symbol Parameter Conditions Min Max Unit
C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 10.00
C=50 pF, 2 V ≤ VDD ≤ 2.7 V - 2.00
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 15.00
C=10 pF, 2 V ≤ VDD ≤ 2.7 V - 2.50
01
C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 30.00
C=50 pF, 2 V ≤ VDD ≤ 2.7 V - 60.00
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 15.00
C=10 pF, 2 V ≤ VDD ≤ 2.7 V - 30.00
C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 30.00
C=50 pF, 2 V ≤ VDD ≤ 2.7 V - 15.00
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 60.00(4)
C=10 pF, 2 V ≤ VDD ≤ 2.7 V - 30.00
10
C=50 pF, 2.7 V ≤ VDD ≤ 3.6 V - 11.00
C=50 pF, 2 V ≤ VDD ≤ 2.7 V - 22.00
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 4.00
C=10 pF, 2 V ≤ VDD ≤ 2.7 V - 8.00
C=30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 60.00(4)
C=30 pF, 2 V ≤ VDD ≤ 2.7 V - 30.00
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 80.00(4)
C=10 pF, 2 V ≤ VDD ≤ 2.7 V - 40.00
11
C=30 pF, 2.7 V ≤ VDD ≤ 3.6 V - 5.50
C=30 pF, 2 V ≤ VDD ≤ 2.7 V - 11.00
C=10 pF, 2.7 V ≤ VDD ≤ 3.6 V - 2.50
C=10 pF, 2 V ≤ VDD ≤ 2.7 V - 5.00
1. The I/O speed is configured using the OSPEEDRy[1:0] bits. The Fm+ mode is configured in the SYSCFG_CFGR1 register.
Refer to the RM0490 reference manual for a description of GPIO Port configuration register.
3. The fall time is defined between 70% and 30% of the output waveform, according to I2C specification.
4. This value represents the I/O capability but the maximum system frequency is limited to 48 MHz.
62/92 DS13866 Rev 4

Figure 18. I/O AC characteristics definition(1)
90% 10%
50% 50%
10% 90%
t r(IO)out t f(IO)out
Maximum frequency is achieved with a duty cycle at (45 - 55%) when loaded by the
specified capacitance.
1. Refer to Table 51: I/O AC characteristics.
5.3.14 NRST input characteristics

The NRST input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU.
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under the ambient temperature and supply voltage conditions summarized
in Table 23: General operating conditions.
Table 52. NRST pin characteristics

NRST input low level

VIL(NRST) - - - 0.3 x VDD
voltage
V
NRST input high level
VIH(NRST) - 0.7 x VDD - -
voltage
NRST Schmitt trigger
Vhys(NRST) - - 200 - mV
voltage hysteresis
Weak pull-up
RPU(1) VIN = VSS 25 40 55 kΩ
equivalent resistor(2)
NRST input filtered
VF(NRST) (1) 2.0 V < VDD < 3.6 V - - 70 ns
pulse
NRST input not filtered
VNF(NRST)(1) 2.0 V < VDD < 3.6 V 350 - - ns
pulse
1. Specified by design – Not tested in production..
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is minimal (~10% order).
DS13866 Rev 4 63/92

77
Figure 19. Recommended NRST pin protection
External
reset circuit(1) VDD
RPU
NRST(2) Internal reset
Filter
0.1 μF(3)
MS19878V3
1. The reset network protects the device against parasitic resets.

2. The user must ensure that, upon power-on, the level on the NRST pin can exceed the minimum VIH(NRST)
level specified in Table 52: NRST pin characteristics. Otherwise, the device does not exit the power-on
reset. This applies to any NRST configuration set through the NRST_MODE[1:0] bitfield, the GPIO mode
inclusive.
3. The external capacitor on NRST must be placed as close as possible to the device.
5.3.15 Analog-to-digital converter characteristics

Unless otherwise specified, the parameters given in Table 53 are preliminary values derived
from tests performed under ambient temperature, fPCLK frequency and VDDA supply voltage
conditions summarized in Table 23: General operating conditions.
Note: It is recommended to perform a calibration after each power-up.
Table 53. ADC characteristics(1)

Analog supply
VDDA - 2.0 - 3.6 V
voltage
Positive reference
VREF+ - 2 - VDD V
voltage
ADC clock
fADC - 0.14 - 35 MHz
frequency
12 bits - - 2.50
10 bits - - 2.92
fs Sampling rate MSps
8 bits - - 3.50
6 bits - - 4.38
External trigger fADC = 35 MHz; 12 bits - - 2.33

fTRIG MHz
frequency 12 bits - - fADC/15
Conversion voltage
VAIN - 0 - VREF+(2) V
range
External input
RAIN - - - 50 kΩ
impedance
64/92 DS13866 Rev 4

Table 53. ADC characteristics(1) (continued)

Internal sample and

CADC - - 5 - pF
hold capacitor
Conversion
tSTAB ADC power-up time LDO already started 2
cycle
fADC = 35 MHz 2.35 µs
tCAL Calibration time
- 82 1/fADC
Trigger conversion CKMODE = 00 2 - 3 1/fADC
latency for regular
CKMODE = 01 6.5
and injected
tLATR
channels without CKMODE = 10 12.5 1/fPCLK
aborting the
conversion CKMODE = 11 3.5
0.043 - 4.59 µs
ts Sampling time fADC = 35 MHz
1.5 - 160.5 1/fADC
ADC voltage
tADCVREG_S regulator start-up - - - 20 µs
TUP time
fADC = 35 MHz
Total conversion 0.40 - 4.95 µs
Resolution = 12 bits
time
tCONV ts + 12.5 cycles for successive
(including sampling
time) Resolution = 12 bits approximation 1/fADC
= 14 to 173
Laps of time
allowed between
tIDLE - - - 100 µs
two conversions
without rearm
fs = 2.5 MSps - 410 -
ADC consumption
IDDA(ADC) fs = 1 MSps - 164 - µA
from VDDA
fs = 10 kSps - 17 -
fs = 2.5 MSps - 65 -
ADC consumption
IDDV(ADC) fs = 1 MSps - 26 - µA
from VREF+
fs = 10 kSps - 0.26 -
2. VREF+ is internally connected to VDDA on some packages.Refer to Section 4: Pinouts, pin description and alternate
functions for further details.
DS13866 Rev 4 65/92

77
Table 54. Maximum ADC RAIN .

Sampling time at 35 MHz Max. RAIN(1)
Resolution Sampling cycle at 35 MHz
[ns] (Ω)
1.5 43 50
3.5 100 680
7.5 214 2200
12.5 357 4700
12 bits
19.5 557 8200
39.5 1129 15000
79.5 2271 33000
160.5 4586 50000
1.5 43 68
3.5 100 820
7.5 214 3300
12.5 357 5600
10 bits
19.5 557 10000
39.5 1129 22000
79.5 2271 39000
160.5 4586 50000
1.5 43 82
3.5 100 1500
7.5 214 3900
12.5 357 6800
8 bits
19.5 557 12000
39.5 1129 27000
79.5 2271 50000
160.5 4586 50000
1.5 43 390
3.5 100 2200
7.5 214 5600
12.5 357 10000
6 bits
19.5 557 15000
39.5 1129 33000
79.5 2271 50000
160.5 4586 50000
66/92 DS13866 Rev 4

Table 55. ADC accuracy(1)(2)

VDDA = VREF+ = 3 V
Total - ±3 ±4
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25°C
ET unadjusted
error 2 V < VDDA = VREF+ < 3.6 V
- ±3 ±6.5
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = entire range
VDDA = VREF+ = 3 V
- ±1.5 ±2
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25°C
EO Offset error
2 V < VDDA = VREF+ < 3.6 V
- ±1.5 ±4.5
VDDA = VREF+ = 3 V
- ±3 ±3.5
fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
EG Gain error LSB
2 V < VDDA = VREF+ < 3.6 V
- ±3 ±5
VDDA = VREF+ = 3 V
- ±1.2 ±1.5
Differential fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
ED
linearity error 2 V < VDDA = VREF+ < 3.6 V
- ±1.2 ±1.5
VDDA = VREF+ = 3 V
- ±2.5 ±3
Integral linearity fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
EL
error 2 V < VDDA = VREF+ < 3.6 V
- ±2.5 ±3
VDDA = VREF+ = 3 V
10.1 10.2 -
Effective fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
ENOB bit
number of bits 2 V < VDDA = VREF+ < 3.6 V
9.6 10.2 -
VDDA = VREF+ = 3 V
Signal-to-noise f 62.5 63 -
ADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
SINAD and distortion dB
ratio 2 V < VDDA = VREF+ < 3.6 V
59.5 63 -
VDDA = VREF+ = 3 V
63 64 -
Signal-to-noise fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
SNR dB
ratio 2 V < VDDA = VREF+ < 3.6 V
60 64 -
VDDA = VREF+ = 3 V
- -74 -73
Total harmonic fADC = 35 MHz, fs ≤ 2.5 Msps, TA = 25 °C
THD dB
distortion 2 V < VDDA = VREF+ < 3.6 V
- -74 -70
2. ADC DC accuracy values are measured after internal calibration.
DS13866 Rev 4 67/92

77
Figure 20. ADC accuracy characteristics

VREF+ VDDA
[1LSB = (or )]
Output code 2n 2n
EG
n
(1) Example of an actual transfer curve
2 -1 (2) Ideal transfer curve
2n-2 (3) End-point correlation line
2n-3 (2)
n = ADC resolution
ET = total unadjusted error: maximum deviation
(3) between the actual and ideal transfer curves
ET
7 (1) EO = offset error: maximum deviation between the first
actual transition and the first ideal one
6
EL EG = gain error: deviation between the last ideal
5 EO
transition and the last actual one
4 ED = differential linearity error: maximum deviation
ED between actual steps and the ideal one
3
2 EL = integral linearity error: maximum deviation between
1 any actual transition and the end point correlation line
1 LSB ideal
0 VREF+ (VDDA)
(1/2n)*VREF+
(2/2n)*VREF+
(3/2n)*VREF+
(4/2n)*VREF+
(5/2n)*VREF+
(6/2n)*VREF+
(7/2n)*VREF+
(2n-3/2n)*VREF+
(2n-2/2n)*VREF+
(2n-1/2n)*VREF+
(2n/2n)*VREF+
VSSA
MSv19880V6
Figure 21. ADC typical connection diagram
VDDA(4) VREF+(4)
I/O Sample-and-hold ADC converter

analog
RAIN(1) switch RADC
Converter
(2)
Cparasitic Ilkg(3) CADC
VAIN Sampling
switch with
multiplexing
VSS VSS VSSA
MSv67871V3
1. Refer to Table 53: ADC characteristics for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (refer to Table 49: I/O static characteristics for the value of the pad capacitance). A high
Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced.
3. Refer to Table 49: I/O static characteristics for the values of Ilkg.
4. Refer to Figure 2: Power supply overview.
General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 9: Power supply scheme.
The 100 nF capacitor should be ceramic (good quality) and it should be placed as close as
possible to the chip.
68/92 DS13866 Rev 4

5.3.16 Temperature sensor characteristics
Table 56. Temperature sensor characteristics

Symbol Parameter Min Typ Max Unit
TL(1) VSENSE linearity with temperature - ±1 ±5 °C

(2)
Avg_Slope Average slope from VSENSE voltage 2.4 2.53 2.65 mV/°C
V30(3) Voltage at 30°C (±5 °C) 0.742 0.76 0.786 V
tSTART(TS_BUF)(1) Sensor Buffer Start-up time in continuous mode - 8 15
tSTART(1) Start-up time when entering in continuous mode - 8 120 µs
tS_temp(1) ADC sampling time when reading the temperature 5 - -
Temperature sensor consumption from VDD, when

isens (1) - 4.7 7.0 µA
selected by ADC
3. Measured at VDDA = 3.0 V ±10 mV. The V30 ADC conversion result is stored in the TS_CAL1 byte.
5.3.17 Timer characteristics

The parameters given in the following tables are specified by design. Refer to
Section 5.3.13: I/O port characteristics for details on the input/output alternate function
characteristics (output compare, input capture, external clock, PWM output).
Table 57. TIMx(1) (2)characteristics

- 1 - tTIMxCLK
tres(TIM) Timer resolution time
fTIMxCLK = 48 MHz 20.833 - ns
Timer external clock frequency
fEXT - 0 fTIMxCLK/4 MHz
on CH1 to CH4
ResTIM Timer resolution TIMx - 16 bit
tCOUNTER 16-bit counter clock period - 1 65536 tTIMxCLK
Maximum possible count with
tMAX_COUNT - - 65536 tTIMxCLK
16-bit counter
1. TIMx, is used as a general term to refer to a timer (for example, TIM1).
DS13866 Rev 4 69/92

77
Table 58. IWDG min/max timeout period at 32 kHz LSI clock(1)

Prescaler divider PR[2:0] bits Min timeout RL[11:0]= 0x000 Max timeout RL[11:0]= 0xFFF Unit
/4 0 0.125 512
/8 1 0.250 1024
/16 2 0.500 2048
/32 3 1.0 4096 ms
/64 4 2.0 8192
/128 5 4.0 16384
/256 6 or 7 8.0 32768
1. The exact timings further depend on the phase of the APB interface clock versus the LSI clock, which causes an
uncertainty of one RC period.
5.3.18 Characteristics of communication interfaces

I2C-bus interface characteristics
The I2C-bus interface meets timing requirements of the I2C-bus specification and user
manual rev. 03 for:
• Standard-mode (Sm): with a bit rate up to 100 kbit/s
• Fast-mode (Fm): with a bit rate up to 400 kbit/s
• Fast-mode Plus (Fm+): with a bit rate up to 1 Mbit/s.
The timings are specified by design as long as the I2C peripheral is properly configured
(refer to the reference manual RM0490) and when the I2CCLK frequency is greater than the
minimum shown in the following table.
Table 59. Minimum I2CCLK frequency
Symbol Parameter Condition Typ Unit
Standard-mode 2
Analog filter enabled
9
DNF = 0
Fast-mode
Minimum I2CCLK Analog filter disabled
frequency for correct 9
fI2CCLK(min) DNF = 1 MHz
operation of I2C
peripheral Analog filter enabled
19
DNF = 0
Fast-mode Plus
Analog filter disabled
16
DNF = 1
The SDA and SCL I/O requirements are met with the following restrictions: the SDA and
SCL I/O pins are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDDIO1 is disabled, but is still present. Only FT_f I/O pins
70/92 DS13866 Rev 4

support Fm+ low-level output current maximum requirement. Refer to Section 5.3.13: I/O
port characteristics for the I2C I/Os characteristics.
All I2C SDA and SCL I/Os embed an analog filter. Refer to the following table for its
characteristics:
Table 60. I2C analog filter characteristics(1)

Symbol Parameter Min Max Unit
Limiting duration of spikes suppressed

tAF 50 260 ns
by the filter(2)
2. Spikes shorter than the limiting duration are suppressed.
SPI/I2S characteristics
Unless otherwise specified, the parameters given in Table 61 for SPI are derived from tests
performed under the ambient temperature, fPCLKx frequency and supply voltage conditions
summarized in Table 23: General operating conditions. The additional general conditions
are:
• OSPEEDRy[1:0] set to 11 (output speed)
• capacitive load C = 30 pF
• measurement points at CMOS levels: 0.5 x VDD
Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI).
Table 61. SPI characteristics(1)

Master mode
24
2. V < VDD < 3.6 V
Master transmitter mode
24
2. V < VDD < 3.6 V
fSCK
SPI clock frequency Slave receiver mode - - 24 MHz
1/tc(SCK)
Slave transmitter mode/full duplex(2)
24
2.7 V < VDD < 3.6 V
Slave transmitter mode/full duplex(2)
22
2 V < VDD < 3.6 V
tsu(NSS) NSS setup time 4 * TPCLK - - ns
Slave mode
th(NSS) NSS hold time 2 * TPCLK - - ns
tw(SCKH) TPCLK TPCLK
SCK high and low time Master mode TPCLK ns
tw(SCKL) -1 +1
TPCLK TPCLK
- SCK low time Master mode TPCLK ns
-2 +2
tsu(MI) Master mode 4.5 - - ns
Data input setup time
tsu(SI) Slave mode 2 - - ns
DS13866 Rev 4 71/92

77
Table 61. SPI characteristics(1) (continued)

th(MI) Master mode 2 - - ns

Data input hold time
th(SI) Slave mode 3 - - ns
Data output access
ta(SO) Slave mode 9 - 34 ns
time
Data output disable
tdis(SO) Slave mode 9 - 16 ns
time
Slave mode
- 10 16
2.7 V < VDD < 3.6 V
tv(SO) ns
Data output valid time Slave mode
- 10 22
2 V < VDD < 3.6 V
tv(MO) Master mode - 3 5.5 ns
Slave mode
th(SO) 8 - - ns
Data output hold time 2 V < VDD < 3.6 V
th(MO) Master mode 1.5 - - ns
2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low
or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master
having tsu(MI) = 0 while Duty(SCK) = 50%
Figure 22. SPI timing diagram - slave mode and CPHA = 0
NSS input
tc(SCK) th(NSS)
tsu(NSS) tw(SCKH) tr(SCK)

CPHA=0
SCK input
CPOL=0
CPHA=0
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tf(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
th(SI)
tsu(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41658V1
72/92 DS13866 Rev 4

Figure 23. SPI timing diagram - slave mode and CPHA = 1
NSS input
tc(SCK)
tsu(NSS) tw(SCKH) tf(SCK) th(NSS)

CPHA=1
SCK input
CPOL=0
CPHA=1
CPOL=1
ta(SO) tw(SCKL) tv(SO) th(SO) tr(SCK) tdis(SO)
MISO output First bit OUT Next bits OUT Last bit OUT
tsu(SI) th(SI)
MOSI input First bit IN Next bits IN Last bit IN
MSv41659V1
1. Measurement points are done at 0.5 VDD and with external CL = 30 pF.
Figure 24. SPI timing diagram - master mode
High
NSS input
tc(SCK)
SCK Output
CPHA=0
CPOL=0
CPHA=0
CPOL=1
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tw(SCKH) tr(SCK)
tsu(MI) tw(SCKL) tf(SCK)
MISO
INPUT MSB IN BIT6 IN LSB IN
th(MI)
MOSI
OUTPUT MSB OUT BIT1 OUT LSB OUT
tv(MO) th(MO)
ai14136c
1. Measurement points are done at 0.5 VDD and with external CL = 30 pF.
DS13866 Rev 4 73/92

77
Table 62. I2S characteristics(1)

fMCK I2S main clock output - - 48 MHz
Master TX - 12
Master RX - 12
fCK I2S clock frequency MHz
Slave TX - 15
Slave RX - 48
tv(WS) WS valid time Master mode - 5
th(WS) WS hold time Master mode 2 -
tsu(WS) WS setup time Slave mode 3.5 -

ns
th(WS) WS hold time Slave mode 1 -
tsu(SD_MR) Master receiver 5 -
tsu(SD_SR) Slave receiver 2.5 -
th(SD_MR) Master receiver 1.5 -
Data input hold time
th(SD_SR) Slave receiver 1 -
tv(SD_ST) Slave transmitter (after enable edge) - 19,5

Data output valid time
tv(SD_MT) Master transmitter (after enable edge) - 5 ns
th(SD_ST) Slave transmitter (after enable edge) 8 -

Data output hold time
th(SD_MT) Master transmitter (after enable edge) 2.5 -
Figure 25. I2S slave timing diagram (Philips protocol)
tc(CK)
CPOL = 0
CK Input
CPOL = 1
tw(CKH) tw(CKL) th(WS)
WS input
tsu(WS) tv(SD_ST) th(SD_ST)
SDtransmit LSB transmit(2) MSB transmit Bitn transmit
tsu(SD_SR) th(SD_SR)
SDreceive LSB receive(2) MSB receive Bitn receive LSB receive
MSv39721V1
74/92 DS13866 Rev 4

1. Measurement points are done at CMOS levels: 0.3 VDDIO1 and 0.7 VDDIO1.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 26. I2S master timing diagram (Philips protocol)
90%
10%
tf(CK) tr(CK)
tc(CK)
CK output
CPOL = 0
tw(CKH)
CPOL = 1
tv(WS) tw(CKL) th(WS)
WS output
tv(SD_MT) th(SD_MT)
SDtransmit LSB transmit(2) MSB transmit Bitn transmit LSB transmit
tsu(SD_MR) th(SD_MR)
SDreceive LSB receive(2) MSB receive Bitn receive LSB receive
MSv39720V1

2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
USART (SPI mode) characteristics

Unless otherwise specified, the parameters given in Table 63 for USART are derived from
tests performed under the ambient temperature, fPCLKx frequency and supply voltage
conditions summarized in Table 23: General operating conditions. The additional general
conditions are:
• OSPEEDRy[1:0] set to 10 (output speed)
• capacitive load C = 30 pF
• measurement points at CMOS levels: 0.5 x VDD
Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, CK, TX, and RX for USART).
DS13866 Rev 4 75/92

77
Table 63. USART (SPI mode) characteristics

Master mode - - 6.0

fCK USART clock frequency Slave receiver mode - - 16.0 MHz
Slave transmitter - - 16.0
tsu(NSS) NSS setup time Slave mode Tker(1) + 1 - -
th(NSS) NSS hold time Slave mode 2 - -
tw(CKH) CK high time 1 / fCK / 2 1 / fCK / 2
Master mode 1 / fCK / 2
tw(CKL) CK low time -1 +1
tsu(MI) Master mode 16 - -

tsu(SI) Slave mode 1.5 - -
th(MI) Master mode 0 - -
Data input hold time ns
th(SI) Slave mode 0 - -
Slave mode
- 12.0 19
2.7 V < VDD < 3.6 V
tv(SO)
Data output valid time Slave mode
- 12.0 13
2.0 V < VDD < 3.6 V
tv(MO) Master mode - 2.0 4
th(SO) Slave mode 9.5 - -
Data output hold time
th(SO) Master mode 0.5 - -
1. Tker is the usart_ker_ck_pres clock period
Figure 27. USART timing diagram in SPI master mode

1/fCK
tw(CKH)
CPHA=0
CK output
CPOL=0
CPHA=0
CPOL=1
tw(CKL)
CPHA=1
CK output
CPOL=0
CPHA=1
CPOL=1
tsu(RX) th(RX)
RX input MSB IN BIT6 IN LSB IN
TX output MSB OUT BIT1 OUT LSB OUT
tv(TX) th(TX) MSv65386V6
76/92 DS13866 Rev 4

Figure 28. USART timing diagram in SPI slave mode

NSS input
1/fCK th(NSS)
tsu(NSS) tw(CKH)
CPHA=0
CPOL=0
CK input
CPHA=0
CPOL=1
tw(CKL) tv(TX) th(TX)
TX output First bit OUT Next bits OUT Last bit OUT
tsu(RX) th(RX)
RX input First bit IN Next bits IN Last bit IN
MSv65387V6
DS13866 Rev 4 77/92

77
Package information STM32C011x4/x6
6 Package information
In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
6.1 Device marking

Refer to technical note “Reference device marking schematics for STM32 microcontrollers
and microprocessors” (TN1433) available on www.st.com, for the location of pin 1 / ball A1
as well as the location and orientation of the marking areas versus pin 1 / ball A1.
Parts marked as “ES”, “E” or accompanied by an engineering sample notification letter, are
not yet qualified and therefore not approved for use in production. ST is not responsible for
any consequences resulting from such use. In no event will ST be liable for the customer
using any of these engineering samples in production. ST’s Quality department must be
contacted prior to any decision to use these engineering samples to run a qualification
activity.
A WLCSP simplified marking example (if any) is provided in the corresponding package
information subsection.
6.2 SO8N package information (O7)

This SO8N is an 8-lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package.
Figure 29. SO8N -Outline
K[Û
A2 A B
c
B
b ccc
e
0.25 mm
D SEATING GAUGE PLANE
PLANE
C k
8
E1 E
1 L
A1
L1
O7_SO8_ME_V3
1. Drawing is not to scale.
Table 64. SO8N -Mechanical data

millimeters inches(1)
Symbol
Min. Typ. Max. Min. Typ. Max.
A - - 1.750 - - 0.0689
A1 0.100 - 0.250 0.0039 - 0.0098
78/92 DS13866 Rev 4

STM32C011x4/x6 Package information
Table 64. SO8N -Mechanical data (continued)

Symbol
A2 1.250 - - 0.0492 - -
b 0.280 - 0.480 0.0110 - 0.0189
c 0.100 - 0.230 0.0039 - 0.0091
(2)
D 4.800 4.900 5.000 0.1890 0.1929 0.1969
E 5.800 6.000 6.200 0.2283 0.2362 0.2441
E1(3) 3.800 3.900 4.000 0.1496 0.1535 0.1575
e - 1.270 - - 0.0500 -
h 0.250 - 0.500 0.0098 - 0.0197
k 0° - 8° 0° - 8°
L 0.400 - 1.270 0.0157 - 0.0500
L1 - 1.040 - - 0.0409 -
ccc - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side
3. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25 mm per side.
Note: The package top may be smaller than the package bottom. Dimensions D and E1 are
determinated at the outermost extremes of the plastic body exclusive of mold flash, tie bar
burrs, gate burrs and interleads flash, but including any mismatch between the top and
bottom of plastic body. Measurement side for mold flash, protusions or gate burrs is bottom
side.
DS13866 Rev 4 79/92

87
Figure 30. SO8N - Footprint example
0.6 (x8)
3.9
6.7
1.27
O7_FP_V1
1. Dimensions are expressed in millimeters.
80/92 DS13866 Rev 4

6.3 WLCSP12 package information (B0EK)

This WLCSP is a 12-ball, 1.70 x 1.42 mm, 0.35 mm pitch, wafer level chip scale package
Figure 31. WLCSP12 – Outline

(DETAIL A)
G F
e1 e
(DETAIL B)
A4 A2
B3 B1 e
C4 C2
e2 D3 D1 DETAIL B
E4 E2
F3 F1
BACKSIDE COATING
BOTTOM VIEW
A
bbb Z
A3 A2
SIDE VIEW SIDE VIEW
D
B
A
BUMP
E
B1 Orientation ref A1
4x
aaa
eee Z
TOP VIEW
Z
b (Nx)
ccc Z X Y
ddd Z
SEATING
PLANE
DETAIL A
ROATATED 90
B0EK_WLCSP12_ME_V1

2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
3. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
4. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of
the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc
perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The
axis perpendicular to datum Z of each ball must lie within this tolerance zone.
DS13866 Rev 4 81/92

87
Table 65. WLCSP12 – Mechanical data

Symbol
Min Typ Max Min Typ Max
A(2) - - 0.49 - - 0.0193

A1 - 0.17 - - 0.0067 -
A2 - 0.29 - - 0.0114 -
(3)
A3 - 0.025 - - 0.0098 -
(4)
Øb 0.21 0.24 0.27 0.0083 0.0094 0.0106
D 1.68 1.70 1.72 0.0661 0.0669 0.0677
E 1.41 1.42 1.43 0.0555 0.0559 0.0563
e - 0.35 - - 0.0138 -
e1 - 0.909 - - 0.0358 -
e2 - 0.875 - - 0.0344 -
F(5) - 0.409 - - 0.0161 -
G(5) - 0.282 - - 0.0111 -
N 12
aaa - - 0.10 - - 0.0039
bbb - - 0.10 - - 0.0039
ccc(6) - - 0.10 - - 0.0039
ddd(7) - - 0.05 - - 0.0020
eee - - 0.05 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. The maximum total package height is calculated by the RSS method (Root Sum Square) using nominal
and tolerances values of A1 and A2.
3. Back side coating. Nominal dimension is rounded to the 3rd decimal place resulting from process
capability.
4. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
5. Calculated dimensions are rounded to the 3rd decimal place
6. Bump position designation per JESD 95-1, SPP-010. The tolerance of position that controls the location of
the pattern of balls with respect to datums X and Y. For each ball there is a cylindrical tolerance zone ccc
perpendicular to datum Z and located on true position with respect to datums X and Y as defined by e. The
axis perpendicular to datum Z of each ball must lie within this tolerance zone.
7. The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball there is a cylindrical tolerance zone ddd perpendicular to datum Z and located on true
position as defined by e. The axis perpendicular to datum Z of each ball must lie within this tolerance zone.
Each tolerance zone ddd in the array is contained entirely in the respective zone ccc above. The axis of
each ball must lie simultaneously in both tolerance zones
82/92 DS13866 Rev 4

Figure 32. WLCSP12 – Footprint example
Dpad
Dsm
BGA_WLCSP_FT_V1
Table 66. WLCSP12 - Example of PCB design rules

Dimension Recommended values
Pitch 0.35 mm
Dpad 0.200 mm
Dsm 0.275 mm
Stencil thickness 0.08 mm
Marking example
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
The printed markings may differ depending on the supply chain.
Other optional marking or inset/upset marks that identify the parts throughout supply chain
operations, are not indicated below.
DS13866 Rev 4 83/92

87
Figure 33. WLCSP12 package marking example
Product identification(1)
Pin 1 identifier
Y WW
Date code
MS55865V2
6.4 TSSOP20 package information (YA)

TSSOP20 is a 20-lead, 6.5 x 4.4 mm thin small-outline package with 0.65 mm pitch.
Figure 34. TSSOP20 – Outline
20 11
c
E1 E
SEATING 0.25 mm
PLANE GAUGE PLANE
C
1 10
PIN 1
IDENTIFICATION
k
aaa C A1 L
A A2
L1
b e
YA_ME_V3
Table 67. TSSOP20 – Mechanical data

Symbol
A - - 1.200 - - 0.0472
A1 0.050 - 0.150 0.0020 - 0.0059
A2 0.800 1.000 1.050 0.0315 0.0394 0.0413
b 0.190 - 0.300 0.0075 - 0.0118
84/92 DS13866 Rev 4

Table 67. TSSOP20 – Mechanical data (continued)

Symbol
c 0.090 - 0.200 0.0035 - 0.0079

D(2) 6.400 6.500 6.600 0.2520 0.2559 0.2598
E 6.200 6.400 6.600 0.2441 0.2520 0.2598
(3)
E1 4.300 4.400 4.500 0.1693 0.1732 0.1772
e - 0.650 - - 0.0256 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0° - 8° 0° - 8°
aaa - - 0.100 - - 0.0039
1. Values in inches are converted from mm and rounded to four decimal digits.
2. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15 mm per side.
3. Dimension “E1” does not include interlead flash or protrusions. Interlead flash or protrusions shall not
exceed 0.25 mm per side.
Figure 35. TSSOP20 – Footprint example

0.25
6.25
20 11
1.35
0.25
7.10 4.40
1.35
1 10
0.40 0.65 YA_FP_V1
DS13866 Rev 4 85/92

87
6.5 UFQFPN20 package information (A0A5)

UFQFPN20 is a 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra-thin fine-pitch quad flat package.
Figure 36. UFQFPN20 – Outline
Pin 1 E
TOP VIEW
L1
D
ddd
L3 D1
e 10 L2 A3
5
e
b
E1 E
1
15
20 16
L5 A1
A
BOTTOM VIEW SIDE VIEW

A0A5_ME_V4
86/92 DS13866 Rev 4

Table 68. UFQFPN20 – Mechanical data

Symbol
Min Typ Max Min Typ Max
A 0.500 0.550 0.600 0.0197 0.0217 0.0236

A1 0.000 0.020 0.050 0.0000 0.0008 0.0020
A3 - 0.152 - - 0.060 -
D 2.900 3.000 3.100 0.1142 0.1181 0.1220
D1 - 2.000 - - 0.0790 -
E 2.900 3.000 3.100 0.1142 0.1181 0.1220
E1 - 2.000 - - 0.0790 -
L1 0.500 0.550 0.600 0.0197 0.0217 0.0236
L2 0.300 0.350 0.400 0.0118 0.0138 0.0157
L3 - 0.200 - - 0.0079 -
L5 - 0.150 - - 0.0059 -
b 0.180 0.250 0.300 0.0071 0.0098 0.0118
e - 0.500 - - 0.0197 -
ddd - - 0.050 - - 0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 37. UFQFPN20 – Footprint example
A0A5_FP_V2
DS13866 Rev 4 87/92

87
STM32C011x4/x6
6.6 Thermal characteristics

The operating junction temperature TJ must never exceed the maximum given in Table 23:
General operating conditions.
The maximum junction temperature in °C that the device can reach if respecting the
operating conditions, is:
TJ(max) = TA(max) + PD(max) x ΘJA
where:
• TA(max) is the maximum operating ambient temperature in °C,
• ΘJA is the package junction-to-ambient thermal resistance, in °C/W,
• PD = PINT + PI/O,
– PINT is power dissipation contribution from product of IDD and VDD
– PI/O is power dissipation contribution from output ports where
PI/O = Σ (VOL × IOL) + Σ ((VDDIO1 – VOH) × IOH), taking into account the actual VOL
/ IOL and VOH / IOH of the I/Os at low and high level in the application.
Table 69. Thermal characteristics

Symbol Parameter Package(1) Value Unit
UFQFPN20 76.4
Thermal resistance TSSOP20 88.7

ΘJA °C/W
junction-ambient WLCSP12 148
SO8N 100
UFQFPN20 30

ΘJB °C/W
junction-board WLCSP12 116.3
SO8N 56
UFQFPN20 31

ΘJC °C/W
junction-case WLCSP12 10.6
SO8N 46
1. Refer to Section 6: Package information for package dimensions
6.6.1 Reference documents

[1] Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection
(Still Air) (JESD51-2A), JEDEC, January 2008. Available from www.jedec.org.
88/92 DS13866 Rev 4

STM32C011x4/x6 Ordering information
7 Ordering information
Example STM32 C 011 F 6 P 6 xyy
Device family
STM32 = Arm® based 32-bit microcontroller
Product type
C = general-purpose
Device subfamily
011 = STM32C011
Pin count
J=8
D = 12
F = 20
Flash memory size

4 = 16 Kbytes
6 = 32 Kbytes
Package type
U = UFQFPN
Y = WLCSP
P = TSSOP
M = SO˽N
Temperature range
6 = -40 to 85°C (105°C junction)
7 = -40 to 105°C (125°C junction)
3 = -40 to 125°C (130°C junction)
Options
TR = tape and reel packing
= tray packing
other = 3-character ID incl. custom flash memory code and packing information
For a list of available options (memory, package, and so on) or for further information on any
aspect of this device, contact your nearest ST sales office.
DS13866 Rev 4 89/92

89
Important security notice STM32C011x4/x6
8 Important security notice
The STMicroelectronics group of companies (ST) places a high value on product security,
which is why the ST product(s) identified in this documentation may be certified by various
security certification bodies and/or may implement our own security measures as set forth
herein. However, no level of security certification and/or built-in security measures can
guarantee that ST products are resistant to all forms of attacks. As such, it is the
responsibility of each of ST's customers to determine if the level of security provided in an
ST product meets the customer needs both in relation to the ST product alone, as well as
when combined with other components and/or software for the customer end product or
application. In particular, take note that:
• ST products may have been certified by one or more security certification bodies, such
as Platform Security Architecture (www.psacertified.org) and/or Security Evaluation
standard for IoT Platforms (www.trustcb.com). For details concerning whether the ST
product(s) referenced herein have received security certification along with the level
and current status of such certification, either visit the relevant certification standards
website or go to the relevant product page on www.st.com for the most up to date
information. As the status and/or level of security certification for an ST product can
change from time to time, customers should re-check security certification status/level
as needed. If an ST product is not shown to be certified under a particular security
standard, customers should not assume it is certified.
• Certification bodies have the right to evaluate, grant and revoke security certification in
relation to ST products. These certification bodies are therefore independently
responsible for granting or revoking security certification for an ST product, and ST
does not take any responsibility for mistakes, evaluations, assessments, testing, or
other activity carried out by the certification body with respect to any ST product.
• Industry-based cryptographic algorithms (such as AES, DES, or MD5) and other open
standard technologies which may be used in conjunction with an ST product are based
on standards which were not developed by ST. ST does not take responsibility for any
flaws in such cryptographic algorithms or open technologies or for any methods which
have been or may be developed to bypass, decrypt or crack such algorithms or
technologies.
• While robust security testing may be done, no level of certification can absolutely
guarantee protections against all attacks, including, for example, against advanced
attacks which have not been tested for, against new or unidentified forms of attack, or
against any form of attack when using an ST product outside of its specification or
intended use, or in conjunction with other components or software which are used by
customer to create their end product or application. ST is not responsible for resistance
against such attacks. As such, regardless of the incorporated security features and/or
any information or support that may be provided by ST, each customer is solely
responsible for determining if the level of attacks tested for meets their needs, both in
relation to the ST product alone and when incorporated into a customer end product or
application.
• All security features of ST products (inclusive of any hardware, software,
documentation, and the like), including but not limited to any enhanced security
features added by ST, are provided on an "AS IS" BASIS. AS SUCH, TO THE EXTENT
PERMITTED BY APPLICABLE LAW, ST DISCLAIMS ALL WARRANTIES, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, unless the
applicable written and signed contract terms specifically provide otherwise.
90/92 DS13866 Rev 4

STM32C011x4/x6 Revision history
9 Revision history
Table 70. Document revision history

Date Revision Changes
30-Mar-2022 1 Initial release

14-Sep-2022 2 Fixed typo errors.
Updated:
– Table 2, Table 20, Table 27, Table 28, Table 29, Table 30,
9-Dec-2022 3 Table 36, Table 40, Table 55
– Figure 4, Figure 9, Figure 20, Figure 21
– title of Figure 3 and Figure 4
Updated:
– Cover page
– Section Features, Section 1: Introduction (added reference to
reference manual and errata sheet), Section 3.5: Boot modes,
Section 3.7.1: Power supply schemes, Section 3.9: Clocks and
startup, Section 3.15.1: Advanced-control timer (TIM1)
Section 3.18: Universal synchronous/asynchronous receiver
transmitter (USART), Section 5.2: Absolute maximum ratings,
Section : USART (SPI mode) characteristics, Section 5.3.6: Wake-
15-Jan-2024 4 up time from low-power modes, section I/O system current
consumption, section General input/output characteristics, section
USART (SPI mode) characteristics, Section 5.3.17: Timer
characteristics, and Section 6: Package information
– Table 7, Table 12, Table 20, Table 27, Table 44, Table 45,
Table 50, Table 56, Table 63,
– Figure 1, Figure 2, Figure 18, Figure 21, Figure 22, Figure 23
Added:
– Section 6.6: Thermal characteristics
– Figure 27 and Figure 28
DS13866 Rev 4 91/92

91
STM32C011x4/x6
IMPORTANT NOTICE – READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgment.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. For additional information about ST trademarks, refer to www.st.com/trademarks. All other product
or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2024 STMicroelectronics – All rights reserved
92/92 DS13866 Rev 4

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STM32C011x4/x6

Arm®Cortex®-M0+ 32-bit MCU, 32 KB flash, 6 KB RAM,

January 2024 DS13866 Rev 4 1/92

2/92 DS13866 Rev 4

3.15.5 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

4 Pinouts, pin description and alternate functions . . . . . . . . . . . . . . . . . 26

DS13866 Rev 4 3/92

5.3.16 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

8 Important security notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4/92 DS13866 Rev 4

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

DS13866 Rev 4 5/92

Table 49. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

6/92 DS13866 Rev 4

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

DS13866 Rev 4 7/92

This document provides information on STM32C011x4/x6 microcontrollers, such as

8/92 DS13866 Rev 4

The STM32C011x4/x6 mainstream microcontrollers are based on high-performance

Table 2. STM32C011x4/x6 family device features and peripheral counts

Package SO8N WLCSP12 UFQFPN20

Bootloader USART1, I2C1

DS13866 Rev 4 9/92

Figure 1. Block diagram

GPIOs LSI RC 32 kHz XTAL OSC

PB[7,6] Port B IWDG

PC[15,14] Port C RCC LSE LSE OSCX_IN

System and RTC_OUT

from peripherals AHB-to-APB

13x IN ADC I/F 4 channels

TIM3 4 ch., ETR as AF

MISO/MCK TIM14 1 channel as AF

RX, TX, CTS, RTS

I2C1 SCL, SDA, SMBA,

Power domain of analog blocks : VDD VDDA VDDIO1

10/92 DS13866 Rev 4

3.1 Arm® Cortex®-M0+ core with MPU

3.2 Memory protection unit

3.3 Embedded flash memory

DS13866 Rev 4 11/92

Flexible protections can be configured thanks to option bytes:

User execution Debug, boot from RAM or boot

Main 1 Yes Yes Yes No No No

3.4 Embedded SRAM

3.5 Boot modes

12/92 DS13866 Rev 4

3.6 Cyclic redundancy check calculation unit (CRC)

3.7 Power supply management

3.7.1 Power supply schemes

DS13866 Rev 4 13/92

Figure 2. Power supply overview

Reset block VDD domain

3.7.2 Power supply supervisor

3.7.3 Voltage regulator

3.7.4 Low-power modes

14/92 DS13866 Rev 4

3.7.5 Reset mode

3.8 Interconnect of peripherals

DS13866 Rev 4 15/92