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Interfacimg Programs-1

The document describes several Verilog code examples including a binary up/down counter, BCD counter, interfacing a stepper motor and DC motor to FPGA, designing a ripple carry counter and 4-bit ripple carry adder. Test benches are provided to test the code and expected and output waveforms are displayed.

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swastik nayak
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35 views10 pages

Interfacimg Programs-1

The document describes several Verilog code examples including a binary up/down counter, BCD counter, interfacing a stepper motor and DC motor to FPGA, designing a ripple carry counter and 4-bit ripple carry adder. Test benches are provided to test the code and expected and output waveforms are displayed.

Uploaded by

swastik nayak
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© © All Rights Reserved
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Program 8: BINARY UP/DOWN COUNTER:

module upordown_counter(
Clk,
reset,
UpOrDown,
Count
);
input Clk, reset, UpOrDown;

output [3 : 0] Count;

reg [3 : 0] Count = 0;

always @(posedge(Clk) or posedge(reset))


begin
if(reset == 1)
Count <= 0;
else
if(UpOrDown == 1) //Up mode selected
if(Count == 15)
Count <= 0;
else
Count <= Count + 1; //Incremend Counter
else //Down mode selected
if(Count == 0)
Count <= 15;
else
Count <= Count - 1; //Decrement counter
end

endmodule

BDC DOUNTER:

Design Block/Design Code

module bcd_counter(clk, rst, bcd_out);

input clk, rst;

output [3:0] bcd_out;

reg [3:0] temp;

assign bcd_out=temp;

always@(posedge clk)

begin if(rst)

begin temp<=4'b0000;
end

else

begin

temp<=temp+1'b1;

if(temp==4'b1001)

temp<=4'b0000;

end

end

endmodule

DEMONSTRATION EXPERIMENTS:

Aim: Design Verilog code to Interface a Stepper motor to FPGA .


module STP_mtr(clk, dir, d_out);
input clk;
input [1:0] dir;
output reg [3:0] d_out;
reg [30:0] clk_div = 31'd0;
reg [7:0] count=8'h0;
reg [3:0] shift_reg = 4'b1001;
reg [1:0] state = 2'b00;
always@(posedge clk)
begin
clk_div = clk_div + 1;
end
always@(posedge clk_div[16])
begin
if(dir == 2'b10 && state == 2'b00)
begin
shift_reg = {shift_reg[0], shift_reg[3:1]};// clock wise
count = count + 1;
if (count == 8'd200)
begin
state = state+1;
count = 8'd0;
end
end
else if(dir == 2'b01 && state == 2'b01)
begin
shift_reg = {shift_reg[2:0], shift_reg[3]}; // anti clock
count = count + 1;
if (count == 8'd200)
begin
state = state+1;
count = 8'd0;
end
end
else
begin
shift_reg = shift_reg;
if (state==2'b10)
state =2'b00;
end
d_out = shift_reg;
end
endmodule

UCF FILE
NET "clk" LOC = p56;
NET "dir[0]" LOC = p124;
NET "dir[1]" LOC= p123;
NET "d_out[0]" LOC = p29;
NET "d_out[1]" LOC = p30;
NET "d_out[2]" LOC = p32;
NET "d_out[3]" LOC = p33;
Result: A Stepper Motor is interfaced to the FPGA Kit and the changes in speed and direction is
observed accordingly.

LED BLINKING:
module blink_LED (
input clk, // Clock input
output reg led // Output for the LED
);

reg [24:0] counter; // 25-bit counter for timing

always @(posedge clk) begin


if (counter == 25000000) begin // Adjust this value for desired blink frequency
led <= ~led; // Toggle the LED
counter <= 0; // Reset the counter
end else begin
counter <= counter + 1; // Increment the counter
end
end

endmodule
UCF:
NET "led" LOC = P98;
NET "clk" LOC = P56;
ADDITIONAL PROGRAMS:
Aim: Interface a DC motor to FPGA and write Verilog code to change its speed and direction.
Design Code:
module DC_MOTOR(clk,dir,speed,P_DCMEN,P_DCM);
input clk,dir;
input [1:0]speed;
output reg P_DCMEN;
output reg [1:0] P_DCM ;
reg [32:0] clk_div = 33'd0;
always@(posedge clk)
clk_div = clk_div + 1;
always@(clk_div)
begin
if (speed == 2'b00) P_DCMEN = clk_div[2];
if (speed == 2'b01) P_DCMEN = clk_div[4];
if (speed == 2'b10) P_DCMEN = clk_div[8];
if (speed == 2'b11) P_DCMEN = clk_div[16];
end
always@(clk_div)
begin
if (dir == 0)
P_DCM = 2'b01;
else
P_DCM = 2'b10;
end
endmodule

UCF:
NET "P_DCM[0]" LOC = P82;
NET "P_DCM[1]" LOC = P83;
NET "P_DCMEN" LOC = P84;
NET "dir" LOC = P121 ;
NET "speed(0)" LOC = P123;
NET "speed(1)" LOC =P124;
NET "clk" LOC = P56;

Result: A DC Motor is interfaced to the FPGA Kit and the changes in speed and direction is observed
accordingly.

ADDITIONAL EXPERIMENTS:

1)Design Ripple carry counter


Design code:
module cntr(q,clk,reset);
output [3:0]q;
input clk, reset;
T_FF tff0(q[0],clk,reset);
T_FF tff1(q[1],q[0],reset);
T_FF tff2(q[2],q[1],reset);
T_FF tff3(q[3],q[2],reset);
endmodule
module T_FF(q,clk,reset);
input clk, reset;
output q;
wire d;
D_FF dff0(q,d,clk,reset);
not n1(d,q);
endmodule

module D_FF(q,d,clk,reset);
output q;
input clk,reset,d;
reg q;
always@(posedge reset or negedge clk)
begin
if(reset)
q =1'b0;
else
q =d;
end
endmodule
TEST BENCH CODE:
module tb;
// Inputs
reg clk;
reg reset;
// Outputs
wire [3:0] q;
// Instantiate the Unit Under Test (UUT)
cnrt uut (.clk(clk), .reset(reset), .q(q));
initial begin
// Initialize Inputs
clk = 1'b1;
forever #5 clk =~clk;
end
initial
begin
reset = 1'b1;
#15 reset = 1'b0;
#180 reset = 1'b1;
#10 reset = 1'b0;
end
endmodule
EXPECTED WAVEFORM:

OUTPUT WAVEFORM

2) DESIGN 4 BIT RIPPLE CARRY ADDER:


module fulladder(a,b,c_in,sum,c_out);
input[3:0]a,b;
input c_in;
output[3:0]sum;
output c_out;
wire c1,c2,c3;
fulladd fa0(a[0],b[0],c_in,sum[0],c1);
fulladd fa1(a[1],b[1],c1,sum[1],c2);
fulladd fa2(a[2],b[2],c2,sum[2],c3);
fulladd fa3(a[3],b[3],c3,sum[3],c_out);
endmodule
module fulladd(a,b,c_in,sum,c_out);
input a,b,c_in;
output sum,c_out;
wire s1,c1,s2;
xor (s1,a,b);
and (c1,a,b);
xor (sum,s1,c_in);
and (s2,s1,c_in);
xor (c_out,s2,c1);
endmodule
module stimulus;
reg [3:0] a;
reg [3:0] b;
reg c_in;
wire [3:0] sum;
wire c_out;
fulladder uut (
.a(a),
.b(b),
.c_in(c_in),
.sum(sum),
.c_out(c_out)
);
initial begin
// Initialize Inputs
a=4'd0;b=4'd0;c_in=1'b0;
#5 a=4'd3; b=4'd4;
#5 a=4'd2; b=4'd5;
#5 a=4'd9; b=4'd9;
#5 a=4'd10; b=4'd15;
#5 a=4'd10; b=4'd5; c_in=1'b1;
end
endmodule
Expected Waveform:

Output Waveform:

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