School of Electronics Engineering (SENSE)

B. Tech – Electronics & Computer Engineering

BECE406E - FPGA BASED SYSTEM DESIGN

LAB RECORD
(L33+L34)

Submitted By
21BLC1374 – Pranav Pratap Patil

Submitted To
Dr. Sahthivel S M
DATE: 23/09/2024
[21BLC1374] Lab 8 – Serial Adder & Vending Machine 23/09/2024

Slot: L33+L34

LAB - 8
Serial Adder & Vending Machine
AIM: To Design and implement a 4-bit Serial Adder using a full adder and PISO registers to
perform the addition of 4-bit numbers and verify its functionality using ModelSim. Design and
Implement a Candy Vending Machine that dispenses candy if 15 cents received and dispenses
refund if more that 15 cents received and Implement in DE2-115 Kit.

Software Required: Quartus Prime, ModelSim

Hardware Required: Altera Cyclone IV E DE2-115 Kit, USB Cable, Power Supply

Procedure:
1. Start Quartus Prime Lite Edition.
2. Go To : File → New Project Wizard.
3. Set The Working Directory and Name of the Project and Create an Empty Project.
4. Set Family to “Cyclone IV E”, Package to “FBGA”, Pin Count to “780” , Core Speed
Grade to “7” and Set Device as “EP4CE115F29C7”.
5. Set Simulation Tool to “ModelSim” and Format to “Verilog HDL”.
6. Verify all details in Summary are Acurate then click Finish.
7. Go To : File → New → “Verilog HDL File”, To create a New File.
8. Code the Apropriate Verilog Program in the File and Save It.
9. Once Done, Go To : Processing → Start Compilation, To compile the Verilog Code.
10. To Perform RTL Simulation Go To : Tools → Run Simulation Tool → RTL Simulation.
11. Perform The Necessary Simulations in ModelSim and Verify The Output.
12. Once Code Is Verified Close ModelSim, Go To : Assignments → Pin Planner.
13. Assign Necessary Input Output Pins and Recompile using Step 9.
14. To Flash The Code in the Kit, Connect the Power Supply to the Kit and Connect the
Provided USB Cable.
15. Go To : Tools → Programmer, Select USB-Blaster, and Click Start.
16. On Succesful Flashing Verify The Output

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[21BLC1374] Lab 8 – Serial Adder & Vending Machine 23/09/2024

4-Bit Serial Adder using PISO registers:

Code:
module full_adder (
input wire a,
input wire b,
input wire cin,
output wire sum,
output wire cout
);
assign {cout, sum} = a + b + cin;
endmodule

module PISO (
input wire clk,
input wire load,
input wire [3:0] parallel_in,
output reg serial_out
);
reg [3:0] shift_reg;

always @(posedge clk) begin

if (load)
shift_reg <= parallel_in; // Load parallel data
else
shift_reg <= shift_reg >> 1; // Shift right for serial output
end

always @(shift_reg) begin

serial_out = shift_reg[0]; // LSB as serial output
end
endmodule

module serial_adder (
input wire clk,
input wire load,
input wire [3:0] A, // First 4-bit input
input wire [3:0] B, // Second 4-bit input
output wire [3:0] sum, // Final 4-bit sum
output wire carry_out // Carry out
);
wire serial_a, serial_b, serial_sum, carry;
reg carry_reg;

// Instantiate PISO registers for A and B

PISO A_shift_reg (.clk(clk), .load(load), .parallel_in(A),
.serial_out(serial_a));
PISO B_shift_reg (.clk(clk), .load(load), .parallel_in(B),
.serial_out(serial_b));

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[21BLC1374] Lab 8 – Serial Adder & Vending Machine 23/09/2024

// Instantiate full adder

full_adder FA (.a(serial_a), .b(serial_b), .cin(carry_reg),
.sum(serial_sum), .cout(carry));

reg [3:0] sum_reg;

always @(posedge clk) begin

if (load) begin
carry_reg <= 0; // Clear carry when loading
sum_reg <= 0; // Clear sum
end else begin
sum_reg <= {serial_sum, sum_reg[3:1]}; // Shift sum
carry_reg <= carry; // Update carry
end
end

assign sum = sum_reg; // Final 4-bit sum

assign carry_out = carry_reg; // Final carry out
endmodule

module tb_serial_adder;
reg clk;
reg load;
reg [3:0] A;
reg [3:0] B;
wire [3:0] sum;
wire carry_out;

// Instantiate the serial adder

serial_adder UUT (
.clk(clk),
.load(load),
.A(A),
.B(B),
.sum(sum),
.carry_out(carry_out)
);

// Clock generation (period = 10 units of time)

always #5 clk = ~clk;

// Initialize signals and apply test cases

initial begin
// Test Case 1: A = 13 (1101), B = 10 (1010)
clk = 0;
load = 1;
A = 4'b1101; // A = 13

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[21BLC1374] Lab 8 – Serial Adder & Vending Machine 23/09/2024

B = 4'b1010; // B = 10
#10 load = 0; // Start serial addition
#50; // Wait for 4 clock cycles to observe the result
$display("Test Case 1: A = %b, B = %b | Sum = %b, Carry = %b", A, B,
sum, carry_out);

// Test Case 2: A = 7 (0111), B = 8 (1000)

load = 1;
A = 4'b0111; // A = 7
B = 4'b1000; // B = 8
#10 load = 0;
#50;
$display("Test Case 2: A = %b, B = %b | Sum = %b, Carry = %b", A, B,
sum, carry_out);

// Test Case 3: A = 15 (1111), B = 15 (1111)

load = 1;
A = 4'b1111; // A = 15
B = 4'b1111; // B = 15
#10 load = 0;
#50;
$display("Test Case 3: A = %b, B = %b | Sum = %b, Carry = %b", A, B,
sum, carry_out);

// Test Case 4: A = 5 (0101), B = 3 (0011)

load = 1;
A = 4'b0101; // A = 5
B = 4'b0011; // B = 3
#10 load = 0;
#50;
$display("Test Case 4: A = %b, B = %b | Sum = %b, Carry = %b", A, B,
sum, carry_out);

// Test Case 5: A = 0 (0000), B = 0 (0000)

load = 1;
A = 4'b0000; // A = 0
B = 4'b0000; // B = 0
#10 load = 0;
#50;
$display("Test Case 5: A = %b, B = %b | Sum = %b, Carry = %b", A, B,
sum, carry_out);

// Test Case 6: A = 15 (1111), B = 15 (1111)

load = 1;
A = 4'b1111; // A = 0
B = 4'b1111; // B = 0
#10 load = 0;
#50;

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[21BLC1374] Lab 8 – Serial Adder & Vending Machine 23/09/2024

$display("Test Case 6: A = %b, B = %b | Sum = %b, Carry = %b", A, B,

sum, carry_out);

// Finish the simulation

$finish;
end
endmodule

Output:

Vending Machine:
Code:
module vendingMachineFPGA(
input Nick, Dim, Clock, Reset,
output Can, Ref,
output [6:0] HEX0,
output [6:0] HEX1
);
wire Slow_Clk_Out;
wire [2:0] State;

clkdivider mut (.clk(Clock), .rst(Reset), .slowclk(Slow_Clk_Out));

vendingMachineFunc uut (.N(Nick), .D(Dim), .clk(Slow_Clk_Out),
.rst(Reset), .candy(Can), .refund(Ref), .Y(State));
bcd_to_7segment bcd_decoder (.bcd(State), .seg0(HEX0), .seg1(HEX1));
endmodule

module vendingMachineFunc(
input wire N, // Nickel input
input wire D, // Dime input
input wire clk, // Clock input
input wire rst, // Reset input
output reg candy, // Candy dispense output
output reg refund, // Refund output
output reg [2:0] Y
);

// Define state encoding using parameters

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[21BLC1374] Lab 8 – Serial Adder & Vending Machine 23/09/2024

parameter S0 = 3'b000; // 0 cents (initial state)

parameter S5 = 3'b001; // 5 cents
parameter S10 = 3'b010; // 10 cents
parameter S15 = 3'b011; // 15 cents (dispense candy)
parameter S20 = 3'b100; // 20 cents (refund nickel and go to S15)

reg [2:0] current_state, next_state;

// Sequential block for state transitions

always @(posedge clk or posedge rst) begin
if (rst)
current_state <= S0; // Reset to start state
else
current_state <= next_state; // Move to next state
Y = current_state;
end

// Combinational block for next state logic and outputs

always @(*) begin
// Next state logic
next_state = (current_state == S0) ? (N ? S5 : (D ? S10 : S0)) :
(current_state == S5) ? (N ? S10 : (D ? S15 : S5)) :
(current_state == S10) ? (N ? S15 : (D ? S20 : S10)) :
(current_state == S15) ? S0 : // Force return to S0
after candy dispensing
(current_state == S20) ? S15 : S0;

// Outputs logic for candy and refund

candy = (current_state == S15) ? 1'b1 : 1'b0; // Dispense candy in
S15
refund = (current_state == S20) ? 1'b1 : 1'b0; // Issue refund in S20
end
endmodule

module clkdivider(
input clk, rst,
output slowclk
);
reg [26:0] count;
always @(posedge clk) begin
if (rst) count <= 0;
else count <= count + 1;
end
assign slowclk = count[25];
endmodule

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[21BLC1374] Lab 8 – Serial Adder & Vending Machine 23/09/2024

module bcd_to_7segment (
input [2:0] bcd,
output reg [6:0] seg0,
output reg [6:0] seg1
);

// BCD to 7-segment display

always @ (bcd) begin
case (bcd)
3'b000: begin seg1 = 7'b1000000; seg0 = 7'b1000000; end //00
3'b001: begin seg1 = 7'b1000000; seg0 = 7'b0010010; end //05
3'b010: begin seg1 = 7'b1111001; seg0 = 7'b1000000; end //10
3'b011: begin seg1 = 7'b1111001; seg0 = 7'b0010010; end //15
3'b100: begin seg1 = 7'b0100100; seg0 = 7'b1000000; end //20
default: begin seg1 = 7'b0111111; seg0 = 7'b0111111; end //Default
endcase
end
endmodule

Output:
Machine In State S0 (0 cents in the Machine):

Machine In State S5 (5 cents in the Machine):

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[21BLC1374] Lab 8 – Serial Adder & Vending Machine 23/09/2024

Machine In State S10 (10 cents in the Machine):

Machine In State S15 (15 cents in the Machine, Candy Dispense Indicated):

Machine In State S20 (20 cents in the Machine, Refund Dispense Indicated):

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[21BLC1374] Lab 8 – Serial Adder & Vending Machine 23/09/2024

Inference:
We have understood how to design a 4 bit adder using Parrallel in Serial Out Shift Registers
and a Full Adder to create a 4-bit Serial Adder and a Vending Machine using FSM Principals
and Implemented in on the Kit and used the 7 Segment Displays and LEDs to visualize the
current state of the Machine.

Result:
Thus, we have successfully designed and implemented a 4-bit Serial Adder using a full adder
and PISO registers and performed the addition of 4-bit numbers and verified its functionality
using ModelSim. We have also designed and implemented a Candy Vending Machine that
dispenses candy if 15 cents received and dispenses refund if more that 15 cents received and
Implemented in DE2-115 Kit.

[21BLC1374] BECE406E – FPGA Based Systems Design Lab Page No. 9