4.5.

2 ASNCHRONOUS BUS

An alternative scheme for controlling data transfers on the bus is based on the use of a handshake between the master and
the slave. The concept of a handshake is a generalization of the idea of the Slave ready signal in Figure 425. The common
clock is replaced by two timing control lines, Master-ready and Slave ready. The first is asserted by the master to indicate
that it is ready for transaction, and the second is a response from the save.

In principle, data transfer controlled by a handshake protocol proceed as follows. The master places the address and
command information on the bus. Then it indicates

to all devices that it has done so by activating the Master-ready line. This causes all devices on the bus to decode the
address. The selected slave performs the required operation and informs the processor it has done so by activating the
Slave-ready line. The master waits for Slave-ready to become asserted before it removes its signals from the bus. In the case
of a read operation, it also strobes the data into its input buffer. An example of the timing of an input data transfer using
the handshake scheme is given in Figure 4.26, which depicts the following sequence of events:

-t0 — The master places the address and command information on the bus, and all devices on the bus begin to decode this
information.

-t1 — The master sets the Master-ready line to 1 to inform the I/0 devices that the address and command information is
ready. The delay t1 — t0 is intended to allow for any skew that may occur on the bus. Skew occurs when two signals
simultaneously transmitted from one source arrive at the destination at different times. This happens because different
lines of the bus may have different propagation speeds . Thus, to guarantee that the Master-ready signal does not arrive at
any device ahead of the address and command information, the delay t1 — to should be larger than the maximum possible
bus skew. (Note that, in the synchronous case, bus skew is accounted for as a pan of the maximum propagation delay.)
When the address information arrives at any device, it is decoded by the interface Circuitry. Sufficient time should be
allowed for the interface circuitry to decode the address. The delay needed can be included in the period t1 — t0.

-t2 — The selected slave, having decoded the address and command information, performs the required input operation by
placing the data from its data register on the data lines. At the same time, it sets the Slave-ready signal to I. If extra delays
are introduced by the interface circuitry before it places the data on the bus, the slave must delay the Slave-ready signal
accordingly. The period t2 — t1 depends on the distance between the master and the slave and on the delays introduced by
the slave's circuitry. It is this variability that gives the bus its asynchronous nature.

-t3— The Slave-ready signal arrives at the master, indicating that the input data are available on the bus. However, since it
was assumed that the device interface transmits the Slave-ready signal at the same time that it places the data on the bus,
the master should allow for bus skew. It must also allow for the setup time needed by its input buffer. After a delay
equivalent to the maximum bus skew and the minimum setup time, the master strobes the data into its input buffet At the
same time, it drops the Master-ready signal, indicating that it has received the data
-t4 —The master removes the address and command information from the bus. The delay between t3 and t4 is again
intended to allow for bus skew. Erroneous addressing may take place if the address, as seen by some device on the bus,
starts to change while the Master-ready signal is still equal to I.

-t5 — When the device interface receives the 1 to 0 transition of the Master-ready signal, it removes the data and the
Slave-ready signal from the bus. This completes the input transfer.

The timing for an output operation, illustrated in Figure 4.27, is essentially the same as for an input operation. In this case,
the master places the output data on the data lines:

At the same time that it transmits the address and command information, the selected slave strobes
the data into its output buffer when it receives the Master.ready signal and indicates that it has done
so by setting the Slave-ready signal to 1. The remainder of the cycle is identical to the input
operation. In the timing diagrams in Figures 4.26 and 4.27, it is assumed that the master
compensates for bus skew and address decoding delay. It introduces the delays from t0 to th and
from t to t0 for this purpose. If this delay provides sufficient time for the I/O device interface to
decode the address, the interface circuit can use the Master-ready signal directly to gate other
signals to or from the bus. This point will become clearer when we study the interface circuit
examples in the next section. The handshake signals in Figures 4.26 and 4.27 are fully interlocked. A
change of state in one signal is followed by a change in the other signal. Hence, this scheme is known
as a full handshake. It provides the highest degree of flexibility and reliability.

4.5.3 DISCUSSION

Many variations of the bus techniques just described are found in commercial computers. For
example, the bus in the 68000 family of processors has two modes of operation, one asynchronous
and one synchronous. The choice of a particular design involves trade-offs among factors such as:
- Simplicity of the device interface

- Ability to accommodate device interfaces that introduce different amounts of delay

- Total time required for a bus transfer

- Ability to detect errors resulting from addressing a non-existent device or from an interface
malfunction

The main advantage of the asynchronous bus is that the handshake process eliminates the need for
synchronization of the sender and receiver clocks, thus simplifying timing design. Delays, whether
introduced by the interface circuits or by propagation over the bus wires, are readily accommodated.
When these delays change, for example, due to a change in load when an interface circuit is added or
removed, the timing of data transfer adjusts automatically based on the new conditions. For a
synchronous bus, clock circuitry must be designed carefully to ensure proper synchronization, and
delays must be kept within strict bounds. The rate of data transfer on an asynchronous bus
controlled by a full handshake is limited by the fact that each transfer involves two round-trip delays
(four end-to-end delays). This can be readily seen in Figures 4.26 and 4.27 as each transition on
Slave-ready must wait for the arrival of a transition on Master-ready, and vice versa. On synchronous
buses, the clock period need only accommodate one end-to-end propagation delay. Hence, faster
transfer rates can be achieved. To accommodate a slow device, additional clock cycles are used, as
described above. Most of today's high-speed buses use this approach.