OBJECTIVE: To design, simulate and layout a CMOS Comparator with the given specifications.

Design Specifications: 1) 2) 3) 4) 5) 6) 7) Gain > 2000 Propagation Delay < 0.75s CMR > 3V Slew Rate > 2V/s Output Dynamic Range > 3V Power Supply = + 5V Load Capacitance CL = 5pF

Spice Parameters for the AMI 1.5 technology: NMOS:

K N = 7.55 105 A / V 2
'

N = 0.07V 1
VTN = 0.68V PMOS:
K P = 2.15 105 A / V 2
'

P = 0.12V 1
VTP = 0.75V

INTRODUCTION:

In this project, a simple CMOS comparator was designed, simulated using Cadence tool kit and finally a layout was done using L-Edit Layout Tool. The design was based on a +/-5V power supply, AMI 1.5-micron technology. To meet the given specifications, a two-stage open loop comparator design was used. This design is very similar to the one of a differential op amp without compensation. However the output of the comparator will only take on two values, either the logic high (when it goes up to VOH) or logic low, (output drops to VOL) depending on the difference between two analog inputs.

Schematic of a two stage open loop comparator DESIGN METHODOLOGY:

As a starting point for the hand design the specifications are considered. Out of all the given specifications the most difficult to achieve was the propagation delay tp and gain. So, as the first step the propagation delay was assumed to be 0.60 s. Now in a CMOS comparator the propagation delay tp is expressed as
2k t p = RC ln 2k 1 .(1)

where R is the total equivalent resistance and C is the total equivalent capacitance in the output stage of the comparator. Here the factor k is given as k= Vin Vin (min) (2)

In this case the value of k is unity. Thus the expression for tp as shown in equation (1) modifies to
t p = RC ln 2 t p = 0.693RC

Now here the value of C is the value of the load capacitance i.e. 5pF. Thus our assumption of t p to be 0.60s leads us to the relation

0.60 s = 0.693 R 5 pF R = 174.3k This R in our circuit topology corresponds to ( rds6 || rds7 ). Thus have, (rds 6 rds7 ) = 174.3K 1 1 = 174.3K n I d 7 p I d 6 But from the topology Id6 = Id7 = Id. Thus,

n I d + p I d =

1 174.3k

Id6 = Id7 = Id = 43 A.
But to be have some margin the value is assumed somewhat larger than the obtained value. Thus the value is assumed is

I d 6 = I d 7 = I d = 50 A.
Now, the value of Id5 is taken to be one-fifth of the Id7. Thus the value is

I I d 5 = d 7 = 10 A. 5
Now assuming that the transistor pairs M1, M2 & M3, M4 are matched, ideally
I d1 = I d 2 = I d 3 = I d 4 = Id 5 = 5A. 2

Gain is the most important parameter to be achieved in a comparator design. The design is to done in such a way that the desired gain is obtained. Here gain (Av) of more than 2000 is required . Hence assuming a gain of 2500 to be achieved. Now the total gain Av is given by

AV (tot ) = AV 1 AV 2 A gain of 25 is desired to be obtained from the second stage. Here Vdssat can be upto 2 V for M6. For this Vdssat we got W/L to be unity. Although this W/L is fine the required amount of gain is not obtained using this W/L. So to obtain the required gain we need to change the W/L. For Vdssat = 0.5 V we get W/L = 18. Using this value the transconductance of M6 can be evaluated by the following expression
W gm6 = 2k 'p I d 6 L 6 This gives us g m 6 = 207.2 A / V This also gives us a gain of 25 from the second stage which is as desired. Thus
W = 20 L 6 Now the gain required from the first stage is 100. AV 1 = gm2 (rds2 || rds4 ) = 100 From the current values we get 1 rds2 = I = 2.85M N d2
1 rds4 = I = 1.66 M P d4

rds2 || rds3 = 1.05M This gives the transconductance of M2 by the formula given above gm2 = 95.2 A / V Thus the size of M2 was calculated by the relation
' W gm2 = 2k n I d 2 L 2

W = 12.02 12 L 2 Now as the M1 and M2 are matched, their sizes should be the same.

W = 12 L 2 The basic rule for the proper operation of the comparator is that Vds 3 = Vgs 6 From the current equation Vgs6 = Vds3 = 1.237 V But we have Vds4 = Vds3 and Vds3 = Vgs3 = Vgs4. Hence Vgs4 = 1.237 V. Now with this knowledge the sizes of M3 & M4 are computed using the current expressions to get W W = =3 L 3 L 4 Now the size of M5 is decided using the CMR requirements. The transistor M5 has to remain in saturation. For M5 to remain in saturation : Vds 5 = Vgs 5 VT 5 . Vin ( cm ) Vgs1 (Vss ) = Vgs 5 VT 5

Take Vincm = 3V and from the current equation for Id1 we get Vgs1=0.785 V Vgs 5 VT 5 = 1.21V Thus using the current equation we get W =1 L 5 The current in both the stages is provided by using current mirrors. The current Id5 is 10A. So to keep the amount of current as minimum as possible, a reference current of 10A is assumed in the transistor M8. This leads to the sizes of M8 and M5 to be equal as Vgs of both transistors are equal. Hence W W = =1 L 8 L 5 The current in M7 being five times that in M8 gives the size of M7 to be five times that of M8. W = 5 L 7

Thus the dimensions of all the transistors are obtained. These are specified in the table below:
TRANSISTOR M1 M2 M3 M4 M5 M6 M7 M8 W(m) 18 18 3 3 1.5 30 7.5 1.5 L(m) 1.5 1.5 1.5 3 1.5 1.5 1.5 1.5

SIMULATION RESULTS AND CHANGES MADE IN THE DESIGN

The proposed design was simulated using Cadence tool. The simulation was performed using the AMI 1. 5 technology parameters. Initially the designed values were used to simulate the circuit, the output that was expected was not achieved. The gain was very small and the propagation delay was higher than what was required. Hence the design was modified to achieve the specifications. The main aim again was to keep transistors to the minimum possible sizes. But this time the saturation voltages of the transistors were reduced. Initially as mentioned in the design methodology the saturation voltages of the output state transistors was taken to be VDD-V OH and V SS-V OL . But as this did not give desired results the saturation voltages were taken to be 0.5 V and the design was accordingly modified. This gave the desired results. The original results and the changes made are described below:
Resolution: On simulating the design with the obtained parameters it was found that the circuit works as a comparator for input voltage values larger than 2.6 mV. This voltage gives us the resolution of the comparator as 2.6 mV. This is minimum value of the voltage that should be applied to the circuit for it to act as a comparator. Gain: The Gain of the comparator was found out to be 865. This is quite less than what the specifications are. It was found out that the first stage provided less amount of gain than required. So the sizes of the input stage transistors were modified to obtain the required gain.

It is known that gain of the system is directly proportional to the rds of the transistors. Also rds of a transistor is inversely proportional to the and is inversely proportional to the channel length. So rds is directly proportional to the channel length. Hence to increase the gain of the first stage the lengths and widths of all the transistors were doubled keeping the W/L ratio same. As L is doubled is halved and hence the rds is doubled thereby increasing the gain of the system. After doubling the lengths and the width the gain was obtained as per the requirements.
Propagation delay: The propagation delay observed was 0.314 s for the fall time and 0.02 s for the rise time at an input of 3V. Now for an input of + 1.295 mv (i.e. Vin(min)) the propagation delay is found to be 0.325 s for the fall time 0.03 s for the rise time. The propagation delay obtained for the minimum value of input is the worst propagation delay. Slew rate: The slew rate was observed to be 13.8 V/s. Output dynamic range: The output dynamic range was obtained to be + 4.9 V. Common Mode range: The common mode range is + 4.5 V to 3.7 V. For positive value it was check that M1 remains in saturation and for the negative value it was verified that M5 remains in saturation.

Final Dimensions of the Transistors after Simulation

TRANSISTOR M1 M2 M3 M4 M5 M6 M7 M8

W(m) 36 36 6 6 1.5 30 7.5 1.5

L(m) 3 3 3 3 1.5 1.5 1.5 1.5

Comparison of the hand calculated and the simulated values

Parameters Gain AV Propagation Delay tp Slew Rate SR Output Dynamic range Common Mode range Resolution

Calculated Values 2500 0.40 s 10V/ s + 4.5 V + 3.5 V 2.4 mV

Simulated Values 3384 0.324 s 13.8 V/s + 4.9 V + 4.9 V to 3.7 V 2.6 mV

As the table shows, there are still some differences between the designed values and the ones that were finally obtained in simulation. This is because several simplifications were assumed in the design and the parasitic capacitances not considered at all.

LAYOUT OF THE COMPARATOR

Once the simulation of the designed circuit was completed, the layout of the circuit was done using Tanner L-Edit Pro V9.0 tool kit. Various considerations are to be taken in to account while doing the layout. The first and the foremost thing is the proper matching of the transistors of the differential input stage and the active loads. This is necessary because even a small mismatch at the input stage will show up at the output as a larger mismatch and affect the performance of the circuit. Proper matching is achieved by splitting up the large transistors into smaller sized ones and using the centroid layout technique. For matching the differential input pair same source was used for both transistors M1 and M2. The entire transistors were split up into smaller ones and were connected in parallel using the centroid layout techniques. Similarly transistors M3 and M4 were also split up into smaller ones. Finally the current mirrors M8, M5 and M7 were made in the same substrate to provide suitable matching. This is necessary because these are the transistors that provide the current to various branches of the comparator and hence must be matched. Here M7 had a bigger size and hence it was split up in to smaller ones of the size of M5 and M8 and connected in parallel. Body contacts were provided to avoid body effect for each of the substrate. During the entire layout various rules regarding the dimensions, spacing and connections were followed as per the standards. Also care was taken to consume minimum area and power during the layout by reducing the interconnects.
CONCLUSION:

The comparator design meets the required specifications. Although there are many factors that need to be taken into account while designing a good comparator. The major factor that affects the performance is the DC offset voltage due to mismatch in the input stage. This can show up at the output as a considerable voltage. This has to be taken care of by proper matching of the input transistors. Also another factor affecting the performance is the speed or the propagation delay of the delay. To get a high-speed comparator a cascaded comparator can be used. Also if the comparator is to be placed in a noisy environment then the output will also be noisy in response to a noisy input. In this case the transfer characteristic of the comparator is to be modified. A comparator with hysterisis can be used which basically forces the transition from low to high to occur at a different time than the transition from high to low. If we need to drive large capacitive loads then we can put push-pull inverters in cascade with the output stage of our design. Finally the layout was done so as to achieve maximum matching and minimum interconnects so as to reduce the parasitic capacitances.

Here is the layout the comparator: