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    Lab 07

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    This document summarizes an OTA design methodology project. It involves: 1) Plotting gm/ID design charts for NMOS and PMOS transistors. 2) Designing an NMOS input stage OTA topology to meet the CMIR specification. 3) Simulating the open-loop OTA and comparing results to hand calculations. 4) Simulating the closed-loop OTA in unity gain configuration and analyzing loop gain characteristics.

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    Lab 07

    Uploaded by

    احمد على
    13 views12 pages
    This document summarizes an OTA design methodology project. It involves: 1) Plotting gm/ID design charts for NMOS and PMOS transistors. 2) Designing an NMOS input stage OTA topology to meet the CMIR specification. 3) Simulating the open-loop OTA and comparing results to hand calculations. 4) Simulating the closed-loop OTA in unity gain configuration and analyzing loop gain characteristics.

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    This document summarizes an OTA design methodology project. It involves: 1) Plotting gm/ID design charts for NMOS and PMOS transistors. 2) Designing an NMOS input stage OTA topology to meet the CMIR specification. 3) Simulating the open-loop OTA and comparing results to hand calculations. 4) Simulating the closed-loop OTA in unity gain configuration and analyzing loop gain characteristics.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    13 views12 pages

    Lab 07

    Uploaded by

    احمد على
    This document summarizes an OTA design methodology project. It involves: 1) Plotting gm/ID design charts for NMOS and PMOS transistors. 2) Designing an NMOS input stage OTA topology to meet the CMIR specification. 3) Simulating the open-loop OTA and comparing results to hand calculations. 4) Simulating the closed-loop OTA in unity gain configuration and analyzing loop gain characteristics.

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    © All Rights Reserved
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    of 12

    Lab 07 gm/ID Design Methodology

    Part 1: gm/ID Design Charts


    Using ADT Device Xplore, plot the following design charts vs gm/ID for both PMOS and
    NMOS. Set VDS = VDD/3 and L = 0.18u,0.5u:0.5u:2u

    NMOS

    PMOS
    Part 2: OTA Design
    0.18um CMOS
    Since the required CMIR is close to the supply rail ,I will use NMOS input stage so the
    topology will look like the following figure:
    Part 3: Open-Loop OTA Simulation
    1) Schematic of the OTA with DC node voltages clearly annotated.

    • Is the current (and gm) in the input pair exactly equal? yes
    • What is DC voltage at VOUT? Why? VOUT = 1.072V
    Vin = Vin CM ,so Vp =0 ----> current equal in two branches -----> Vgs in CM load are
    equal -----> VDS in CM load are equal ---------> VOUT follow mirror node so the
    circuit behaves perfectly symmetric.

    2) Diff small signal ccs:


    • Plot diff gain (in dB) vs frequency.
    • Compare simulation results with hand calculations in a table.

    Analytic Simulation
    Gain_dB 34.15dB 34.6dB
    Gain 51 53.7
    BW 100kHz 93.84kHz
    GBW 5.15MHz 5.051MHz
    UGF 5.15MHz 5.045MHz
    3) CM small signal ccs:
    • Plot CM gain in dB vs frequency.

    • Compare simulation results with hand calculations in a table.


    AoCM = gds_tail/(2*gm3,4) = 1.3/(2*65.4) = 10m Analytic Simulation
    AoCM = -40dB Gain_dB -40dB -39.56dB
    • (Optional) Avcm vs VICM: Gain 10m 10.51m
     Plot CM gain at 1Hz in dB vs VICM.

     Justify the results.


    When VICM increases VDS_tail increase ( VICM = VGS1 + VDS_tail ) ,so RSS (
    ro_tail) increase with VDS ,therefore AoCM decrease (RSS degenerate gain)
    then AoCM saturate due to constant RSS in deep saturation.
    4) CMRR:
    • Plot CMRR in dB vs frequency at VICM at the middle of the CMIR.

    • Compare simulation results with hand calculations in a table.


    CMRR = Aodiff - AoCM = 34.15 – (-40) = 74.15dB Analytic Simulation
    • (Optional) CMRR vs VICM: CMRR 74.15dB 74.16dB

     Plot CMRR at 1Hz in dB vs VICM.

    ➢ Justify the results.


    When VICM increases VDS_tail increase (VICM = VGS1 + VDS_tail) ,so RSS (
    ro_tail) increase with VDS ,therefore AoCM decrease (RSS degenerate gain)
    ,therefore CMRR increase (CMRR = Aodiff – AoCM) until RSS saturate at larger
    value , the CMRR saturate at larger value. Then CMRR start to degradate due to
    input pair mosfet come into triode (ro decrease and Avd start degradate).
    5) Diff large signal ccs:
    • Plot VOUT vs VID.

    • From the plot, what is the value of Vout at VID = 0? Why?


    Vout = 1.072V. Vin = Vin CM only , Vind = 0 ,so Vp =0 ----> current equal in two
    branches -----> Vgs in CM load are equal -----> VDS in CM load are equal --------->
    VOUT follow mirror node so the circuit behaves perfectly symmetric.
    • Plot the derivative of VOUT vs VID. Compare the peak with Avd.

    Peak = 54.2 almost equal Avd


    6) CM large signal ccs (region vs VICM):
    • Plot “region” OP parameter vs VICM for the input pair and the tail current source.
    • Find the CM input range (CMIR). Compare with hand analysis in a table.
    VICM_min = VGS1 + Vdsat_tail = 670.9 + 145.3 = 816.2mV
    VICM_max = VDD – VGS3 + Vth1 = 1.8 – 728.5m + 567.8m = 1.64V
    From simulation : 730m --------> 1.74 Analytic Simulation
    CMIR 824mV 1.01V
    7) (Optional) CM large signal ccs (GBW vs VICM):
    From simulation CMIR : 449.29m --------> 1.41 Region method GBW method
    CMIR 1.01V 0.96V
    PART 4: Closed-Loop OTA Simulation
    1) Schematic of the OTA with DC OP point clearly annotated in unity gain buffer
    configuration.

    • Is the current (and gm) in the input pair exactly equal? Why?
    Not equal. Because the output will follow the input. The output voltage deviates
    from its CM level (the voltage at the mirror node for the 5T OTA) in order to match
    the input voltage. Since the gain is finite, there will be a non-zero differential input
    voltage that will cause an imbalance between the two sides of the differential pair.
    • Calculate the mismatch in 𝐼𝐷 and gm.
    Δgm = 158.9 – 155.8 = 3.1uS
    Δ𝐼𝐷 = 9.77 – 9.487 = 0.283uA
    2) Loop gain:
    Plot loop gain in dB and phase vs frequency.

    Compare DC gain and GBW with those obtained from open-loop simulation.
    Comment

    Gain_LG , GBW are not effected due to feedback factor = 1 Gain_LG = β AOL = AOL ,
    GBW is always const because the output node is dominant pole and the system
    behavior near to first order, when gain multiply by factor the BW divided by the
    same factor.

    Gain_LG = AOL = 53.7 GBW = const = 5.051MHz

    BW equal the same Bw for open loop ( due to GBW is const) = 93.84kHz

    Compare simulation results with hand calculations in Loop gain Analytic

    a table. Gain_dB 34.4dB 34.6dB


    Gain 52.48 53.7
    BW 95.34kHz 93.84kHz
    Note: analytic calculations steps is the same as open GBW 5.015MHz 5.051MHz
    loop calculations. UGF 5.006MHz 5.045MHz

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