Embedded System Design

BITS Pilani Prof. Manoj S Kakade

Dept of EEE
Pilani Campus
 BITS Pilani
Pilani Campus

ESZG512/MELZG526/SEZG516
Embedded System Design
Contact Session 5
Contents
• Polling, interrupt, DMA
ARM Cortex-M4:
• Exceptions and Interrupts
• Exception handlers in C
• Exception entry behavior
• Exception return behavior

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Polling
 Polling
 The microcontroller continuously monitors the status of a given
device.
 When the conditions are met, it performs the service.
 After that, it moves on to monitor the next device until everyone is
serviced.
 The polling method is not efficient since it wastes much of the
microcontroller’s time by polling devices that do not need service.

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 Interrupt

 Interrupt
 Whenever any device needs its service, the device notifies the
microcontroller by sending it an interrupt signal.
 Upon receiving an interrupt signal, the microcontroller interrupts
whatever it is doing and serves the device.
 The program which is associated with the interrupt is called the
interrupt service routine (ISR) or interrupt handler.
 The advantage of interrupts is that the microcontroller can serve
many devices (not all at the same time)
 Each device can get the attention of the microcontroller based on the assigned priority.

 The limiting factor for the data transfer is the time to recognize,
process and return from the interrupt.
5

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 DMA

 DMA
 It is a device that can initiate and control, bus accesses between I/O
devices and memory and between two memory areas.
 Using a DMA controller is reasonably simple, provided the
programming defines exactly the data transfer operations that the
processor expects.
 Low latency I/O data transfer method.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Overview of exceptions and interrupts
 Interrupts are events typically generated by hardware (e.g.,
peripherals or external input pins) that cause changes in program
flow control outside a normal programmed sequence.
 In addition to interrupt requests, there are other events that need
servicing, and we call them “exceptions.”
 In ARM terminology, an interrupt is one type of exception.
 All Cortex-M processors provide a Nested Vectored Interrupt
Controller (NVIC) for exception handling.

Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors” 7

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Sources of Exceptions
Various sources of exceptions in a typical microcontroller

Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors” 8

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Sources of Exceptions
 Cortex-M4 NVIC supports:
 Up to 240 IRQs (Interrupt Requests)
 Non-Maskable Interrupt (NMI)
 The NMI is usually generated from peripherals like a watchdog timer or Brown-Out Detector
(BOD).

 SysTick (System Tick) timer interrupt.

 Number of system exceptions.
 Most of the IRQs are generated by peripherals such as timers, I/O
ports, and communication interfaces (e.g., UART, I2C).
 The rest of the exceptions are from the processor core.
 Interrupts can also be generated using software.
Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors” 9

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Exception types
 Exceptions are numbered 1 to 15 for system exceptions and 16 and
above for interrupt inputs (inputs to the processor, but not
necessarily accessible on the I/O pins of the package).
 Most of the exceptions, including all interrupts, have programmable
priorities, and a few system exceptions have fixed priority.
 Different Cortex-M3 or Cortex-M4 microcontrollers can have
different numbers of interrupt sources (from 1 to 240) and different
numbers of priority levels.
 This is because chip designers can configure the Cortex-M3 or Cortex-M4
design source code for different application requirements.

Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors” 10

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Exception types
List of System Exceptions

Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors” 11

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Exception types

Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors” 12

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Exception types

Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors” 13

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Exception types

Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors” 14

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Exception handlers
Exception handlers:
The processor handles exceptions using:
Interrupt Service Routines (ISRs)
 Interrupts IRQ0 to IRQ239 are the exceptions handled by ISRs.
Fault handlers
 Hard fault, memory management fault, usage fault, bus fault are
fault exceptions handled by the fault handlers.
System handlers
 NMI, PendSV, SVCall SysTick, and the fault exceptions are all
system exceptions that are handled by system handlers.

Source: ARMv7M Architecture Reference Manual 15

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Vector table

Source: ARMv7M Architecture Reference Manual 16

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 Exception handlers in C
 C compilers for ARM architecture follow a specification from
ARM called the AAPCS (ARM Architecture Procedure Calling
Standard ), Procedure Call Standard for ARM Architecture.
 A C function can modify R0 to R3, R12, R14 (LR), and PSR.
 If the C function needs to use R4 to R11, it should save these
registers on to the stack memory and restore them before the end of
the function.
 R0 - R3, R12, LR, and PSR are called “caller saved registers.”
 R4 - R11 are called “callee-saved registers.”

Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors” 17

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Exception handlers in C

Register usage in a function call in AAPCS

18
Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors”

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Exception entry behavior
 On preemption of the instruction stream, the hardware saves
context state onto a stack pointed to by one of the SP registers.
 The stack used depends on the mode of the processor at the time of
the exception.
 The stacked context supports the ARM Architecture Procedure
Calling Standard (AAPCS). This means the exception handler can
be an AAPCS-compliant procedure.

Source: ARMv7M Architecture Reference Manual 19

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The ARMv7-M architecture uses a full-descending stack, where:
 When pushing context, the hardware decrements the stack pointer
to the end of the new stack frame before it stores data onto the
stack.
 When popping context, the hardware reads the data from the stack
frame and then increments the stack pointer.

When pushing context to the stack, the hardware saves eight 32-bit
words, comprising xPSR, Return Address, LR(R14), R12, R3, R2,
R1, and R0.

Source: ARMv7M Architecture Reference Manual 20

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Stacking and vector fetch
Stacking and vector fetch

Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors” 21

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Stacking sequence in the Cortex-M3 processor on AHB lite interface

Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors” 22

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 If the processor was in Thread mode, and was using MSP (bit 1 of
the CONTROL register is 0, as in the default setting), the stacking
operation is carried out in the main stack with MSP.

Exception stacking in thread mode using the main stack

Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors” 23

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 If the processor was in Thread mode, and was using the process
stack (bit 1 of the CONTROL register is 1), then the stacking
operation is carried out in the process stack with PSP.
 After entering Handler mode, the processor must be using the
MSP, so the stacking operation of all nested interrupts are carried
out with the main stack with MSP.

Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors” 24

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Exception stacking in thread mode using the process stack, and nested interrupt
stacking using the main stack
25
Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors”

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Source: ARMv7M Architecture Reference Manual 26

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Saving context on process switch
 When switching between different processes, software must save
all context for the old process, including its associated
EXC_RETURN value, before switching to the new process, and
restore that context before returning to the old process.

Source: ARMv7M Architecture Reference Manual 27

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 EXC_RETURN
 Since the value of the return address (PC) is not stored in LR as in
normal C function calls (the exception mechanism puts an
EXC_RETURN code in LR at exception entry, which is used in
exception return), the value of the return address also needs to be
saved by the exception sequence.
 So in total eight registers need to be saved during the exception
handling sequence on the Cortex-M3 or Cortex-M4 processors
without a floating point unit.

Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors” 28

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EXC_RETURN
EXC_RETURN
 As the processor enters the exception handler or Interrupt Service Routine
(ISR), the value of the Link Register (LR) is updated to a code called
EXC_RETURN.
 The exception mechanism relies on this value to detect when the processor has
completed an exception handler.
 The lowest five bits of this value provide information on the return stack and
processor mode.

Source: ARMv7M Architecture Reference Manual 29

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EXC_RETURN

30
Source: ARMv7M Architecture Reference Manual

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Exception return behavior
Exception return behavior
 An exception return occurs when the processor is in Handler
mode and one of the following instructions loads a value of
0xFXXXXXXX into the PC:
 POP/LDM that includes loading the PC.
 LDR with PC as a destination.
 BX with any register.

When used in this way, the processor intercepts the value written to
the PC. This value is the EXC_RETURN value.

Source: ARMv7M Architecture Reference Manual 31

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 At the end of an exception handler, the bit 2 of the
EXC_RETURN value generated at the exception entrance is used
to decide which stack pointer should be used to extract the stack
frame.
 If bit 2 is 0, the processor knows that the main stack was used for
stacking, as shown in Figure.

Source: ARMv7M Architecture Reference Manual 32

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 33
Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors”

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 If bit 2 is 1, the processor knows that the process stack was used
for stacking, as shown in the second unstacking operation in Figure

Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors” 34

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 35
Source: Joseph Yiu, “The Definitive Guide to ARM Cortex-M3 and Cortex-M4 Processors”
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Lab Instructor :
Prof. S.S. Kendre
Email ID : kendres.shankarrao@wilp.bits-pilani.ac.in

Lab Access:
Mr. Vishal (08322580217/ 7720893522)
Email ID: vishal@wilp.bits-pilani.ac.in

Thank you
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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956