AN4507 Application Note

TGD-1X

AN4507
Gate Drive Considerations For IGBT Efficiency
Application Note
Replaces March 1998 version, AN4507-1.3 AN4507-2.0 January 2000

This note describes considerations that should be taken into 1.2 IGBT SWITCHING LOSSES
account when designing a gate drive circuit for an IGBT, and
gives some typical circuit suggestions. When turning an IGBT on or off the switching losses of the
device are affected by the level of Vge and the Gate Resist-
When designing a gate drive for an application the ance Rg. The effect of increasing Vge or reducing Rg is to
following items should be considered:- reduce the delay time, rise time and fall times of the device
and hence to reduce the switching losses. Reducing the
1) Conduction Losses level of Vge or increasing Rg results in increased switching
2) IGBT Switching Losses losses, but can reduce Electromagnetic Emissions (EMI).
3) Anti parallel Diode Switching Losses Other factors affecting the switching losses are the anti
4) Device Protection parallel diode (FWD), circuit inductance, snubbers, device
5) Drive Circuit Isolation and Control Signal Trans- junction temperature, operating voltage and current etc.
mission
6) Circuit Layout

1.1 CONDUCTION LOSSES

Rg
When an IGBT is turned on the collector emitter voltage Vce
FWD1
is a function of gate emitter voltage Vge. As Vge is increased VGE
the conduction losses are reduced. It is desirable therefore
to increase Vge. to the maximum allowed on the data sheet
to minimise the conduction losses, however device manu-
facturers only guarantee short circuit capability with a Vge of
15V or less. A typical output characteristic for an IGBT is
given below.
Rg
FWD2
VGE

IC

VGE = 20V Fig.2

VGE = 15V
1.3 ANTI PARALLEL DIODE SWITCHING LOSSES
4x IC rated The reverse recovery and turn on characteristics of the
VGE = 12V FWD are affected by all the factors mentioned in 1.2, and
can therefore be controlled to a certain extent by adjusting
the speed of the IGBT. In the event of a diode becoming too
VGE = 8V
IC rated snappy in a application, the IGBT turn on can be slowed
down hence reducing the value of di/dt applied to the diode
so reducing the diode losses; but at the expense of increas-
VCE
ing the IGBT losses. An alternative method of reducing the
FWD losses in a bridge configuration is to turn on the IGBT
Fig.1 Typical output characteristics from a reduced Vge. This limits the peak reverse recovery
current, Irr, of the FWD in the opposite side of the arm,

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AN4507
TGD-1XApplication Note

according to the IGBTs' forward output characteristic, see When a device experiences a short circuit, the current is
fig.1. limited according to the devices transfer characteristic.
Assuming a Vge of 15V the short circuit current can reach
1.4 DEVICE PROTECTION CONSIDERATIONS values of 3 to 4 times the devices rated forward current.

The majority of IGBT manufacturers guarantee that IGBT’s VCE, IC

will withstand a short circuit for 10µs at 50% of the devices
rated voltage, with a Vge of 15V and a starting temperature
of <125˚C. Two different types of short circuit conditions VCE
should be considered.
i) When a device is switched into an already existing short
circuit see fig 3 for typical waveforms.

ii) When a short circuit appears whilst the device is already IC

conducting (see fig 4).

In the second instance both the voltage and collector current

rise very quickly and the rapidly rising dv/dt coupled with the
miller capacitance can increase the effective Vge seen by the
IGBT, further increasing the short circuit current level eq[1]. Time
For this reason it is good practice to connect some back-to- Fig.4 Typical waveforms of IC and VCE of IGBT being
back zener diodes directly across the gate emitter terminals switched
to limit the level of Vge (see fig 5). into a short circuit

Vge = C dv/dt * Rg + Vg [1]

VCE, IC

VCE Miller capacitance

Rg
FWD

IC Vg

Time
Fig.3 Typical IC and VCE waveforms of IGBT being switched
into a short circuit Fig.5 Showing Zener diodes clamping VGE

If the device is switched into an already existing short circuit The fault current can be reduced by reducing Vge. If the user
the dv/dt problem does not exist, and the miller effect is not reduces Vge to <15V the period of time for which the short
considered to be as significant a problem. circuit can be with stood is increased, this circuit is shown in
fig 6.
If the value of Rg is increased the rise time of the short circuit
current can be increased, reducing the energy loss during If a device is being used in a application with a Vge of >15V
the short circuit. At turn off an increased Rg can slow the manufacturers will not guarantee the device will turn of the
devices di/dt hence reducing overvoltages. resulting fault current which can increase to levels in excess

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 AN4507 Application Note
TGD-1X

of 10 times the devices rated current. The user should also The -ve bias is also useful for minimising the risk of FWD's
be aware that when turning off fault currents the di/dt is snapping off at high dv/dts, causing the IGBT device in
considerably greater than is seen under normal operation parallel with the FWD to turn back on due to the Miller
and the overshoot voltages due to parasitic inductances are capacitance effect.
increased.

NPN
PNP

NPN

PNP

NPN PNP PNP

Fig.6 Schematic showing method of reducing gate drive voltage.

1.4-1 THE USE OF NEGATIVE GATE BIAS 1.4-2 GATE DRIVE FAILURE PROBLEMS
In addition to the above considerations it is recommended Other important features the designer of the gate drive
to use a -ve gate bias of -15V when turning off an IGBT should consider are failure of the gate drive or the effect due
during a short circuit. A -ve bias of -5V is often recom- to temporary loss of power. If the gate drive circuit fails it is
mended as being the minimum -ve bias required. A -ve bias helpful to have known starting condition or a condition the
is essential when turning off a fault current for the following circuit will end in. This can easily be achieved by introducing
reasons. The threshold voltage Vth reduces by approxi- a resistor into the gate emitter connection that will discharge
mately 10mV/C junction temperature rise. Under fault con- the gate emitter in the event of the gate drive loosing power,
ditions the Vth can be as much as 2V below the 25˚C figure see fig.8.
quoted on the data sheet, also inherent parasitic and mutual
inductance within the IGBT module can introduce a further
reduction in the turn off voltage seen by the individual IGBT
chips in the module, see fig 7.

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AN4507
TGD-1XApplication Note

1.5 DRIVE CIRCUIT ISOLATION AND CONTROL

SIGNAL TRANSMISSION
In power electronic circuits it is usually necessary to isolate
the drive circuit components from the control circuitry. For
FWD this purpose the power is normally transmitted to the drive
circuit via a transformer (see fig 9). The control and fault
VR VGE signals can also be transmitted too and from the drive circuit
VL1
via transformers or alternatively by opto isolators. Whatever
VTR method is used, care should be taken to ensure that there
is suitable, voltage capability, speed, and immunity to dv/dt.
VL2
1.6 CIRCUIT LAYOUT
Particular attention should be given to the drive circuit layout
-V
to maximise noise immunity due to parasitic circuit ele-
-V + VTR + VR +VL1 = VGE < VTH to turn IGBT off ments, and also to ensure that the correct tracking distances
(VTH = ƒ(Tj)IC.Va) are maintained for the operating voltage being used. If wires
have to be used to connect the drive circuit to the gate and
Fig.7 Circuit showing effect of parasites emitter connections of the IGBT they should be kept as short
as possible and twisted together to reduce the effect of any
noise voltages that may be induced in the wires. It is bad
practice to connect the emitter connection of the gate circuit
into the path of the collector emitter current, this is due to the
Rg very high load current di/dt’s seen in the circuit and the
Rg << Rd inherent parasitic inductance in any conductor. In special
cases where this may be considered as an advantage is
Rd when it is used to improve sharing during the switching
operation of parallel devices, by providing -ve feedback to
the gate voltage thereby slowing down the switching opera-
tion of the faster devices in the network. This is not recom-
mended and is only included here for completeness. When
Fig.8 Circuit showing failsafe resistor
considering the transient current sharing of a number of
paralleled modules a slight difference in emitter potentials in
the power circuit can give rise to oscillations in the drive
circuit.

Vs

NPN
NPN
D Q
Ck Ch To Base Drive Control
T
PNP PNP

Fig.9 Circuit showing simple method of supplying power via a transformer

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 AN4507 Application Note
TGD-1X

To damp these oscillations out it can be helpful to place the 1. Gate is discharged until gate emitter voltage reaches the
gate resistor in the gate emitter connection to the IGBT miller plateau and the collector emitter voltage begins to rise
rather than in the traditional gate connection see fig 10. slowly.

2. Collector Emitter voltage rises quickly. The rate of rise of

C this voltage can be controlled via altering either the gate
resistor or the gate turn off voltage. With a large resistor the
rate of rise of voltage is very slow, if the gate resistance is
reduced until the rate of voltage rise is limited by the rate of
current rise than further reductions in Rg have no beneficial
effect
G
AUX E 3. when the Collector emitter voltage has reached the DC
link voltage the current in the IGBT falls rapidly. This rapid
current fall causes an over voltage due to parasitic induct-
E ance in the circuit, an additional over shoot is caused by the
VFR of the diode turning on. The initial rate of fall of current
Fig.10 is independent of the gate drive circuit if Vge is below the
threshold voltage, but it can be slowed if the gate emitter
The majority of problems with current sharing can be mini-
voltage is slightly above the threshold voltage at turn off, this
mised by ensuring that the current paths to the individual
however causes significant increase in switching losses
modules are the same length and arranging the leads to
and should only be used to remove fault conditions
equalise the effect of any mutual inductances between
current paths to the individual paralleled modules.
4. The last stage of the turn off process is completed by the
tail current which can not be affected by the gate drive.
2.0 DESCRIPTION OF THE GATE DRIVE AND IGBT
TURN OFF WAVEFORMS
The turn off behaviour of an IGBT can be split into 4 phases
as follows

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AN4507
TGD-1XApplication Note

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