DATA SHEET

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8 MHz, Rail-To-Rail, CMOS

Operational Amplifier 5
1
SC70−5 TSOP−5/SOT23−5
NCS20161, NCS20162, CASE 419A CASE 483

NCS20164, NCV20161,
NCV20162, NCV20164 8
1
The NCS20161, NCS20162, and NCS20164 are a family of single,
dual and quad operational amplifiers (op amps) that provide 8 MHz Micro8]/MSOP8 SOIC−8
gain−bandwidth product while consuming 500 A of quiescent CASE 846A CASE 751
current per channel. The NCS2016x has an input offset voltage of
0.3 mV and operates from 1.8 V to 5.5 V supply over a wide
temperature range (−40°C to 125°C). The rail−to−rail input and output 14 14
operation allows the use of the entire supply voltage range. Thus, this 1
series of op amps offers superior performance over many industry 1
standard parts. These devices are AEC−Q100 qualified when denoted TSSOP−14 SOIC−14
CASE 948G CASE 751A
by the NCV prefix.
With low current consumption and low supply voltage operation in
industry standard packages, the NCS20161 series is ideal for sensor
signal conditioning and low voltage current sensing applications in DEVICE MARKING INFORMATION
See general marking information in the device marking
automotive, consumer and industrial markets. section on page 2 of this data sheet.

Features
• Gain−Bandwidth Product: 8 MHz
ORDERING INFORMATION
• Low Supply Current per Channel: 500 A typ (VS = 5.5 V)
See detailed ordering and shipping information on page 3 of
• Low Input Offset Voltage: ±0.3 mV this data sheet.
• Wide Supply Range: 1.8 V to 5.5 V
• Wide Temperature Range: −40°C to +125°C
• Rail−to−Rail Input and Output
• Unity Gain Stable
• Available in Single, Dual and Quad Packages
• NCV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant

Applications
• Automotive
• Battery Powered / Portable
• Sensor Signal Conditioning
• Low Voltage Current Sensing
• Filter Circuits
• Unity Gain Buffer

This document contains information on some products that are still under development.
onsemi reserves the right to change or discontinue these products without notice.

© Semiconductor Components Industries, LLC, 2021 1 Publication Order Number:

September, 2023 − Rev. 2 NCS20161/D
NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

MARKING DIAGRAMS

Single Channel Configuration

NCS20161, NCV20161

5
XXMG
XXXAYWG
G
G
1
SC70−5 TSOP−5/SOT23−5
CASE 419A CASE 483

Dual Channel Configuration

NCS20162, NCV20162
8 8
XXXX 20162
AYWG ALYW
G G
1 1

Micro8]/MSOP8 SOIC−8
CASE 846A CASE 751

Quad Channel Configuration

NCS20164, NCV20164

14 14
XXXX
XXXX 20164G
ALYWG AWLYWW
G
1 1

TSSOP−14 SOIC−14
CASE 948G CASE 751A

XXXXX = Specific Device Code

A = Assembly Location
WL, L = Wafer Lot
Y = Year
WW, W = Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)

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 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

Single Channel Configuration

NCS20161, NCV20161

OUT 1 5 VDD IN+ 1 5 VDD

+
VSS 2 VSS 2
−

−
IN+ 3 4 IN− IN− 3 4 OUT

SOT23−5 (TSOP−5) SC70−5

SN2 Pinout SQ3 Pinout

Quadruple Channel Configuration

NCS20164, NCV20164
Dual Channel Configuration
NCS20162, NCV20162 OUT 1 1 14 OUT 4

IN− 1 2 − − 13 IN− 4
OUT 1 1 8 VDD
3 + +
IN+ 1 12 IN+ 4
IN− 1 2 − 7 OUT 2
VDD 4 11 VSS
IN+ 1 3 + 6 IN− 2
−
IN+ 2 5 + + 10 IN+ 3
VSS 4 + 5 IN+ 2 − −
IN− 2 6 9 IN− 3

Micro8/MSOP8, SOIC−8 OUT 2 7 8 OUT 3

TSSOP−14, SOIC−14
Figure 1. Pin Connections

ORDERING INFORMATION
Device* Configuration Automotive Marking Package Shipping†
NCS20161SQ3T2G** Single No TBD SC70 3000 / Tape and Reel
NCS20161SN2T1G** TBD SOT23−5/TSOP−5 3000 / Tape and Reel
NCV20161SQ3T2G** Yes TBD SC70 3000 / Tape and Reel
NCV20161SN2T1G** TBD SOT23−5/TSOP−5 3000 / Tape and Reel
NCS20162DMR2G** Dual No TBD Micro8/MSOP8 4000 / Tape and Reel
NCS20162DR2G** 20162 SOIC−8 2500 / Tape and Reel
NCV20162DMR2G** Yes TBD Micro8/MSOP8 4000 / Tape and Reel
NCV20162DR2G** 20162 SOIC−8 2500 / Tape and Reel
NCS20164DR2G Quad No 20164G SOIC−14 2500 / Tape and Reel
NCS20164DTBR2G** TBD TSSOP−14 2500 / Tape and Reel
NCV20164DR2G** Yes 20164G SOIC−14 2500 / Tape and Reel
NCV20164DTBR2G** TBD TSSOP−14 2500 / Tape and Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NCV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
**In Development. Contact local sales office for more information.

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 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

ABSOLUTE MAXIMUM RATINGS (Note 1)

Rating Symbol Limit Unit
Supply Voltage (VDD – VSS) VS −0.3 to 6 V
Common Mode Input Voltage VI VSS−0.3 to VDD+0.3 V
Differential Input Voltage VID VDD – VSS+0.2 V
Maximum Input Current II ±10 mA
Maximum Output Current (Note 2) IO ±100 mA
Continuous Total Power Dissipation (Note 2) PD 200 mW
Maximum Junction Temperature TJ 150 °C
Storage Temperature Range TSTG −65 to 150 _C
Mounting Temperature (Infrared or Convection – 20 sec) Tmount 260 _C
ESD Capability (Note 3) Human Body Model HBM 2500 V
Charge Device Model CDM 1500
Latch−Up Current (Note 4) ILU 100 mA
Moisture Sensitivity Level (Note 5) MSL Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Refer to ELECTRICAL CHARACTERISTICS for Safe Operating Area.
2. Continuous short circuit operation to ground at elevated ambient temperature can result in exceeding the maximum allowed junction
temperature of 150°C. Output currents in excess of the maximum output current rating over the long term may adversely affect reliability.
Shorting output to either VDD or VSS will adversely affect reliability.
3. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per JEDEC standard Js−001−2017 (AEC−Q100−002)
ESD Charged Device Model tested per JEDEC standard JS−002−2014 (AEC−Q100−011)
4. Latch−up Current tested per JEDEC standard JESD78E (AEC−Q100−004)
5. Moisture Sensitivity Level tested per IPC/JEDEC standard: J−STD−020A

OPERATING RANGES
Parameter Symbol Min Max Unit
Operating Supply Voltage (VDD − VSS) VS 1.8 5.5 V
Differential Input Voltage VID − VS V
Common Mode Input Voltage Range VCM VSS – 0.1 VDD + 0.1 V
Ambient Temperature TA −40 125 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.

THERMAL CHARACTERISTICS (Note 6)

Package Junction−to−Ambient Junction−to−Case Top Junction−to−Board Unit
Thermal Resistance Thermal Resistance Thermal Resistance
JA JT JB
SOIC−8 205 32 116 °C/W
SOIC−14 138 8 100 °C/W
6. Thermal parameters are based on a 2s2p board following JESD51−7 (JEDEC).

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 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

ELECTRICAL CHARACTERISTICS AT VS = 1.8 V to 5.5 V

TA = 25°C; RL ≥ 10 k connected to mid−supply; VCM = VOUT = mid−supply unless otherwise noted.
Boldface limits apply over the specified temperature range, TA = −40°C to 125°C. (Note 7)
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Input Offset Voltage VOS VS = 5 V − ±0.3 ±2.1 mV
VS = 5 V − − ±2.6 mV
Offset Voltage Drift dVOS/dT VS = 5 V − ±1.5 − V/°C
Input Bias Current (Note 7) IIB − ±5 − pA
Input Offset Current (Note 7) IOS − ±5 − pA
Channel Separation DC − 100 − dB
Input Capacitance CIN − 4 − pF
Common Mode Rejection Ratio CMRR VS = 5.5 V, VCM = VSS − 0.1 V to VDD − 1.4 V 80 103 − dB
VS = 5.5 V, VCM = –0.1 V to 5.6 V 57 79 −
VS = 1.8 V, VCM = VSS − 0.1 V to VDD − 1.4 V − 91 −
VS = 1.8 V, VCM = –0.1 V to 1.9 V − 71 −
OUTPUT CHARACTERISTICS
Open Loop Voltage Gain AVOL VS = 1.8 V, VSS + 0.04 V < VO < VDD – 0.04 V, − 100 − dB
RL = 10 k
VS = 5.5 V, VSS + 0.05 V < VO < VDD – 0.05 V, 101 108 −
RL = 10 k
VS = 1.8 V, VSS + 0.06 V < VO < VDD – 0.06 V, − 97 −
RL = 2 k
VS = 5.5 V, VSS + 0.15 V < VO < VDD – 0.15 V, − 113 −
RL = 2 k
Short Circuit Current ISC Output sourcing current VS = 5 V − 40 − mA
Output sinking current, VS = 5 V − 50
Output Voltage Swing from VDD VDD − VS = 5.5 V, RL = 10 k − 3 20 mV
VOH
VS = 5.5 V, RL = 2 k − − 60

Output Voltage Swing from VSS VOL − VS = 5.5 V, RL = 10 k − 3 20 mV

VSS
VS = 5.5 V, RL = 2 k − − 60
AC CHARACTERISTICS
Unity Gain Bandwidth UGBW VS = 5 V, G = +1 − 8 − MHz
Slew Rate at Unity Gain SR VS = 5 V, G = +1 − 3.5 − V/s
Phase Margin m VS = 5 V, G = +1 − 52 − _
Gain Margin Am − 11 − dB
Settling Time to 0.1% tS VS = 5 V, VIN = 2 V step, G = +1, CL = 100 pF − 0.5 − μs
Settling Time to 0.01% tS VS = 5 V, VIN = 2 V step, G = +1, CL = 100 pF − 1 − μs
Overload Recovery Time tOR VS = 5 V, VIN x gain > VS − 1 − μs
Open Loop Output Impedance ZOL VS = 5 V, f = 10 MHz − 240 − 
NOISE CHARACTERISTICS
Total Harmonic Distortion plus Noise THD+n VS = 5.5 V, VCM = 2.5 V, VO = 1 VRMS, G = +1, − 0.0008 − %
f = 1 kHz
Input Referred Voltage Noise en VS = 5 V, f = 1 kHz − 20 − nV/√Hz
VS = 5 V, f = 10 kHz − 10 −
7. Performance guaranteed over the indicated operating temperature range by design and/or characterization.

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 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

ELECTRICAL CHARACTERISTICS AT VS = 1.8 V to 5.5 V (continued)

TA = 25°C; RL ≥ 10 k connected to mid−supply; VCM = VOUT = mid−supply unless otherwise noted.
Boldface limits apply over the specified temperature range, TA = −40°C to 125°C. (Note 7)
Parameter Symbol Conditions Min Typ Max Unit
NOISE CHARACTERISTICS
Input Referred Current Noise in f = 1 kHz − 20 − fA/√Hz
Input Voltage Noise, Peak−to−Peak En VS = 5 V, f = 0.1 Hz to 10 Hz − 5 − μVPP
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio PSRR VS = 1.8 V – 5.5 V, VCM = VSS − 8 80 μV/V
Power Supply Quiescent Current IQ Per channel, no load − 500 800 μA
7. Performance guaranteed over the indicated operating temperature range by design and/or characterization.

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 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

TYPICAL CHARACTERISTICS
(AT TA = 25°C, VCM = MID−SUPPLY, CL = 20 PF, RL = 10 K TO MID−SUPPLY, UNLESS OTHERWISE NOTED)

25 20
VS = 5 V VS = 5 V
18
20 105 Units 16 105 Units
NUMBER OF UNITS

NUMBER OF UNITS
14
15 12
10
10 8
6
5 4
2
0 0
−1.4 −1.0 −0.6 −0.2 0.2 0.6 1.0 1.4 −3 −2 −1 0 1 2 3 4
INPUT OFFSET VOLTAGE (mV) INPUT OFFSET VOLTAGE DRIFT (V/°C)
Figure 2. Input Offset Voltage Distribution Figure 3. Input Offset Voltage Drift Distribution

2000 2000

1500 1500
INPUT OFFSET VOLTAGE (V)

INPUT OFFSET VOLTAGE (V)

1000 1000

500 500

0 0

−500 −500

−1000 −1000
VS = 5.5 V VS = 1.8 V
−1500 −1500
5 typical units 5 typical units
−2000 −2000
−0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 −0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
COMMON MODE VOLTAGE (V) COMMON MODE VOLTAGE (V)
Figure 4. Input Offset Voltage vs. Common Figure 5. Input Offset Voltage vs. Common
Mode Voltage at 5.5 V Supply Mode Voltage at 1.8 V Supply

2000 2000

1500 1500
INPUT OFFSET VOLTAGE (V)

INPUT OFFSET VOLTAGE (V)

VS = 1.8 V
1000 1000
VCM = mid−supply
500 500

0 0

−500 −500
VS = 5.5 V
−1000 −1000
VCM = mid−supply
−1500 −1500
5 typical units
−2000 −2000
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 6. Input Offset Voltage vs. Temperature Figure 7. Input Offset Voltage vs. Temperature
at 5.5 V Supply at 1.8 V Supply

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 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

TYPICAL CHARACTERISTICS
(AT TA = 25°C, VCM = MID−SUPPLY, CL = 20 PF, RL = 10 K TO MID−SUPPLY, UNLESS OTHERWISE NOTED)

120 160

OPEN LOOP VOLTAGE GAIN (V/V)

VS = 5.5 V
100 140
Phase VS = 1.8 V
GAIN (dB) AND PHASE (°)

120
80
100
60
Gain 80
40
60
20
40
0 20
VS = 5 V
−20 0
10 100 1K 10K 100K 1M 10M −50 −25 0 25 50 75 100 125 150
FREQUENCY (Hz) TEMPERATURE (°C)
Figure 8. Open Loop Gain vs. Frequency Figure 9. Open Loop Gain vs. Temperature

30 600
IIB+
20 500 IIB−
IOS
INPUT CURRENT (pA)

10
400
0 VS = 5.5 V
GAIN (dB)

300
−10
200
−20
AV = 1
100
−30 AV = −1
AV = 10
−40 0
VS = 5.5 V
−50 −100
10 100 1K 10K 100K 1M 10M −50 −25 0 25 50 75 100 125 150
FREQUENCY (Hz) TEMPERATURE (°C)
Figure 10. Closed Loop Gain vs. Frequency Figure 11. Input Current vs. Temperature

0.8 0.7
OUTPUT VOLTAGE SWING TO VDD (V)

OUTPUT VOLTAGE SWING TO VSS (V)

TA = −40°C TA = −40°C
0.7 TA = 25°C 0.6 TA = 25°C
TA = 85°C TA = 85°C
0.6 TA = 125°C TA = 125°C
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.2

0.1 0.1
VS = 5.5 V VS = 5.5 V
0 0
0 10 20 30 40 0 10 20 30 40 50 60
OUTPUT CURRENT (mA) OUTPUT CURRENT (mA)
Figure 12. Output Voltage Swing High Figure 13. Output Voltage Swing Low

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 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

TYPICAL CHARACTERISTICS
(AT TA = 25°C, VCM = MID−SUPPLY, CL = 20 PF, RL = 10 K TO MID−SUPPLY, UNLESS OTHERWISE NOTED)

120 120
VIN = 0 dBm VIN = −10 dBm
100 100

80
80
60
CMRR (dB)

PSRR (dB)
60
40
40
20
20 VS = 1.8 V, PSRR+
0 VS = 1.8 V, PSRR−
0 VS = 1.8 V VS = 5.5 V, PSRR+
VS = 5.5 V −20
VS = 5.5 V, PSRR−
−20 −40
10 100 1K 10K 100K 1M 10M 10 1K 100K 10M
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 14. CMRR vs Frequency Figure 15. PSRR vs. Frequency

0 6

−1 5

−2
4
CMRR (V/V)

PSRR (V/V)

−3
3
−4
2
−5
VS = 5.5 V
−6 1
VCM = −0.1 V to 4.1 V VS = 1.8 V to 5.5 V
−7 0
−50 −25 0 25 50 75 100 125 150 −50 −25 0 25 50 75 100 125 150
TEMPERATURE (°C) TEMPERATURE (°C)
Figure 16. CMRR vs Temperature Figure 17. PSRR vs. Temperature

4 180
VS = 5 V
VOLTAGE NOISE DENSITY (nV/√Hz)

3 160

2 140
120
VOLTAGE (V)

1
100
0
80
−1
60
−2
40
VS = 5.5 V
−3 20
VS = 1.8 V
−4 0
10 100 1K 10K 100K 1M
TIME (1 s/div) FREQUENCY (Hz)
Figure 18. 0.1 Hz to 10 Hz Noise Figure 19. Voltage Noise Density vs.
Frequency

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 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

TYPICAL CHARACTERISTICS
(AT TA = 25°C, VCM = MID−SUPPLY, CL = 20 PF, RL = 10 K TO MID−SUPPLY, UNLESS OTHERWISE NOTED)

−90 0
VS = 5.5 V VS = 5.5 V
RL = 2.2 k to mid−supply −10
RL = 2.2 k to mid−supply
−95 VIN = 0.5 VRMS −20 VIN = 0.5 VRMS
AV = 1 AV = −1
−30
−100
THD+n (dB)

THD+n (dB)
−40
−105 −50
−60
−110
−70
−80
−115
−90
−120 −100
10 100 1K 10K 0.001 0.01 0.1 1
FREQUENCY (Hz) AMPLITUDE (VRMS)
Figure 20. THD+n vs. Frequency Figure 21. THD+n vs. Output Amplitude

540 510
VS = 5.5 V
530 500
QUIESCENT CURRENT (A)

QUIESCENT CURRENT (A)

520
490
510
480
500
470
490

480 460

470 450
−50 −25 0 25 50 75 100 125 150 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
TEMPERATURE (°C) SUPPLY VOLTAGE (V)
Figure 22. Quiescent Current Per Channel vs. Figure 23. Quiescent Current Per Channel vs.
Temperature Supply Voltage

0.08 3
0.06
2
0.04
0.02
1
VOLTAGE (V)

VOLTAGE (V)

0
Input Input
−0.02 Output 0
Output
−0.04
−1
−0.06
−0.08
VS = 5.5 V −2 VS = 5.5 V
−0.10
AV = 1 AV = 1
−0.12 −3

TIME (0.2 s/div) TIME (1 s/div)

Figure 24. Small Signal Step Response Figure 25. Large Signal Step Response

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 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

TYPICAL CHARACTERISTICS
(AT TA = 25°C, VCM = MID−SUPPLY, CL = 20 PF, RL = 10 K TO MID−SUPPLY, UNLESS OTHERWISE NOTED)

4 0.4 4
Input
3 VDD 0.3 3 Output

VOUT TO FINAL VALUE (V)

SUPPLY VOLTAGE (V)

2 0.2 2

VOLTAGE (V)
1 0.1 1
Output
0 0 0

−1 VDD = 2.75 V −0.1 −1

VSS = −2.75 V
−2 −0.2 −2
VSS
−3 −0.3 −3
−4 −0.4 −4

TIME (1 s/div) TIME (100 s/div)

Figure 26. Power Up Figure 27. No Phase Reversal

60 160
OPEN LOOP VOLTAGE GAIN (dB) 140
40
OUTPUT CURRENT (mA)

120
20
100
0
Sourcing
VS = 5 V 80
Sinking
−20
60
−40
40
−60 20 VS = 5.5 V
−80 0
−50 −25 0 25 50 75 100 125 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
TEMPERATURE (°C) OUTPUT VOLTAGE (V)
Figure 28. Short Circuit Current vs. Figure 29. Open Loop Gain vs. Output Voltage
Temperature

1.5 1 1.5 5
VOUT TO FINAL VALUE (mV)

VOUT TO FINAL VALUE (mV)

1.0 0 1.0 4
Input
INPUT VOLTAGE (V)

INPUT VOLTAGE (V)

Output Input
0.5 −1 0.5 3
Output

0 −2 0 2
VS = 5.5 V VS = 5.5 V
AV = −1 AV = −1
−0.5 −3 −0.5 1
CL = 100 pF CL = 100 pF
−1.0 −4 −1.0 0

−1.5 −5 −1.5 −1

TIME (500 ns/div) TIME (500 ns/div)

Figure 30. Output Low−to−High Settling Time Figure 31. Output High−to−Low Settling Time

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 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

TYPICAL CHARACTERISTICS
(AT TA = 25°C, VCM = MID−SUPPLY, CL = 20 PF, RL = 10 K TO MID−SUPPLY, UNLESS OTHERWISE NOTED)

100 300
90
250
80
70

IMPEDANCE ()
200
EMIRR (dB)

60
50 150
40
100
30
20
50
10 VS = 5 V
0 0
10M 100M 1G 10G 10K 100K 1M 10M
FREQUENCY (Hz) FREQUENCY (Hz)
Figure 32. EMIRR vs. Frequency Figure 33. Open Loop Output Impedance vs.
Frequency

0 60
VS = 5 V VS = 5 V
−20 50
PHASE MARGIN (°)
CROSSTALK (dB)

−40 40

−60 30

−80 20

−100 10

−120 0
10 100 1K 10K 100K 1M 10M 0 50 100 150 200 250
FREQUENCY (Hz) CAPACITIVE LOAD (pF)
Figure 34. Channel Separation vs. Frequency Figure 35. Phase Margin vs. Capacitive Load

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 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

TYPICAL CHARACTERISTICS
(AT TA = 25°C, VCM = MID−SUPPLY, CL = 20 PF, RL = 10 K TO MID−SUPPLY, UNLESS OTHERWISE NOTED)

50 50
VS = 5.5 V VS = 5.5 V
45 45
AV = 1 AV = −1
40 40
35 35
OVERSHOOT (%)

OVERSHOOT (%)
30 30
25 25
20 20
15 15
10 Rising Edge 10 Rising Edge
Falling Edge 5 Falling Edge
5
0 0
0 50 100 150 200 250 300 0 50 100 150 200 250 300
CAPACITIVE LOAD (pF) CAPACITIVE LOAD (pF)
Figure 36. Overshoot vs. Capacitive Load for Figure 37. Overshoot vs. Capacitive Load for
AV = 1 AV = −1

1.5 3.0
VS = 5.5 V VS = 5.5 V
1.0 2.5
AV = −10 AV = −10
0.5 2.0

0 1.5
VOLTAGE (V)

VOLTAGE (V)

−0.5 1.0

−1.0 0.5

−1.5 0

−2.0 −0.5
Input Input
−2.5 −1.0 Output
Output
−3.0 −1.5

TIME (1 s/div) TIME (1 s/div)

Figure 38. Negative Overvoltage Recovery Figure 39. Positive Overvoltage Recovery

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 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

APPLICATION INFORMATION

The NCS20161 family of operational amplifiers is events (within the limits specified) trigger the protection
manufactured using onsemi’s CMOS process. Products in structure so the operational amplifier is not damaged.
this class are general purpose, unity−gain stable amplifiers In order to safe guard against excessive voltages across the
and include single, dual and quad configurations. op amp’s inputs, external clamp diodes can be used as shown
in Figure 40. The four low−drop fast diodes (Schottky
Rail−to−Rail Input with No Phase Reversal preferred) are used in parallel with the internal structure to
The NCS2016x operational amplifiers are designed to divert the excessive energy to the supply rails where it can
prevent phase reversal or any similar issues when the input be easily dissipated or absorbed by the supply capacitors.
pins potential exceed the supply voltages by up to 100 mV. The application designer should also take into account that
The input stage of the NCS20161 family consists of two these external diodes add leakage currents and parasitic
differential CMOS input stages connected in parallel: the capacitance that must be considered when evaluating the
first is constructed using paired PMOS devices and it end−to−end performance of the amplifier stage.
operates at low common mode input voltages (VCM); the
second stage is build using paired NMOS devices to operate Limiting Input Currents
at high VCM. The transition between the two input stages In order to prevent damage/ improper operation of these
occurs at a common mode input voltage of approximately amplifiers, the application circuit must limit the current
VDD−1.3V. flowing through the input pins. A possible solution is
presented in Figure 40 by means of the two added series
Limiting Input Voltages resistors. The minimum value for the input resistors should
In order to prevent damage and/or improper operation of be calculated using Ohm’s Law so they limit the input pin
these amplifiers, the application circuit must never expose current to less than the absolute maximum values specified.
the input pins to voltages or currents higher than the The application designer should take into account that these
Absolute Maximum Ratings. resistors also add parasitic inductance that must be
The internal ESD structure includes special diodes to considered when evaluating performance.
protect the input stages while maintaining a low input bias Combining the current limiting resistors with the voltage
current (IIB). The input protection circuitry clamp the inputs limiting diodes creates a solid input protection structure, that
when the signals applied exceed more than one diode drop can be used to insure reliable operation of the amplifier even
below VSS or one diode drop above VDD. Very fast ESD in the hardest conditions.
VDD VDD

VDD

IN+ + IN+ + IN+ +

IN− − IN− − IN− −

VSS

VSS VSS
Figure 40. Typical Protection of the Operational Amplifier Inputs

Rail−to−Rail Output ♦ degraded phase margin

The maximum output voltage swing is dependent of the ♦ lowered bandwidth
particular output load. According to the specification, the ♦ gain peaking of the frequency response
output can reach within 20 mV of either supply rail when ♦ overshoot and ringing of the step response
load resistance is 10 k. The VOL and VOH graphs shows the While the NCS2016x series op amps are capable of driving
load drive capabilities of the part under different conditions. capacitive loads up to 100 pF, adding a small resistor in
Output current is internally limited to the typical values series to the output (RISO in Figure 41) will increase the
listed in the Electrical Characteristics table. phase margin. This leads to higher stability by making the
Capacitive Loads equivalent load more resistive at high frequencies.
Driving capacitive loads can create stability problems for
voltage feedback op amps, as it is a known possible cause for:

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 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

VDD The unity gain buffer is recommended here (Figure 42).

The ADC’s internal sampling capacitor requires a buffer
front−end to recharge it faster than the sampling time, and
IN+ + RISO this problem is even worse if more channels are sampled by
the same ADC using an internal multiplexer. In order to
IN− −
achieve a settling time shorter than the multiplexed
CL sampling rate, an RC stage is recommended between the
buffer and the ADC input. The RISO resistor’s value should
VSS
be low enough to charge the capacitor quickly, but at the
same time large enough to isolate the capacitive load from
Figure 41. Driving Capacitive Loads the amplifier output to preserve phase margin. When
transients are generated by the sensor’s output, first the two
Simulating the application with onsemi’s Spice model is
amplifier inputs see a high differential voltage between
a good starting point for selecting the isolation resistor’s
them, then the output settles and brings the inverting input
value. Bench testing the frequency and step response can be
back to the correct voltage.
used to fine−tune the value according to the desired
Let us take an example of a 0.1 V to 4 V sensor signal. To
characteristic.
successfully accommodate it, the differential input range of
Unity Gain Bandwidth the NCS2016x is close to the supply range and the output
Interfacing a high impedance sensor’s output to will match the input. The differential input voltage is limited
a relatively low−impedance ADC input usually requires an only by the ESD protection structure and not by
intermediate stage to avoid unwanted interference of the two back−to−back diodes between inputs.
devices, and this stage needs to have a high input impedance,
a low output impedance, and high output current.
VDD
ADC

sensor + RISO

CL Csampling

VSS

Figure 42. Unity Gain Buffer Stage for Sampling with ADC

Power Supply Bypassing crosstalk, increased current consumption, or add noise to the
For AC, the power supply pins (VDD and VSS for split supply rails.
supply, VDD for single supply) should be bypassed locally
with a quality capacitor in the range of 100 nF as close as VDD VDD
possible to the amplifier supply pins. Ceramic capacitors are
recommended for their low ESR and good high frequency
response. + +
For DC, a bulk capacitor in the range of 1 μF placed within
inches distance from the op amp can provide the additional − −
current needed to drive higher loads.

Unused Operational Amplifiers VSS

Occasionally not all the op amp channels offered in the
quad packages are needed for a specific application. They
can be connected as “buffering ground” as shown in Figure 43. Unused Operational Amplifiers
Figure 43, a solution that does not need any extra parts.
Connecting them differently (inputs split to rails, left
floating, etc.) can sometimes cause unwanted oscillation,

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 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

PCB Surface Leakage PCB Routing Recommendations

If it is critical to obtain the lowest input bias current, the In addition to amplifying the useful signal, op amps can
PCB’s surface leakage should be considered. Dry also pick the high frequency noise together with the signal
environment surface current increases further when the and amplify it accordingly, if the design allows it. In order
board is exposed to humidity, dust or chemical to reach the values specified in the Electrical Characteristics
contamination. For harsh environment conditions, tables and to avoid high frequency interference issues, it is
protecting the entire board surface (with all the exposed recommended that the PCB layout follows the basic
metal pins and soldered areas) is advised. Conformal coating guidelines listed below:
or potting the board in resin proves effective in most cases. ♦ A dedicated layer for the ground plane should be
An alternate solution for reduced leakage is the use of used whenever possible and all supply decoupling
guard rings around sensitive pins and pads. A proper guard capacitors should connect to it by vias
ring should have low impedance and be biased to the same ♦ Copper traces should be as short as possible
voltage as the sensitive pin so that no current flows in ♦ High current paths should not be shared by small
between them. signal or low current traces
For an inverting amplifier, the non−inverting input is ♦ If present, switching power supply blocks should be
usually connected to supply’s ground (or virtual ground at kept away from the analog sensitive areas to avoid
half the rail voltage in single supply applications) so it can potential conducted and radiated noise issues
represent a good ring solution. When routing the PCB traces, ♦ When different circuit taxonomies share the same
create a closed perimeter around the inverting input pad (which board, it is recommended to keep separated the
carries the signal) and connect it to the non−inverting input. power areas, the digital areas and the small signal
For a non−inverting amplifier, use a similarly shaped analog areas. Small−signal components in the signal
(rectangle or circle) copper trace around the non−inverting path should be placed as close as possible to the
input pad (which carries the signal) and connect it to the amplifier input pins
inverting input pin, which presents a much lower impedance ♦ Metal shielding the sensitive areas and the
thanks to the feedback network. “offender” blocks may be required in some cases

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NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

PACKAGE DIMENSIONS

SC−88A (SC−70−5/SOT−353)
CASE 419A−02
ISSUE M

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 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

PACKAGE DIMENSIONS

SOIC−8 NB
CASE 751−07
ISSUE AK NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS INCHES
G
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
C N X 45 _ B 3.80 4.00 0.150 0.157
SEATING C 1.35 1.75 0.053 0.069
PLANE D 0.33 0.51 0.013 0.020
−Z− G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
0.10 (0.004) J 0.19 0.25 0.007 0.010
H M J K 0.40 1.27 0.016 0.050
D
M 0_ 8_ 0 _ 8 _
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
0.25 (0.010) M Z Y S X S
STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
4. GATE 2
SOLDERING FOOTPRINT* 5. DRAIN 2
6. DRAIN 2
7. DRAIN 1
8. DRAIN 1
1.52
0.060

7.0 4.0
0.275 0.155

0.6 1.270
0.024 0.050

SCALE 6:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy

and soldering details, please download the
onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.

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18
 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

PACKAGE DIMENSIONS

TSOP−5
CASE 483
ISSUE N

NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
NOTE 5 D 5X Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
0.20 C A B 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH
2X 0.10 T THICKNESS. MINIMUM LEAD THICKNESS IS THE
MINIMUM THICKNESS OF BASE MATERIAL.
M 4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
5 4 FLASH, PROTRUSIONS, OR GATE BURRS. MOLD
2X 0.20 T S
B FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT
1 2 3 EXCEED 0.15 PER SIDE. DIMENSION A.
K 5. OPTIONAL CONSTRUCTION: AN ADDITIONAL
B TRIMMED LEAD IS ALLOWED IN THIS LOCATION.
G DETAIL Z
TRIMMED LEAD NOT TO EXTEND MORE THAN 0.2
FROM BODY.
A A
MILLIMETERS
TOP VIEW DIM MIN MAX
A 2.85 3.15
B 1.35 1.65
DETAIL Z C 0.90 1.10
J D 0.25 0.50
G 0.95 BSC
C H 0.01 0.10
0.05 J 0.10 0.26
H SEATING K 0.20 0.60
C PLANE
END VIEW M 0_ 10 _
SIDE VIEW S 2.50 3.00

SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037

2.4
0.094

1.0
0.039

0.7
0.028 SCALE 10:1 ǒinches
mm Ǔ

*For additional information on our Pb−Free strategy

and soldering details, please download the
onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.

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19
NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

PACKAGE DIMENSIONS

Micro8
CASE 846A−02
ISSUE K

*For additional information on our Pb−Free strategy

and soldering details, please download the
onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.

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 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

PACKAGE DIMENSIONS

TSSOP−14 WB
CASE 948G
ISSUE C

14X K REF NOTES:

1. DIMENSIONING AND TOLERANCING PER
0.10 (0.004) M T U S V S ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
0.15 (0.006) T U S 3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
N EXCEED 0.15 (0.006) PER SIDE.
0.25 (0.010)
14 8 4. DIMENSION B DOES NOT INCLUDE
2X L/2 INTERLEAD FLASH OR PROTRUSION.
M INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
L B 5. DIMENSION K DOES NOT INCLUDE DAMBAR
−U− N PROTRUSION. ALLOWABLE DAMBAR
PIN 1 PROTRUSION SHALL BE 0.08 (0.003) TOTAL
IDENT. F IN EXCESS OF THE K DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 7
DETAIL E 6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
0.15 (0.006) T U S
A K
MILLIMETERS INCHES

ÉÉÉ
ÇÇÇ
−V− K1 DIM MIN MAX MIN MAX
A 4.90 5.10 0.193 0.200

ÇÇÇ
ÉÉÉ
B 4.30 4.50 0.169 0.177
J J1 C −−− 1.20 −−− 0.047
D 0.05 0.15 0.002 0.006
F 0.50 0.75 0.020 0.030
SECTION N−N G 0.65 BSC 0.026 BSC
H 0.50 0.60 0.020 0.024
J 0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
C −W− K 0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
0.10 (0.004) L 6.40 BSC 0.252 BSC
M 0_ 8_ 0_ 8_
−T− SEATING D G H DETAIL E
PLANE GENERIC
MARKING DIAGRAM*

SOLDERING FOOTPRINT

7.06

0.65
PITCH

14X 14X
0.36
1.26
DIMENSIONS: MILLIMETERS

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 NCS20161, NCS20162, NCS20164, NCV20161, NCV20162, NCV20164

PACKAGE DIMENSIONS

SOIC−14 NB
CASE 751A−03
D A
ISSUE L NOTES:
1. DIMENSIONING AND TOLERANCING PER
B ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
14 8 3. DIMENSION b DOES NOT INCLUDE DAMBAR
A3 PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
H E 4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
L 5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
1 7 DETAIL A
MILLIMETERS INCHES
0.25 M B M 13X b DIM MIN MAX MIN MAX
A 1.35 1.75 0.054 0.068
0.25 M C A S B S A1 0.10 0.25 0.004 0.010
A3 0.19 0.25 0.008 0.010
DETAIL A b 0.35 0.49 0.014 0.019
h
A X 45 _
D 8.55 8.75 0.337 0.344
E 3.80 4.00 0.150 0.157
e 1.27 BSC 0.050 BSC
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.019
0.10 L 0.40 1.25 0.016 0.049
e A1 M
SEATING M 0_ 7_ 0_ 7_
C PLANE

SOLDERING FOOTPRINT*
6.50 14X
1.18
1

1.27
PITCH

14X
0.58

DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy
and soldering details, please download the
onsemi Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.

onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.
A listing of onsemi’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. onsemi reserves the right to make changes at any time to any
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information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use
of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products
and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information
provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/or specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license
under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems
or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should
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and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
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