PCA9516A

PCA9516A
5-channel I2C-bus hub

Rev. 03 — 23 April 2009 Product data sheet
1. General description
The PCA9516A is a CMOS integrated circuit intended for application in I2C-bus and
SMBus systems.
While retaining all the operating modes and features of the I2C-bus system, it permits
extension of the I2C-bus by buffering both the data (SDAn) and the clock (SCLn) lines,
thus enabling five buses of 400 pF.
The I2C-bus capacitance limit of 400 pF restricts the number of devices and bus length.
Using the PCA9516A enables the system designer to divide the bus into five segments off
of a hub where any segment-to-segment transition sees only one repeater delay.
It can also be used to run different buses at 5 V and 3.3 V or 400 kHz and 100 kHz buses
where the 100 kHz bus is isolated when 400 kHz operation of the other bus is required.
Two or more PCA9516As cannot be put in series. The PCA9516A design does not
allow this configuration. Since there is no direction pin, slightly different ‘legal’ low voltage
levels are used to avoid lock-up conditions between the input and the output of each
repeater in the hub. A ‘regular LOW’ applied at the input of a PCA9516A will be
propagated as a ‘buffered LOW’ with a slightly higher value on all the enabled outputs.
When this ‘buffered LOW’ is applied to another PCA9515A, PCA9516A, or PCA9518A in
series, the second PCA9515A, PCA9516A, or PCA9518A will not recognize it as a
‘regular LOW’ and will not propagate it as a ‘buffered LOW’ again. The
PCA9510A/9511A/9513A/9514A and PCA9512A cannot be used in series with the
PCA9515A, PCA9516A, or PCA9518A, but can be used in series with themselves since
they use shifting instead of static offsets to avoid lock-up conditions.
2. Features
n 5 channel, bidirectional buffer
n I2C-bus and SMBus compatible
n Active HIGH individual repeater enable input
n Open-drain input/outputs
n Lock-up free operation
n Supports arbitration and clock stretching across the repeater
n Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters
n Powered-off high-impedance I2C-bus pins
n Operating supply voltage range of 2.3 V to 3.6 V
n 5.5 V tolerant I2C-bus and enable pins
NXP Semiconductors PCA9516A
n 0 Hz to 400 kHz clock frequency1

n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
n Packages offered: SO16 and TSSOP16
3. Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
PCA9516AD SO16 plastic small outline package; 16 leads; SOT109-1
body width 3.9 mm
PCA9516APW TSSOP16 plastic thin shrink small outline package; 16 leads; SOT403-1
body width 4.4 mm
3.1 Ordering options

Table 2. Ordering options
Type number Topside mark Temperature range
PCA9516AD PCA9516AD Tamb = −40 °C to +85 °C
PCA9516APW PA9516A Tamb = −40 °C to +85 °C
1. The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.
PCA9516A_3 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 03 — 23 April 2009 2 of 19

4. Block diagram
VCC
PCA9516A
SCL0 BUFFER
BUFFER SCL4
HUB
SCL1 BUFFER
LOGIC
BUFFER SCL3
SCL2 BUFFER
SDA0 BUFFER
BUFFER SDA4
HUB
SDA1 BUFFER
LOGIC
BUFFER SDA3
SDA2 BUFFER
EN1 EN4
EN2 EN3
002aae616
GND
Fig 1. Block diagram
A more detailed view of Figure 1 buffer is shown in Figure 2.
to output
data
in
inc
enable 002aac531
Fig 2. Buffer detail
The output pull-down of each internal buffer is set for approximately 0.5 V, while the input
threshold of each internal buffer is set about 0.07 V lower, when the output is internally
driven LOW. This prevents a lock-up condition from occurring.

5. Pinning information
5.1 Pinning
SCL0 1 16 VCC
SDA0 2 15 EN4
SCL1 3 14 SDA4
SCL0 1 16 VCC
SDA1 4 13 SCL4 SDA0 2 15 EN4
PCA9516AD SCL1 3 14 SDA4
EN1 5 12 EN3
SDA1 4 13 SCL4
PCA9516APW
SCL2 6 11 SDA3 EN1 5 12 EN3
SCL2 6 11 SDA3
SDA2 7 10 SCL3
SDA2 7 10 SCL3
GND 8 9 EN2 GND 8 9 EN2
002aae614 002aae615
Fig 3. Pin configuration for SO16 Fig 4. Pin configuration for TSSOP16
5.2 Pin description

Table 3. Pin description
Symbol Pin Description
SCL0 1 serial clock bus 0
SDA0 2 serial data bus 0
EN1 5 active HIGH bus 1 enable input
GND 8 supply ground
VCC 16 supply power

6. Functional description
The PCA9516A is a five-way hub repeater, which enables I2C-bus and similar bus
systems to be expanded with only one repeater delay and no functional degradation of
system performance.
The PCA9516A contains five bidirectional, open-drain buffers specifically designed to

support the standard low-level-contention arbitration of the I2C-bus. Except during
arbitration or clock stretching, the PCA9516A acts like five pairs of non-inverting,
open-drain buffers, one for SDA and one for SCL. Refer to Figure 1 “Block diagram”.
6.1 Enable
The enable pins EN1 through EN4 are active HIGH and have internal pull-up resistors.
Each enable pin ENn controls its associated SDAn and SCLn ports. When LOW, the ENn
pin blocks the inputs from SDAn and SCLn as well as disabling the output drivers on the
SDAn and SCLn pins. The enable pins should only change state when both the global bus
and the local port are in an idle state to prevent system failures.
The active HIGH enable pins allow the use of open-drain drivers which can be wire-ORed
to create a distributed enable where either centralized control signal (master) or spoke
signal (submaster) can enable the channel when it is idle.
6.2 I2C-bus systems

As with the standard I2C-bus system, pull-up resistors are required to provide the logic
HIGH levels on the buffered bus. (Standard open-collector configuration of the I2C-bus.)
The size of these pull-up resistors depends on the system, but each side of the repeater
must have a pull-up resistor. This part is designed to work with Standard-mode and
Fast-mode I2C-bus devices in addition to SMBus devices. Standard-mode I2C-bus devices
only specify 3 mA output drive; this limits the termination current to 3 mA in a generic
I2C-bus system where Standard-mode devices and multiple masters are possible. Please
see application note AN255, “I2C/SMBus Repeaters, Hubs and Expanders” for additional
information on sizing resistors and precautions when using more than one
PCA9515A/PCA9516A in a system or using the PCA9515A/PCA9516A in conjunction
with the P82B96.
7. Application design-in information

A typical application is shown in Figure 5. In this example, the system master is running
on a 3.3 V I2C-bus while the slave is connected to a 5 V bus. All buses run at 100 kHz
unless slave 3 is isolated, and then the master bus and slave 1 and slave 2 can run at
400 kHz.
Any segment of the hub can talk to any other segment of the hub. Bus masters and slaves
can be located on all five segments with 400 pF load allowed on each segment.
Unused ports should be isolated by holding the enable pin (ENn) to GND and/or pulling
SDAn/SCLn pins to VCC through appropriately sized resistors. The primary bus master is
normally connected to SDA0/SCL0. If the SDA0/SCL0 port is not used, the pins need to
be pulled to VCC through appropriately sized resistors.

The PCA9516A is 5.5 V tolerant so it does not require any additional circuitry to translate
between the different bus voltages.
When one side of the PCA9516A is pulled LOW by a device on the I2C-bus, a CMOS
hysteresis type input detects the falling edge and causes an internal driver on the other
side to turn on, thus causing the other side to also go LOW. The side driven LOW by the
PCA9516A will typically be at VOL = 0.5 V.
3.3 V 5V
VCC
SDA SDA0 SDA1 SDA SLAVE 1
SCL SCL0 SCL1 SCL 400 kHz
BUS 3.3 V
MASTER
EN1
EN2
EN3
SDA2 SDA SLAVE 2
400 kHz EN4
SCL2 SCL 400 kHz
5V
PCA9516A
SDA3 SDA SLAVE 3

SCL3 SCL 100 kHz
3.3 V or 5 V
SDA4
SCL4
002aae617
Fig 5. Typical application
In order to illustrate what would be seen in a typical application, refer to Figure 6 and
Figure 7. If the bus master in Figure 5 were to write to the slave through the PCA9516A,
we would see the waveform shown in Figure 6 on Bus 0. This looks like a normal I2C-bus
transmission until the falling edge of the 8th clock pulse. At that point, the master releases
the data line (SDA) while the slave pulls it LOW through the PCA9516A. Because the VOL
of the PCA9516A is typically around 0.5 V, a step in the SDA will be seen. After the master
has transmitted the 9th clock pulse, the slave releases the data line.
On the Bus 1 side of the PCA9516A, the clock and data lines would have a positive offset
from ground equal to the VOL of the PCA9516A. After the 8th clock pulse, the data line will
be pulled to the VOL of the slave device that is very close to ground in our example.
It is important to note that any arbitration or clock stretching events on Bus 1 require that
the VOL of the devices on Bus 1 be 70 mV below the VOL of the PCA9516A (see VOL−VILc
in Section 9 “Static characteristics”) to be recognized by the PCA9516A and then
transmitted to Bus 0.

9th clock pulse
SCL
VOL of PCA9516A
SDA
VOL of master
002aae618
Fig 6. Bus 0 waveform
9th clock pulse
SCL
SDA VOL of PCA9516A
VOL of slave 002aae619
Fig 7. Bus 1 waveform
8. Limiting values
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages with respect to GND.
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +7 V
Vbus voltage range I2C-bus SCLn or SDAn −0.5 +7 V
I DC current any pin - 50 mA
Ptot total power dissipation - 300 mW
Tstg storage temperature −55 +125 °C
Tamb ambient temperature operating −40 +85 °C

9. Static characteristics
Table 5. Static characteristics (VCC = 3.0 V to 3.6 V)
VCC = 3.0 V to 3.6 V[1]; GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Symbol Parameter Conditions Min Typ[2] Max Unit
Supplies
VCC supply voltage 3.0 - 3.6 V
ICCH HIGH-level supply current both channels HIGH; - 2.1 5 mA
VCC = 3.6 V;
SDAn = SCLn = VCC
ICCL LOW-level supply current both channels LOW; - 4.7 10 mA
VCC = 3.6 V; one SDAn and
one SCLn = GND, other
SDAn and SCLn open
ICCLc contention LOW-level supply current VCC = 3.6 V; - 4.0 10 mA
SDAn = SCLn = GND
Input SCLn; input/output SDAn
VIH HIGH-level input voltage 0.7VCC - 5.5 V
VIL LOW-level input voltage [3] −0.5 - +0.3VCC V
VILc contention LOW-level input voltage [3] −0.5 - +0.4 V
VIK input clamping voltage II = −18 mA - - −1.2 V
ILI input leakage current VI = 3.6 V −1 - +1 µA
IIL LOW-level input current SDAn, SCLn; VI = 0.2 V - - 5 µA
VOL LOW-level output voltage IOL = 0 mA or 6 mA 0.47 0.52 0.6 V
VOL−VILc difference between LOW-level guaranteed by design - - 70 mV
output and LOW-level input voltage
contention
Ci input capacitance VI = 3 V or 0 V - 6 10 pF
Enable inputs EN1 to EN4
VIL LOW-level input voltage −0.5 - +0.8 V
VIH HIGH-level input voltage 2.0 - 5.5 V
IIL LOW-level input current EN1 to EN4; VI = 0.2 V - −12 −30 µA
ILI input leakage current −1 - +1 µA
[1] For operation between published voltage ranges, refer to worst case parameter in both ranges.
[2] Typical value taken at 3.3 V and 25 °C.
[3] VIL specification is for the first LOW level seen by the SDAn/SCLn lines. VILc is for the second and subsequent LOW levels seen by the
SDAn/SCLn lines.

Table 6. Static characteristics (VCC = 2.3 V to 2.7 V)

VCC = 2.3 V to 2.7 V[1]; GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Supplies
VCC supply voltage 2.3 - 2.7 V
ICCH HIGH-level supply current both channels HIGH; - 2.1 5 mA
VCC = 2.7 V;
SDAn = SCLn = VCC
ICCL LOW-level supply current both channels LOW; - 4.6 10 mA
VCC = 2.7 V; one SDAn and
one SCLn = GND, other
SDAn and SCLn open
ICCLc contention LOW-level supply current VCC = 2.7 V; - 3.9 10 mA
SDAn = SCLn = GND
Input SCLn; input/output SDAn
VIH HIGH-level input voltage 0.7VCC - 5.5 V
VIL LOW-level input voltage [3] −0.5 - +0.3VCC V
VILc contention LOW-level input voltage [3] −0.5 - +0.4 V
VIK input clamping voltage II = −18 mA - - −1.2 V
ILI input leakage current VI = 2.7 V −1 - +1 µA
IIL LOW-level input current SDAn, SCLn; VI = 0.2 V - - 5 µA
VOL LOW-level output voltage IOL = 0 mA or 6 mA 0.47 0.52 0.6 V
VOL−VILc difference between LOW-level guaranteed by design - - 70 mV
output and LOW-level input voltage
contention
Enable inputs EN1 to EN4
VIL LOW-level input voltage −0.5 - +0.8 V
VIH HIGH-level input voltage 1.5 - 5.5 V
IIL LOW-level input current EN1 to EN4; VI = 0.2 V - −10 −30 µA
ILI input leakage current −1 - +1 µA
[1] For operation between published voltage ranges, refer to worst case parameter in both ranges.
[3] VIL specification is for the first LOW level seen by the SDAn/SCLn lines. VILc is for the second and subsequent LOW levels seen by the
SDAn/SCLn lines.

10. Dynamic characteristics

Table 7. Dynamic characteristics (VCC = 2.3 V to 2.7 V)
VCC = 2.3 V to 2.7 V; GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
tPHL HIGH to LOW propagation delay Figure 8 45 93 150 ns
tPLH LOW to HIGH propagation delay Figure 8 [2] 33 90 135 ns
tTHL HIGH to LOW output transition time Figure 8 - 60 - ns
tTLH LOW to HIGH output transition time Figure 8 [2] - 131 - ns
tsu set-up time ENn to START condition 100 - - ns
th hold time ENn after STOP condition 130 - - ns

[2] Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times.
Table 8. Dynamic characteristics (VCC = 3.0 V to 3.6 V)

VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
tPHL HIGH to LOW propagation delay Figure 8 45 75 120 ns
tPLH LOW to HIGH propagation delay Figure 8 [2] 33 60 83 ns
tTHL HIGH to LOW output transition time Figure 8 - 47 - ns
tTLH LOW to HIGH output transition time Figure 8 [2] - 130 - ns
tsu set-up time ENn to START condition 100 - - ns
th hold time ENn after STOP condition 100 - - ns

[2] Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times.
3.3 V
input 1.5 V 1.5 V
0.1 V
tPHL tPLH
3.3 V
80 % 80 %
output 1.5 V 1.5 V
20 % 20 %
VOL
tTHL tTLH
002aad478
Fig 8. Propagation delay and transition times

11. Test information
VCC
VCC
RL
VI VO
PULSE
DUT
GENERATOR
RT CL
002aad479
RL = load resistor; 1.35 kΩ.

CL = load capacitance includes jig and probe capacitance; 50 pF.
RT = termination resistance should be equal to Zo of pulse generators.
Fig 9. Test circuit for open-drain outputs

12. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
D E A
X
y HE v M A
16 9
Q
A2
(A 3) A
A1
pin 1 index
θ
Lp
1 8 L
e w M detail X
bp
0 2.5 5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ
max.
0.25 1.45 0.49 0.25 10.0 4.0 6.2 1.0 0.7 0.7
mm 1.75 0.25 1.27 1.05 0.25 0.25 0.1 o
0.10 1.25 0.36 0.19 9.8 3.8 5.8 0.4 0.6 0.3 8
o
0.010 0.057 0.019 0.0100 0.39 0.16 0.244 0.039 0.028 0.028 0
inches 0.069 0.01 0.05 0.041 0.01 0.01 0.004
0.004 0.049 0.014 0.0075 0.38 0.15 0.228 0.016 0.020 0.012
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
99-12-27
SOT109-1 076E07 MS-012
03-02-19
Fig 10. Package outline SOT109-1 (SO16)


TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
D E A
X
y HE v M A
16 9
Q
A2 (A 3)
A
A1
pin 1 index
θ
Lp
L
1 8
detail X
w M
e bp
0 2.5 5 mm
scale
DIMENSIONS (mm are the original dimensions)

A
UNIT A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ
max.
o
0.15 0.95 0.30 0.2 5.1 4.5 6.6 0.75 0.4 0.40 8
mm 1.1 0.25 0.65 1 0.2 0.13 0.1 o
0.05 0.80 0.19 0.1 4.9 4.3 6.2 0.50 0.3 0.06 0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION
99-12-27
SOT403-1 MO-153
03-02-18
Fig 11. Package outline SOT403-1 (TSSOP16)


13. Soldering of SMD packages

This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
13.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
13.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
• Board specifications, including the board finish, solder masks and vias
• Package footprints, including solder thieves and orientation
• The moisture sensitivity level of the packages
• Package placement
• Inspection and repair
• Lead-free soldering versus SnPb soldering
13.3 Wave soldering

Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities

13.4 Reflow soldering

Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 12) than a SnPb process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 9 and 10
Table 9. SnPb eutectic process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 ≥ 350
< 2.5 235 220
≥ 2.5 220 220
Table 10. Lead-free process (from J-STD-020C)

Package thickness (mm) Package reflow temperature (°C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all

times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 12.

maximum peak temperature

temperature = MSL limit, damage level
minimum peak temperature

= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level

Fig 12. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365

“Surface mount reflow soldering description”.
14. Abbreviations
Table 11. Abbreviations
Acronym Description
CDM Charged-Device Model
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
I2C-bus Inter-Integrated Circuit bus
MM Machine Model
RC Resistor-Capacitor network
SMBus System Management Bus

15. Revision history

Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
PCA9516A_3 20090423 Product data sheet - PCA9516A_2
Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of
NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• Section 1 “General description”, 5th paragraph: referenced part type numbers changed from
“PCA951x” to “PCA951xA”
• Added soldering information
• Added Section 14 “Abbreviations”
PCA9516A_2 20040929 Product data sheet - PCA9516A_1
(9397 750 14108)
PCA9516A_1 20040528 Product data sheet - -
(9397 750 13238)

16. Legal information
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Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
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therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
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representations or warranties as to the accuracy or completeness of representation or warranty that such applications will be suitable for the
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use of such information. Limiting values — Stress above one or more limiting values (as defined in
Short data sheet — A short data sheet is an extract from a full data sheet the Absolute Maximum Ratings System of IEC 60134) may cause permanent
with the same product type number(s) and title. A short data sheet is intended damage to the device. Limiting values are stress ratings only and operation of
for quick reference only and should not be relied upon to contain detailed and the device at these or any other conditions above those given in the
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17. Contact information

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com

18. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1
2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2
3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
6.1 Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2 I2C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 5
7 Application design-in information . . . . . . . . . . 5
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
10 Dynamic characteristics . . . . . . . . . . . . . . . . . 10
11 Test information . . . . . . . . . . . . . . . . . . . . . . . . 11
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Soldering of SMD packages . . . . . . . . . . . . . . 14
13.1 Introduction to soldering . . . . . . . . . . . . . . . . . 14
13.2 Wave and reflow soldering . . . . . . . . . . . . . . . 14
13.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 14
13.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 15
14 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18
16.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16.3 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
17 Contact information. . . . . . . . . . . . . . . . . . . . . 18
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 23 April 2009
Document identifier: PCA9516A_3

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PCA9516A

5-channel I2C-bus hub

n 0 Hz to 400 kHz clock frequency1

3.1 Ordering options

PCA9516A_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 23 April 2009 2 of 19

Fig 1. Block diagram

A more detailed view of Figure 1 buffer is shown in Figure 2.

Fig 2. Buffer detail

PCA9516A_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 23 April 2009 3 of 19

5.2 Pin description

PCA9516A_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 23 April 2009 4 of 19

The PCA9516A contains five bidirectional, open-drain buffers specifically designed to

6.2 I2C-bus systems

7. Application design-in information

PCA9516A_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 23 April 2009 5 of 19

SDA3 SDA SLAVE 3

Fig 5. Typical application

PCA9516A_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 23 April 2009 6 of 19

9th clock pulse

Fig 6. Bus 0 waveform

9th clock pulse

SDA VOL of PCA9516A

VOL of slave 002aae619

Fig 7. Bus 1 waveform

PCA9516A_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 23 April 2009 7 of 19

PCA9516A_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 23 April 2009 8 of 19

Table 6. Static characteristics (VCC = 2.3 V to 2.7 V)

PCA9516A_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 23 April 2009 9 of 19

10. Dynamic characteristics

[1] Typical value taken at 2.5 V and 25 °C.

Table 8. Dynamic characteristics (VCC = 3.0 V to 3.6 V)

[1] Typical value taken at 3.3 V and 25 °C.

Fig 8. Propagation delay and transition times

PCA9516A_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 23 April 2009 10 of 19

11. Test information

RL = load resistor; 1.35 kΩ.

PCA9516A_3 © NXP B.V. 2009. All rights reserved.

Product data sheet Rev. 03 — 23 April 2009 11 of 19

12. Package outline

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

OUTLINE REFERENCES EUROPEAN

Fig 10. Package outline SOT109-1 (SO16)

Product data sheet Rev. 03 — 23 April 2009 12 of 19

DIMENSIONS (mm are the original dimensions)

OUTLINE REFERENCES EUROPEAN

Fig 11. Package outline SOT403-1 (TSSOP16)

Product data sheet Rev. 03 — 23 April 2009 13 of 19

13. Soldering of SMD packages

13.1 Introduction to soldering

13.2 Wave and reflow soldering

Key characteristics in both wave and reflow soldering are: