Quectel BG95-M3 Mini PCIe Hardware Design V1.0
Quectel BG95-M3 Mini PCIe Hardware Design V1.0
Quectel BG95-M3 Mini PCIe Hardware Design V1.0
Hardware Design
Rev. BG95-M3_Mini_PCIe_Hardware_Design_V1.0
Date: 2020-05-15
Status: Released
www.quectel.com
LPWA Module Series
BG95-M3 Mini PCIe Hardware Design
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Copyright © Quectel Wireless Solutions Co., Ltd. 2020. All rights reserved.
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Revision History
Speed SUN/
1.0 2020-05-15 Watt ZHU/ Initial
Hyman DING
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Contents
1 Introduction .......................................................................................................................................... 7
1.1. Safety Information...................................................................................................................... 8
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8 Appendix A References..................................................................................................................... 47
9 Appendix B GPRS Coding Schemes ............................................................................................... 50
10 Appendix C GPRS Multi-slot Classes .............................................................................................. 51
11 Appendix D EDGE Modulation and Coding Schemes ................................................................... 53
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Table Index
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Figure Index
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1 Introduction
This document defines Quectel BG95-M3 Mini PCIe module, and describes its air interfaces and
hardware interfaces which are connected with customers’ applications.
This document helps customers quickly understand the interface specifications, electrical characteristics,
mechanical specifications and other related information of the module. To facilitate application designs, it
also includes some reference designs for customers’ reference. The document, coupled with application
notes and user guides, makes it easy to design and set up mobile applications with BG95-M3 Mini PCIe.
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The following safety precautions must be observed during all phases of operation, such as usage, service
or repair of any cellular terminal or mobile incorporating the module. Manufacturers of the cellular terminal
should notify users and operating personnel of the following safety information by incorporating these
guidelines into all manuals of the product. Otherwise, Quectel assumes no liability for customers’ failure to
comply with these precautions.
Full attention must be paid to driving at all times in order to reduce the risk of an
accident. Using a mobile while driving (even with a handsfree kit) causes
distraction and can lead to an accident. Please comply with laws and regulations
restricting the use of wireless devices while driving.
Switch off the cellular terminal or mobile before boarding an aircraft. The operation
of wireless appliances in an aircraft is forbidden to prevent interference with
communication systems. If there is an Airplane Mode, it should be enabled prior to
boarding an aircraft. Please consult the airline staff for more restrictions on the use
of wireless devices on an aircraft.
Cellular terminals or mobiles operating over radio signals and cellular network
cannot be guaranteed to connect in all possible conditions (for example, with
unpaid bills or with an invalid (U)SIM card). When emergent help is needed in such
conditions, please remember using emergency call. In order to make or receive a
call, the cellular terminal or mobile must be switched on in a service area with
adequate cellular signal strength.
The cellular terminal or mobile contains a transmitter and receiver. When it is ON, it
receives and transmits radio frequency signals. RF interference can occur if it is
used close to TV set, radio, computer or other electric equipment.
In locations with potentially explosive atmospheres, obey all posted signs to turn
off wireless devices such as mobile phone or other cellular terminals. Areas with
potentially explosive atmospheres include fuelling areas, below decks on boats,
fuel or chemical transfer or storage facilities, areas where the air contains
chemicals or particles such as grain, dust and metal powders.
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2 Product Concept
BG95-M3 Mini PCIe is an embedded IoT (LTE Cat M1, LTE Cat NB2 and EGPRS) wireless
communication module with PCI Express Mini Card 1.2 standard interface. It provides data connectivity
on LTE-FDD and GPRS/EGPRS networks, and supports half-duplex operation in LTE network. It also
provides GNSS and voice 1) functionality to meet customers’ specific application demands.
Item Description
LTE-FDD:
LTE Cat M1
B1/B2/B3/B4/B5/B8/B12/B13/B18/B19/B20/B25/B26/B27/B28/B66/B85
LTE-FDD:
LTE Cat NB2
B1/B2/B3/B4/B5/B8/B12/B13/B18/B19/B20/B25/B28/B66/B71/B85
Digital Audio Support PCM for VoLTE and GSM CS voice only
NOTE
1) BG95-M3
Mini PCIe supports VoLTE (Voice over LTE) under LTE Cat M1 network and CS voice under
GSM network.
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The following table describes the detailed features of BG95-M3 Mini PCIe module.
Feature Details
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NOTES
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The following figure shows the block diagram of BG95-M3 Mini PCIe.
Main
USB Main Antenna
Antenna
Connector
Mini PCI Express
UART
Interface
BG95-M3
Module
(U)SIM
GNSS
GNSS
Antenna
(U)SIM Card Antenna
Connector Connector
(Optional)
W_DISABLE#
PERST#
DTR
WAKE#
RI
LED_WWAN#
NOTE
The integrated (U)SIM card connector shares the same (U)SIM bus with the external (U)SIM card
connector that is connected to Mini PCI Express (U)SIM interface. It does not support (U)SIM card
detection function, and cannot be used simultaneously with the external (U)SIM card connector. When
unused, it has no any effect to the external (U)SIM card connector.
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3 Application Interfaces
The physical connections and signal levels of BG95-M3 Mini PCIe comply with PCI Express Mini CEM
specifications. This chapter mainly describes the definition and application of the following interfaces of
BG95-M3 Mini PCIe:
Power supply
(U)SIM interface
USB interface
UART interface
PCM and I2C interfaces*
Control and indicator interfaces
NOTE
The following figure shows the pin assignment of BG95-M3 Mini PCIe module. The top side contains
BG95-M3 module and antenna connectors.
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RI 17 18 GND
RESERVED 19 TOP BOT 20 W_DISABLE#
GND 21 22 PERST#
UART_CTS 23 24 RESERVED
UART_RTS 25 26 GND
GND 27 28 RESERVED
GND 29 PIN51 PIN52 30 I2C_SCL
DTR 31 32 I2C_SDA
RESERVED 33 34 GND
GND 35 36 USB_DM
GND 37 38 USB_DP
VCC_3V3 39 40 GND
VCC_3V3 41 42 LED_WWAN#
GND 43 44 USIM_DET
PCM_CLK 45 46 RESERVED
PCM_DOUT 47 48 RESERVED
PCM_DIN 49 50 GND
PCM_SYNC 51 52 VCC_3V3
The following tables show the pin definition and description of BG95-M3 Mini PCIe.
Type Description
DI Digital Input
DO Digital Output
IO Bidirectional
OC Open Collector
OD Open Drain
PI Power Input
PO Power Output
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Connect to
23 PERn0 UART_CTS DI UART clear to send
DTE’s RTS.
24 3.3 Vaux RESERVED Reserved
Connect to
25 PERp0 UART_RTS DO UART request to send
DTE’s CTS
26 GND GND Mini card ground
Require external
pull-up to 1.8 V.
32 SMB_DATA I2C_SDA 1) OD I2C serial data For VoLTE and
GSM CS voice
only.
33 PETp0 RESERVED Reserved
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NOTES
1) PCM
1. and I2C interfaces support VoLTE and GSM CS voice only.
2. The module can be reset by driving PERST# low for 2–3.8 s.
3. Keep all reserved and unused pins unconnected.
The following table briefly outlines the operating modes to be mentioned in the following chapters.
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Mode Details
The following table shows the definition of VCC_3V3 pins and ground pins.
The typical supply voltage of BG95-M3 Mini PCIe is 3.3 V. In 2G network, the input peak current may
reach 2.7 A during the transmitting time. Therefore, the power supply must be able to provide a rated
current of 2.7 A at least, and a low-ESR bypass capacitor no less than 470 µF should be used to prevent
the voltage from dropping. If the switching power supply is used to supply power to the module, the power
device and power supply routing traces of the switching power supply should avoid the antennas as much
as possible to prevent EMI interference.
The following figure shows a reference design of power supply where R2 and R3 are 1% tolerance
resistors, and C3 is a low-ESR capacitor.
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MIC29302WU U1
LDO_IN VCC_3V3
2 IN OUT 4
GND
ADJ
EN
D1 R1 R2
C1 C2
82K 1% R4
5
TVS 470uF 100nF 51K C3 C4 C5 C6
R5 47K 1%
4.7K
MCU_POWER R6
_ON/OFF 47K
The (U)SIM interface circuitry meets ETSI and IMT-2000 requirements. Only 1.8 V (U)SIM card is
supported. The following table shows the pin definition of (U)SIM interface.
BG95-M3 Mini PCIe supports (U)SIM card hot-plug via USIM_DET, and both high and low level detection
are supported. The function is disabled by default. See AT+QSIMDET in document [2] for details.
The following figure shows a reference design of (U)SIM interface with an 8-pin (U)SIM card connector.
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1.8V USIM_VDD
100 nF
GND
33 pF 33 pF 33 pF
GND GND
Figure 4: Reference Design of (U)SIM Interface with 8-Pin (U)SIM Card Connector
If (U)SIM card detection function is not needed, please keep USIM_DET unconnected. A reference design
of (U)SIM interface with a 6-pin (U)SIM card connector is illustrated in the following figure.
USIM_VDD 100 nF
Module
15K
GND (U)SIM Card Connector
USIM_DATA 0R
33 pF 33 pF 33 pF
GND GND
Figure 5: Reference Design of (U)SIM Interface with 6-Pin (U)SIM Card Connector
In order to enhance the reliability and availability of the (U)SIM card in customers’ applications, please
follow the criteria below in (U)SIM circuit design:
Keep the placement of (U)SIM card connector to the module as close as possible. Keep the trace
length as less than 200 mm as possible.
Keep (U)SIM card signals away from RF and power supply traces.
Assure the ground between the module and the (U)SIM card connector short and wide. Keep the
trace width of ground no less than 0.5 mm to maintain the same electric potential. The decouple
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capacitor between USIM_VDD and GND should be not more than 1 μF and be placed close to the
(U)SIM card connector.
To avoid cross-talk between USIM_DATA and USIM_CLK, keep them away from each other and
shield them with surrounded ground.
In order to offer good ESD protection, it is recommended to add a TVS diode with parasitic
capacitance not exceeding 15 pF. The 0 Ω resistors should be added in series between the module
and the (U)SIM card connector so as to facilitate debugging. The 33 pF capacitors are used for
filtering interference of EGSM900. Please note that the (U)SIM peripheral circuit should be close to
the (U)SIM card connector.
The pull-up resistor on USIM_DATA line can improve anti-jamming capability when long layout trace
and sensitive occasion are applied, and should be placed close to the (U)SIM card connector.
The module provides one integrated Universal Serial Bus (USB) interface which complies with the USB
2.0 specification and supports operation at low-speed (1.5 Mbps) and full-speed (12 Mbps) modes. The
USB interface is used for AT command communication, data transmission, GNSS NMEA output, software
debugging, and firmware upgrade.
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Test Points
Minimize these stubs
Module MCU
R3 NM_0R
R4 NM_0R
ESD Array
L1 USB_DM
USB_DM
USB_DP USB_DP
A common mode choke L1 is recommended to be added in series between the module and the MCU in
order to suppress EMI spurious transmission. Meanwhile, the 0 Ω resistors (R3 and R4) should be added
in series between the module and the test points so as to facilitate debugging, and the resistors are not
mounted by default. In order to ensure the integrity of USB data line signal, L1/R3/R4 must be placed
close to the module, and also the resistors should be placed close to each other. The extra stubs of trace
must be as short as possible.
The following principles should be complied with when design the USB interface, so as to meet USB 2.0
specification.
It is important to route the USB signal traces as differential pairs with ground surrounded. The
impedance of USB differential trace is 90 Ω.
Do not route signal traces under crystals, oscillators, magnetic devices and RF signal traces. It is
important to route the USB differential traces in inner-layer of the PCB, and surround the traces with
ground on that layer and with ground planes above and below.
Junction capacitance of the ESD protection device might cause influences on USB data lines, so
please pay attention to the selection of the device. Typically, the stray capacitance should be less
than 2 pF.
Keep the ESD protection devices as close to the USB connector as possible.
NOTE
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The UART interface supports 9600, 19200, 38400, 57600, 115200 and 230400 bps baud rates. The
default baud rate is 115200 bps. This interface can be used for AT command communication and data
transmission.
The following table shows the pin definition of the UART interface.
The power domain of UART interface is 3.3 V. Pay attention to the signal direction while connecting the
UART interface to a peripheral MCU/RAM. A reference design of UART interface is provided below:
MCU/ARM Module
TXD UART_TXD
RXD UART_RXD
RTS UART_RTS
CTS UART_CTS
GND GND
NOTE
AT+IPR can be used to set the baud rate of UART interface, and AT+IFC can be used to set the hardware
flow control (hardware flow control is disabled by default). See document [2] for details.
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BG95-M3 Mini PCIe provides one Pulse Code Modulation (PCM) digital interface and one I2C interface
for VoLTE and GSM CS voice.
The following table shows the pin definition of PCM and I2C interfaces that can be applied in audio codec
design.
The following figure shows a reference design of PCM and I2C interfaces with an external codec IC.
MIC_BIAS
PCM_CLK BCLK
PCM_SYNC FS MIC+
BIAS
SPKOUT+
I2C_SCL SCLK
I2C_SDA SDIN SPKOUT-
Module Codec
2.2K
2.2K
1.8V
Figure 8: Reference Design of PCM and I2C Application with Audio Codec
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NOTE
PCM and I2C interfaces support VoLTE and GSM CS voice only.
The following table shows the pin definition of control and indication interfaces.
NOTE
3.7.1. RI
RI is used to wake up the host. When a URC returns, there will be the following behaviors on the RI pin
after executing AT+QCFG="risignaltype","physical".
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120 ms
High
Low
URC return
Figure 9: RI Behavior
3.7.2. W_DISABLE#
W_DISABLE# enables/disables the RF function (excluding GNSS). It is pulled up by default, and driving it
low makes the module enter airplane mode.
The pin function is disabled by default, and AT+QCFG="airplanecontrol",1 can be used to enable this
function.
The RF function can also be enabled/disabled with AT+CFUN=<fun>, and the details are listed below.
3.7.3. PERST#
PERST# forces a hardware reset on the module. The module can be reset by driving PERST# low for
2–3.8 s and then releasing it. The reset timing is illustrated in the following figure.
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VCC_3V3
≤ 3.8 s
≥2s
PERST# VIH ≥ 2.3 V
VIL ≤ 0.45 V
3.7.4. LED_WWAN#
LED_WWAN# indicates the network status of the module, and it absorbs a current up to 40 mA.
According to the following circuit, in order to reduce the current of the LED, a resistor must be placed in
series with the LED. The LED is powered on when LED_WWAN# is pulled low.
LED_WWAN# R
VCC
LED_WWAN# supports two indication modes which can be switched through AT+QCFG="ledmode":
The following tables show the detailed network status indications of LED_WWAN#.
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3.7.5. WAKE#
WAKE# is an open collector signal which is similar to RI, but a host pull-up resistor and
AT+QCFG="risignaltype","physical" command are required. When a URC returns, a 120 ms low level
pulse will be outputted. The state of WAKE# is shown as below.
120ms
High
(external
pull-up)
Low
URC return
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4 GNSS Receiver
BG95-M3 Mini PCIe includes a fully integrated global navigation satellite system solution that supports
Gen9 VT of Qualcomm (GPS, GLONASS, BeiDou, Galileo and QZSS).
The module supports standard NMEA 0183 protocol, and outputs NMEA sentences at 1 Hz data update
rate via USB interface by default.
By default, the GNSS engine is switched off. It has to be switched on via AT command. See document [3]
for more details about GNSS engine technology and configurations.
The following table shows the GNSS performance of BG95 Mini PCIe.
Autonomous TBD s
Cold start
@open sky
XTRA enabled TBD s
TTFF
Autonomous TBD s
(GNSS) Warm start
@open sky
XTRA enabled TBD s
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Accuracy Autonomous
CEP-50 <3 m
(GNSS) @open sky
NOTES
1. Tracking sensitivity: the minimum GNSS signal power at which the module can maintain lock (keep
positioning for at least 3 minutes continuously).
2. Reacquisition sensitivity: the minimum GNSS signal power required for the module to maintain lock
within 3 minutes after loss of lock.
3. Cold start sensitivity: the minimum GNSS signal power at which the module can fix position
successfully within 3 minutes after executing cold start command.
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5 Antenna Connection
BG95-M3 Mini PCIe is mounted with two antenna connectors for external antenna connection: a main
antenna connector and a GNSS antenna connector. The impedance of the antenna connectors is 50 Ω.
Main GNSS
Antenna Antenna
Connector Connector
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NOTES
1) LTE-FDD
1. B26 and B27 are supported by Cat M1 only.
2) LTE-FDD
2. B71 is supported by Cat NB2 only.
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By default, the GNSS antenna connector supports active antennas with 3.3 V power supply design. It also
supports passive antennas.
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The following table shows the requirements on main and GNSS antennas.
Type Requirements
BG95-M3 Mini PCIe is mounted with antenna connectors (receptacles) for convenient antenna
connection. The dimensions of receptacles are shown as below.
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U.FL-LP mating plugs listed in the following figure can be used to match the receptacles.
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For more details of the recommended mating plugs, please visit http://www.hirose.com.
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This chapter mainly describes the following electrical and radio characteristics of BG95-M3 Mini PCIe:
The input voltage of BG95-M3 Mini PCIe is 3.3 V ±9% (3.0–3.6 V), as specified by PCI Express Mini CEM
Specifications 1.2. The following table shows the power supply requirements of the module.
The following table shows the digital I/O characteristics of the module.
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NOTES
1. The PCM and I2C interfaces belong to 1.8 V power domain and other I/O interfaces belong to
VCC_3V3 power domain.
2. The maximum voltage value of VIL for PERST# and W_DISABLE# is 0.5 V.
6.4. RF Characteristics
The following tables show the conducted RF output power and receiving sensitivity of the module.
LTE-FDD B1/B2/B3/B4/B5/B8/B12/B13/B18/B19/B20/
21 dBm + 1.7/-3 dB < -39 dBm
B25/B26 1)/B27 1)/B28/B66/B71 2)/B85
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NOTES
1)
1. LTE-FDD B26 and B27 are supported by Cat M1 only.
2)
2. LTE-FDD B71 is supported by Cat NB2 only.
Sensitivity (dBm)
Band Primary Diversity
Cat M1/3GPP Cat NB2 1)/3GPP
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Sensitivity (dBm)
Band Primary Diversity
GSM/3GPP
NOTE
1)
LTE Cat NB2 receiving sensitivity without repetitions.
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LTE Cat M1
28 - mA
DRX = 1.28 s
LTE Cat NB1
28 - mA
DRX = 1.28 s
Idle Mode
LTE Cat M1
(USB
eDRX = 40.96 s 27 - mA
connected)
@ PTW = 10.24 s, DRX = 2.56 s
LTE Cat NB1
eDRX = 40.96 s 27 - mA
@ PTW = 10.24 s, DRX = 2.56 s
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This chapter mainly describes mechanical dimensions as well as packaging specification of BG95-M3
Mini PCIe module. All dimensions are measured in millimeter (mm), and the dimensional tolerances are
±0.05 mm unless otherwise specified.
30.00±0.15
24.20±0.2
8.35 Φ2.6±0.1
2.90±0.15 1.00±0.1
6.39 6.39 2.055±0.15
2.90±0.15
11.85±0.15
2.25±0.2
47.75±0.15
23.60±0.2
50.95±0.15
1.40±0.1
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The following figure shows the standard dimensions of Mini PCI Express. See document [1] for Detail A
and Detail B.
BG95-M3 Mini PCIe adopts a standard Mini PCI Express connector which compiles with the directives
and standards listed in document [1]. The following figure takes the Molex 679105700 as an example.
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Figure 19: Dimensions of the Mini PCI Express Connector (Molex 679105700)
BG95-M3 Mini PCIe modules are packaged in a tray. Each tray contains 10 modules. The smallest
package contains 100 modules.
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8 Appendix A References
Abbreviation Description
CS Coding Scheme
DL Downlink
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ME Mobile Equipment
RF Radio Frequency
RX Receive Direction
TX Transmitting Direction
UL Uplink
BG95-M3_Mini_PCIe_Hardware_Design 48 / 53
LPWA Module Series
BG95-M3 Mini PCIe Hardware Design
BG95-M3_Mini_PCIe_Hardware_Design 49 / 53
LPWA Module Series
BG95-M3 Mini PCIe Hardware Design
USF 3 3 3 3
Pre-coded USF 3 6 6 12
Radio Block excl. USF and BCS 181 268 312 428
BCS 40 16 16 16
Tail 4 4 4 -
BG95-M3_Mini_PCIe_Hardware_Design 50 / 53
LPWA Module Series
BG95-M3 Mini PCIe Hardware Design
1 1 1 2
2 2 1 3
3 2 2 3
4 3 1 4
5 2 2 4
6 3 2 4
7 3 3 4
8 4 1 5
9 3 2 5
10 4 2 5
11 4 3 5
12 4 4 5
13 3 3 NA
14 4 4 NA
BG95-M3_Mini_PCIe_Hardware_Design 51 / 53
LPWA Module Series
BG95-M3 Mini PCIe Hardware Design
15 5 5 NA
16 6 6 NA
17 7 7 NA
18 8 8 NA
19 6 2 NA
20 6 3 NA
21 6 4 NA
22 6 4 NA
23 6 6 NA
24 8 2 NA
25 8 3 NA
26 8 4 NA
27 8 4 NA
28 8 6 NA
29 8 8 NA
30 5 1 6
31 5 2 6
32 5 3 6
33 5 4 6
BG95-M3_Mini_PCIe_Hardware_Design 52 / 53
LPWA Module Series
BG95-M3 Mini PCIe Hardware Design
Coding
Modulation Coding Family 1 Timeslot 2 Timeslots 4 Timeslots
Schemes
BG95-M3_Mini_PCIe_Hardware_Design 53 / 53