La-L161p Rev0.1 (Diagramas - Com.br)
La-L161p Rev0.1 (Diagramas - Com.br)
La-L161p Rev0.1 (Diagramas - Com.br)
1 1
Compal Confidential
2
GOG10 2
3
2020-09-15 3
LA-L161P
REV:0.1
4 4
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: W ednesday, March 10, 2021 Sheet 1 of 121
A B C D E
5 4 3 2 1
Audio Codec
HDA Realtek ALC3287
B
Int. Speaker
MIC
SATA Redriver SATA (Gen3) Int. Array Mic
HDD Conn.
PS8527C SPI ROM
SPI
W25R128JVSIQ
USB 2.0 x1 16MB
SPI ROM
W25Q64JVSSIQ
eSPI Bus 8MB
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Black Diagram
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: Wednesday, March 10, 2021 Sheet 2 of 121
5 4 3 2 1
1 2 3 4 5
A A
B B
ZZZ PCB@
PCB
LA-L161PR1A
DAA000PO01A
ZZZ X4E@
EMC
LA-L161P
X4EAQK38L01
OVR-M
LA-L161P LA-L161P
X7691138L05 X7691138L04
D
VRAM D
ZZZ HDMI_Logo@
HDMI
Logo LA-L161P
Security Classification
Issued Date
Compal Secret Data
Deciphered Date Title
Compal Electronics, Inc.
XXXXXXXXXX
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: Wednesday, March 10, 2021 Sheet 3 of 121
1 2 3 4 5
5 4 3 2 1
[FQA01-Power Map_TGL-UP3_DDR4_Volume_S0ix]
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power MAP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: Wednesday, March 10, 2021 Sheet 4 of 121
5 4 3 2 1
5 4 3 2 1
[ FQA01-PWR Sequence_TGL-UP3_DDR4_Volume_S0iX ]
PCH_DPWROK
tPCH05_Min : 1 us
PM_BATLOW#
PM_BATLOW#
tPCH32_Min : 95 ms
SLP_SUS#
SLP_SUS#
+5VALW
+5VALW
EXT_PWR_GATE#
EXT_PWR_GATE#
+3V_PRIM
+3V_PRIM
tPCH06_Min : 200 us
+1.8V_PRIM
+1.8V_PRIM
+VCCIN_AUX
+VCCIN_AUX
+1.05VO_OUT_PCH
+1.05VO_OUT_PCH
+1.05VO_VNNBYPASS
+1.05VO_VNNBYPASS
+1.05VO_EXTBYPASS
+1.05VO_EXTBYPASS
tPCH03_Min : 10 ms
EC_RSMRST#
EC_RSMRST# tPCH07_Min : 0 ms
tPCH18_Min : 95 ms
ESPI_RST# ESPI_RST#
SUSCLK
tPLT02_Max : 90 ms
tPCH31_Min : 105 ms AC_PRESENT_R
AC_PRESENT_R
VCCST_Can_be_On_until_VCCINAUX_goes_LOW
+1.05V_VCCST +1.05V_VCCST_Must_be_ON_anytime_VCCIN_AUX_is_ON +1.05V_VCCST
C C
+1.05VO_VCCPLL +1.05VO_VCCPLL
PBTN_OUT#
PBTN_OUT#
PM_SLP_S5#
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S4#
PM_SLP_S3# PM_SLP_S3#
PM_SLP_S0#
PM_SLP_S0#
CPU_C10_GATE#
CPU_C10_GATE#
VCCST_OVERRIDE High_in_Sx_if_TCSS_wake_enabled
VCCST_OVERRIDE
Min : 0 ms
+2.5V
+2.5V
+1.2V_VDDQ
tCPU01_Min : 1 ms +1.2V_VDDQ
+1.2V_VCCPLL_OC
+1.2V_VCCPLL_OC
B +1.05VS_VCCSTG B
+1.05VS_VCCSTG
VCCST and VCCSTG may remain powered during
Sx power states for Debug support and platform VR optimization.
VCCSTPWRGOOD_TGSS
VCCSTPWRGOOD_TGSS
EC_VCCST_PG EC_VCCST_PG
tCPU00_Min : 2 ms
DDR_PG_CTRL DDR_PG_CTRL
+0.6VS_VTT +0.6VS_VTT
VR_ON VR_ON
+VCCIN +VCCIN
VR_PWRGD VR_PWRGD
+1.05V_VCCIO_OUT +1.05V_VCCIO_OUT
H_PROCPWRGD H_PROCPWRGD
A A
SYS_PWROK SYS_PWROK
SOC_PLTRST#
SOC_PLTRST#
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power Sequence
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: Wednesday, March 10, 2021 Sheet 5 of 121
5 4 3 2 1
A B C D E
UC1A
AC2 REV 1.6 AY2
<38> EDP_TXP3 DDIA_TXP_3 TCP0_TXRX_P1
AC1 AY1
<38> EDP_TXN3 DDIA_TXN_3 TCP0_TXRX_N1
AD2 BB1
<38> EDP_TXP2 DDIA_TXP_2 TCP0_TXRX_P0
AD1 BB2
<38> EDP_TXN2
<eDP> <38> EDP_TXP1
AF1 DDIA_TXN_2
DDIA_TXP_1
TCP0_TXRX_N0
TCP0_TX_P1
AM5
1 AF2 AM7 1
<38> EDP_TXN1 DDIA_TXN_1 TCP0_TX_N1
AG2 AT7
<38> EDP_TXP0 DDIA_TXP_0 TCP0_TX_P0
AG1 AT5
<38> EDP_TXN0 DDIA_TXN_0 TCP0_TX_N0 AP7
AJ2 TCP0_AUX_P AP5
<38> EDP_AUXP DDIA_AUX_P TCP0_AUX_N
<38> EDP_AUXN AJ1
DDIA_AUX_N AT2
DN4 TCP1_TXRX_P1 AT1
DT6 GPP_E22/DDPA_CTRLCLK/DNX_FORCE_RELOAD TCP1_TXRX_N1 AU1
GPP_E23/DDPA_CTRLDATA TCP1_TXRX_P0 AU2
DR5 TCP1_TXRX_N0 AD5
From eDP <38> EDP_HPD GPP_E14/DDSP_HPDA/DISP_MISCA TCP1_TX_P1 AD7
T12 TCP1_TX_N1 AH7
<40> CPU_DP2_P3 DDIB_TXP_3 TCP1_TX_P0
T11 AH5
<40> CPU_DP2_N3 DDIB_TXN_3 TCP1_TX_N0
Y11 AF7
<40> CPU_DP2_P2 DDIB_TXP_2 TCP1_AUX_P
Y9 AF5
<40> CPU_DP2_N2 DDIB_TXN_2 TCP1_AUX_N
<HDMI> T9
<40> CPU_DP2_P1 DDIB_TXP_1
P9 BF1
<40> CPU_DP2_N1 DDIB_TXN_1 TCP2_TXRX_P1
V11 BF2
<40> CPU_DP2_P0 DDIB_TXP_0 TCP2_TXRX_N1
V9 BE2
<40> CPU_DP2_N0 DDIB_TXN_0 TCP2_TXRX_P0 BE1
AB9 TCP2_TXRX_N0 BD7
AD9 DDIB_AUX_P TCP2_TX_P1 BD5
DDIB_AUX_N TCP2_TX_N1 AY5
DM29 TCP2_TX_P0 AY7
<40> CPU_DP2_CTRL_CLK GPP_H16/DDPB_CTRLCLK/PCIE_LNK_DOWN TCP2_TX_N0
HDMI DDC (Port 2) <40> DK27 BB5
CPU_DP2_CTRL_DATA GPP_H17/DDPB_CTRLDATA TCP2_AUX_P BB7
DG43 TCP2_AUX_N
<40> CPU_DP2_HPD GPP_A18/DDSP_HPDB/DISP_MISCB/I2S4_RXD BK1
2 DG47 TCP3_TXRX_P1 BK2 2
DJ47 GPP_A21/DDPC_CTRLCLK/I2S5_TXD TCP3_TXRX_N1 BJ2
GPP_A22/DDPC_CTRLDATA/I2S5_RXD TCP3_TXRX_P0 BJ1
DU8 TCP3_TXRX_N0 BM7
DV8 GPP_E18/DDP1_CTRLCLK/TBT_LSX0_TXD TCP3_TX_P1 BM5
GPP_E19/DDP1_CTRLDATA/TBT_LSX0_RXD TCP3_TX_N1 BH5
DF6 TCP3_TX_P0 BH7
+3V_PRIM DD6 GPP_E20/DDP2_CTRLCLK/TBT_LSX1_TXD TCP3_TX_N0 BK5
GPP_E21/DDP2_CTRLDATA/TBT_LSX1_RXD TCP3_AUX_P BK7
DN23 TCP3_AUX_N
RC164 1 2 10K_0201_5% USB_OC1# DM23 GPP_D9/ISH_SPI_CS#/DDP3_CTRLCLK/TBT_LSX2_TXD/GSPI2_CS0# AN2 TC_RCOMP_P RC618 1 2 150_0201_1%
RC165 1 2 10K_0201_5% USB_OC2# GPP_D10/ISH_SPI_CLK/DDP3_CTRLDATA/TBT_LSX2_RXD/GSPI2_CLK TC_RCOMP_P AN1 TC_RCOMP_N
RC422 1 2 100K_0201_5% ENBKL DK23 TC_RCOMP_N
DN21 GPP_D11/ISH_SPI_MISO/DDP4_CTRLCLK/TBT_LSX3_TXD/GSPI2_MISO M8 DSI_DE_TE_2 RC617 1 2 100K_0201_5%
GPP_D12/ISH_SPI_MOSI/DDP4_CTRLDATA/TBT_LSX3_RXD/GSPI2_MOSI DSI_DE_TE_2
DF43 AB1 DDI_RCOMP RC616 1 2 150_0201_1%
DF45 GPP_A17/DISP_MISCC/I2S4_TXD DDI_RCOMP
DF47 GPP_A19/DDSP_HPD1/DISP_MISC1/I2S5_SCLK CE4 DISP_UTILS 1
GPP_A20/DDSP_HPD2/DISP_MISC2/I2S5_SFRM DISP_UTILS/DSI_DE_TE_1 TP@ T5
USB_OC1# DH52
USB_OC2# DK45 GPP_A14/USB_OC1#/DDSP_HPD3/I2S3_RXD/DISP_MISC3/DMIC_CLK_B1
GPP_A15/USB_OC2#/DDSP_HPD4/DISP_MISC4/I2S4_SCLK
PCH_ENVDD DM8
<38> PCH_ENVDD EDP_VDDEN
EDP_VDDEN: ENBKL DN8
<58> ENBKL EDP_BKLTEN
100K PD on load swith side <38> INVPW M DG10
INVPW M EDP_BKLTCTL
TGL-U_BGA1449
@
3 3
CPU
UC1 UC1
CPU_i5@ CPU_i7@
i5_SRKH6_R3 i7_SRKH5_R3
SA0000E4740 SA0000E4640
4 4
Date:
Date: W ednesday, March 10, 2021 Sheet
Sheet 6 of 121
A B C D E
A B C D E
+1.05VS_VCCSTG_OUT_LGC
1
+1.05VS_VCCSTG
RC6
1K_0201_5% UC1U
REV 1.6
T2422 SOC_XDP_TRST#
TP@ 1CATERR# M7 K4
1
CATERR# PROC_TRST#
2
BK9 B9 SOC_XDP_TMS
<58> H_PECI PECI PROC_TMS RC581
1 H_PROCHOT# 1 2 H_PROCHOT#_R E2 D12 SOC_XDP_TDO 1
<58> H_PROCHOT# PROCHOT# PROC_TDO 1K_0201_5%
RC7 499_0201_1% H_THERMTRIP# M5 A12 SOC_XDP_TDI
THRMTRIP# PROC_TDI B6 SOC_XDP_TCK0
PROC_POPIRCOMP CT39 PROC_TCK
2
PCH_OPIRCOMP CB9 PROC_POPIRCOMP D8 SOC_XDP_TCK0
+3V_PRIM PCH_OPIRCOMP PCH_JTAGX SOC_EAR
T6 TP@ 1 SOC_TP_1 CW12 A9 SOC_XDP_TMS
T7 TP@ 1 SOC_TP_2 CM39 TP_1 PCH_TMS E12 SOC_XDP_TDO
TP_2 PCH_TDO B12 SOC_XDP_TDI
1
XDP_ITP_PMODE DF4 PCH_TDI A7 PCH_JTAG_TCK1
RC371 DBG_PMODE PCH_TCK SOC_XDP_TRST# RC582
H4
100K_0201_5% SOC_GPP_B4 PCH_TRST# 1K_0201_5%
T2413 TP@ 1 DB42
GPP_B4/CPU_GP3 XDP_PREQ# @
DB41 C11
SOC_GPP_E7 DF8 GPP_B3/CPU_GP2 PROC_PREQ# D11 XDP_PRDY#
2
GPP_E7/CPU_GP1 PROC_PRDY# TP@ T498
H_PROCHOT# DU5
<17> VCCIN_AUX_CORE_ALERT#_R DC10 1 2 GPP_E3/CPU_GP0 SOC_EAR
G1
RB751V-40_SOD323-2 SOC_GPP_H2 EAR_N/EAR_N_TEST_NCTF
DF31
SCS00000Z00 SOC_GPP_H1 GPP_H2 SOC_GPP_F7
DV32 DT15
SOC_GPP_H0 DW32 GPP_H1 GPP_F7 DR15 SOC_GPP_F9
GPP_H0 GPP_F9 DT14 SOC_GPP_F10
1SOC_GPP_H19 DJ27 GPP_F10
T2409 TP@ GPP_H19/TIME_SYNC0 +3V_PRIM
TGL-U_BGA1449
1
@
RC38
4.7K_0201_5%
2 @ 2
2
+1.05V_VCCST
SOC_GPP_F7
RC11 1 2 1K_0201_5% CATERR#
www.teknisi-indonesia.com
1
RC12 1 2 1K_0201_5% H_THERMTRIP# RC40
CC2 2 1 0.1U_0201_10V6K 20K_0201_5%
@
@ESD@
2
+3VS
SOC_GPP_H2
BOOT STRAP3 - BIT3 < PU/PD for DCI Debug > +1.05VS_VCCSTG_OUT_LGC
This is bit 1 of a total of 4-bit encoded pin straps for
boot configuration.
Refer to Boot Strap 0 (on GPP_C5) for the encoding.
+3V_PRIM INTERNAL PD 20K SOC_XDP_TMS RC13 1 @ 2 51_0201_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(2/14)DDI,MSIC,XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Size DocumentNumber
Document Number Rev
Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.A
Date:
Date: Wednesday, March 10, 2021 Sheet
Sheet 7 of 121
A B C D E
5 4 3 2 1
UC1B UC1C
REV 1.6 REV 1.6
TGL-U_BGA1449
@
+1.2V
1
Buffer with Open Drain Output RC30
470_0201_5%
For VTT power control UC1D
+1.2V +3VS
REV 1.6
2
CC6 2 1 0.1U_0201_10V6K DDR_DRAMRST# RC31 1 @ 2 0_0201_5%
DDR_DRAMRST#_R <23,24>
1
DV24
UC3 RC28 1 RSVD_2
DW47
1 5 100K_0201_5% CC9 RSVD_3
NC VCC DW49
100P_0201_50V8J RSVD_4
DDR_PG_CTRL A48
2 ESD@ RSVD_5
A
2
4 2
Y DDR_VTT_PG_CTRL <89>
3
GND TGL-U_BGA1449
@
74AUP1G07SE-7_TSSOP5
SA00007W E00
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(3/14)DDR4
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: Wednesday, March 10, 2021 Sheet 8 of 121
5 4 3 2 1
5 4 3 2 1
+3V_PRIM
1
+1.8V_PRIM SPI0_IO3 GPP_C1/SMBDATA SOC_SMBDATA <23,24> SOC_GPP_B23
SOC_SPI_0_D2 DJ39 DN19 SOC_GPP_C2 CPUNSSC CLOCK FREQ
SOC_SPI_0_D1 SPI0_IO2 GPP_C2/SMBALERT# RC81
DJ33 INTERNAL PD 20K
SPI ROM SOC_SPI_0_D0 DJ35 SPI0_MISO
SPI0_MOSI GPP_C3/SML0CLK
DK19 SOC_SML0CLK HIGH: 19.2 MHz (form internal divider)
4.7K_0201_5%
@
1
SOC_SPI_0_CS#1 DF35 DM17 SOC_SML0DATA LOW: 38.4 MHz (direct form crystal) (Default)
100K_0201_5%
RC648
2
TP@ 1 SOC_SPI_0_CS#2 DF39 SPI0_CS0# GPP_C5/SML0ALERT#
T11 SPI0_CS2# SOC_SML1CLK
DK17 SML1 SOC_GPP_B23
DJ6 GPP_C6/SML1CLK DJ17 SOC_SML1DATA
GPP_E11 / THC0_SPI1_CLK GPP_C7/SML1DATA
2
RC32 15_0201_1%
SOC_THC_0_RST# GPP_E17/THC0_SPI1_INT# GPP_A0/ESPI_IO0 ESPI_CS# ESPI_IO0_R <58>
C DT8 DK52 C
GPP_E6/THC0_SPI1_RST# GPP_A4/ESPI_CS# ESPI_RST# ESPI_CS# <58>
@ DL50
GPP_A6/ESPI_RESET# ESPI_RST# <58>
SOC_THC_0_RST# DN15
DK13 GPP_F11/THC1_SPI2_CLK
JTAG ODT DISABLE GPP_F15/GSXSRESET#/THC1_SPI2_IO3
2
A A
UC1G
REV 1.6
TGL-U_BGA1449
@
B B
1
RC575 RC576 RC573 RC574
3.3K_0402_1% 3.3K_0402_1% 3.3K_0402_1% 698_0402_1%
RC51 1 @ 2 0_0201_5% HDA_SDOUT
<58> ME_EN
2
2
2
G
SOC_DMIC_R_CLK0 1 6 SOC_DMIC_CLK0 RC11331 2 0_0402_5%
DMIC_CLK <38>
D
QC4B
PJT138KA_SOT363-6
5
G
SOC_DMIC_R_DAT0 4 3 SOC_DMIC_DAT0 RC11341 2 0_0402_5%
S DMIC_DAT <38>
QC4A D
PJT138KA_SOT363-6
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(5/14)HDA,SD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.A
+3VS
Follow UC1K
REV 1.6 CLKREQ_PCIE#0_SSD2 10K_0201_5% 1 2 RC523
607872_TGL_UY_PDG_Rev0p5 for Glitch BW1 DU14 CLKREQ_PCIE#6_LAN 10K_0201_5% 1 2 RC1146
<51> CLK_PCIE_P6 CLKOUT_PCIE_P6 GPP_F19/SRCCLKREQ6# CLKREQ_PCIE#6_LAN <51> CLKREQ_PCIE#2_WLAN
LAN BW2 DF23 10K_0201_5% 1 2 RC353
+3VALW <51> CLK_PCIE_N6 CLKOUT_PCIE_N6 GPP_H11/SRCCLKREQ5# CLKREQ_PCIE#5_SSD1 <68> CLKREQ_PCIE#4_GPU
DG25 CLKREQ_PCIE#4_GPU <27> 10K_0201_5% 1 2 RC64
CB2 GPP_H10/SRCCLKREQ4# DT24 CLKREQ_PCIE#5_SSD1 1 2
PM_SLP_S0#
SSD2 <68> CLK_PCIE_P5 CLKOUT_PCIE_P5 GPP_D8/SRCCLKREQ3# CPU_C10_GATE#
10K_0201_5% RC352
RC553 1 2 100K_0201_5% CB1 DT30 100K_0201_5% 1 @ 2 RC122
2280 <68> CLK_PCIE_N5 CLKOUT_PCIE_N5 GPP_D7/SRCCLKREQ2# DV30
CLKREQ_PCIE#2_WLAN <52> AC_PRESENT 10K_0201_5% 1 @ 2 RC1136
RC655 1 2 100K_0201_5% PM_SLP_LAN# GPP_D6/SRCCLKREQ1# DW30
SLP_SUS# GPP_D5/SRCCLKREQ0# CLKREQ_PCIE#0_SSD2 <68>
RC394 1 2 100K_0201_5% BW4
PM_SLP_S5# <27> CLK_PCIE_P4 BW5 CLKOUT_PCIE_P4 DM1 SOC_XTAL38.4_OUT
RC395 1 2 100K_0201_5% GPU
PM_SLP_S4# <27> CLK_PCIE_N4 CLKOUT_PCIE_N4 XTAL_OUT DL1 SOC_XTAL38.4_IN CPU_C10_GATE#
RC396 1 2 100K_0201_5% 100K_0201_5% 1 2 RC678
RC397 1 2 100K_0201_5% PM_SLP_S3# CL7 XTAL_IN CLKREQ_PCIE#4_GPU 10K_0201_5% 1 @ 2 RC68
RC398 1 2 100K_0201_5% PM_SLP_A# CL8 CLKOUT_PCIE_P3 DW41 SUSCLK RC376 1 @ 2 0_0201_5% CLKREQ_PCIE#5_SSD1 10K_0201_5% 1 @ 2 RC1132
PM_SLP_WLAN# CLKOUT_PCIE_N3 GPD8/SUSCLK SUSCLK_R <52> CLKREQ_PCIE#0_SSD2
D
RC400 1 2 100K_0201_5% 10K_0201_5% 1 @ 2 RC1131 D
CB4 DT47 SOC_RTCX2
<52> CLK_PCIE_P2 CB5 CLKOUT_PCIE_P2 RTCX2 DR47 SOC_RTCX1
WLAN <52> CLK_PCIE_N2 CLKOUT_PCIE_N2 RTCX1
BY4 DN37 SOC_RTCRST# +3VALW
BY3 CLKOUT_PCIE_P1 RTCRST# DK37 SOC_SRTCRST#
CLKOUT_PCIE_N1 SRTCRST#
+3VALW CN7
SSD1 <68> CLK_PCIE_P0 CLKOUT_PCIE_P0
CN8 PMCALERT# 10K_0201_5% 2 @ 1 RC1135
RC428 1 2 10K_0201_5% SYS_RESET# 2242 <68> CLK_PCIE_N0 CLKOUT_PCIE_N0 PM_BATLOW# 8.2K_0201_5% 2 1 RC69
RC59 2 1 60.4_0402_1% XCLK_BIASREF DJ5 WAKE# 8.2K_0201_5% 2 1 RC451
XCLK_BIASREF LAN_WAKE# 10K_0201_5% 2 1 RC452
TGL-U_BGA1449 SPIVCCIOSEL 4.7K_0201_5% 2 @ 1 RC456
@ESD@ CC20 2 1 100P_0201_50V8J @ SPI SEL
0 : 3.3V 4.7K_0201_5% 2 1 RC457
ESD@ CC21 2 1 100P_0201_50V8J EC_RSMRST#_R 1 : 1.8V
ESD@ CC22 2 1 100P_0201_50V8J SYS_PWROK UC1L PMCALERT# 75K_0201_5% 2 @ 1 RC118
SLP_SUS# DV49 REV 1.6 BM9 H_PROCPWRGD SUSCLK 10K_0201_5% 2 @ 1 RC375
SOC_PLTRST# <90> SLP_SUS# SLP_SUS# PROCPWRGD PBTN_OUT# TP@ T503
ESD@ CC23 2 1 100P_0201_50V8J DK41
PM_SLP_S5# GPD3/PWRBTN# PM_BATLOW# PBTN_OUT# <58>
DM43 DN41
PM_SLP_S4# DJ41 GPD10/SLP_S5# GPD0/BATLOW# DK43 AC_PRESENT_R RC66 1 @ 2 0_0201_5%
<58,89> PM_SLP_S4# PM_SLP_S3# GPD5/SLP_S4# GPD1/ACPRESENT AC_PRESENT <58> Follow
<16,58> PM_SLP_S3#
DJ43
PM_SLP_A# DR41 GPD4/SLP_S3# CW40 PMCALERT# 609003_TGL_U_DDR4_SODIMM_RVP_SCH
PM_SLP_WLAN# DT44 GPD6/SLP_A# GPP_B11/PMCALERT# DN27 CPU_C10_GATE#
GPD9/SPL_WLAN# GPP_H18/CPU_C10_GATE# CPU_C10_GATE# <16>
DG31
PM_SLP_S0# DD42 GPP_H3/SX_EXIT_HOLDOFF#
<58> PM_SLP_S0# PM_SLP_LAN# GPP_B12/SLP_S0#
DN39 DK39 WAKE#
SLP_LAN# WAKE#
EC_RSMRST#_R DM35 DM41 LAN_WAKE# SOC_GPP_F21 100K_0201_5% 1 @ 2 RC137
SYS_RESET# DD10 RSMRST# GPD2/LAN_WAKE# DT41
SOC_PLTRST# DD41 SYS_RESET# GPD11/LANPHYPC/DSWLDO_MON EC_VCCST_PG 0.1U_0201_10V6K 1 2 CC752
GPP_B13/PLTRST# DN43
+3VL_RTC PCH_DPWROK_R DK35 GPD7 ESD@
SYS_PWROK DF10 DSW_PWROK CE5 VCCSTPWRGOOD_TCSS RC453 1 @ 2 0_0201_5% ESD Suggestion
<58> SYS_PWROK PCH_PWROK SYS_PWROK VCCSTPWRGOOD_TCSS EC_VCCST_PG
DN35 BP8
C SOC_SRTCRST# <58> PCH_PWROK PCH_PWROK VCCST_PWRGD BP9 VCCST_OVERRIDE VCCST_OVERRIDE_R C
RC56 1 2 20K_0201_5% RC388 1 @ 2 0_0201_5%
SM_INTRUDER# DM37 VCCST_OVERRIDE
CC13 1 2 1U_0201_6.3V6M SPIVCCIOSEL DT49 INTRUDER# DR12
SPIVCCIOSEL GPP_F20/EXT_PWR_GATE# DW12 SOC_GPP_F21
GPP_F21/EXT_PWR_GATE2#
TGL-U_BGA1449
RC58 1 2 20K_0201_5% SOC_RTCRST# RC72 1 @ 2 0_0402_5% @
EC_CLEAR_CMOS# <58> SOC_RTCX2
@ 1 2
RC665 1 2 0_0201_5%
CC14 1 2 1U_0201_6.3V6M
+3VALW CC18
@ CLRP2 1 2 SHORT PADS CLR CMOS 10P_0201_50V8J
2
RC377 1 2 1M_0201_5% SM_INTRUDER# SM_INTRUDER# RC62 YC1
A 1M pull-up is used on the customer reference board (CRB). 10M_0201_5% 32.768KHZ_9PF_X1A000141000200
@ This is needed to reduce leakage from Coin Cell Battery in G3 state.
CC319 1 2 0.1U_0201_10V6K SJ10000PW00
UC32
1
5
2
RC427 1 @ 2 1M_0201_5%
EC_RSMRST# 1
P
<58> EC_RSMRST# B EC_RSMRST#_R
4 SOC_RTCX1 1 2
3V/5VALW_PG 2 Y
RC78 1 2 100K_0201_5% PCH_PWROK <58,87,90> 3V/5VALW_PG A
G
MC74VHC1G08EDFT2G_SC70-5 CC17
SA0000BIP00
1
10K_0201_5%
10K_0201_5%
8.2P_0201_50V8B
3
RC4057
RC111
2
2
SOC_XTAL38.4_IN
From EC (Open-Drain) +1.05V_VCCST
@
RC76 RC664 1 2 0_0201_5%
1
1K_0201_5%
B +3VALW RC55 RC54 B
33_0201_5% 33_0201_5%
2
EMI@ EMI@
VCCST_PWRGD RC77 1 2 60.4_0402_1% EC_VCCST_PG
<58> VCCST_PWRGD
2
SOC_XTAL38.4_OUT_R
SOC_XTAL38.4_IN_R
UC23
5
PCH_DPWROK 1
P
<58> PCH_DPWROK B PCH_DPWROK_R
4
VCCST_EN 3V/5VALW_PG 2
A G
Y
MC74VHC1G08EDFT2G_SC70-5
SA0000BIP00 YC2
3
1
10K_0201_5%
+3V_PRIM
1
1 3
10K_0201_5%
RC4056
2 4
RC4060
1 1
RC417 1 2 100K_0201_5% VCCST_OVERRIDE_LS
RC418 1 2 100K_0201_5% VCCST_OVERRIDE_N CC26 38.4MHZ_10PF_XRCGB38M400F2P14R0 CC27
RC419 1 2 100K_0201_5% VCCST_OVERRIDE_R 12P_0201_50V8J 12P_0201_50V8J
2
2 2
2
VCCST_OVERRIDE_LS <16>
VCCST_PWRGD
3
PCH PLTRST
D
+3VALW SOC_PLTRST# RC63 1 @ 2 0_0402_5% PCI_RST#
PCI_RST# <27,34,51,52,58,68>
6
1
To EC VR_ON
1
QC2B RC312
6 S PJT7838_SOT363-6 100K_0201_5%
D 4 SB00001EJ00
3
VGS(Max) : 1 V
2
6
3
PM_SLP_S3# 5 QC1A @ @
D
A G
A
VCCST_OVERRIDE_R 2 PJT138KA_SOT363-6 2 QC5B 5 QC5A
D D
G G
For Glitch , Close to M.2 Con
S
G S PJT138KA_SOT363-6 S PJT138KA_SOT363-6
4
QC2A
S PJT7838_SOT363-6
VGS(Max) : 1 V 1 SB00001EJ00
DC4
<58,97> VR_ON
VR_ON 2 1 PM_SLP_S3# Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2020/0914 Deciphered Date 2021/09/04 Title
TGL-UP3(6/14)CLK,GPIO
RB751V-40_SOD323-2
@ THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
tPLT17 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.A
+3VS
2
DJ23 DG19 TP_INT#
DT18 GPP_C19/I2C1_SCL GPP_U4 TP_INT# <58,63>
N18PG61A@ N18PG61A@ GN20P1@
GPP_C18/I2C1_SDA RC1141 RC1143 RC1143
DJ29 10K_0201_5% 10K_0201_5% 10K_0201_5%
DJ31 GPP_H5/I2C2_SCL
<51,52> PCIE_WAKE# GPP_H4/I2C2_SDA
1
DGPU_SEL1
DF29 DGPU_SEL0
DG29 GPP_H7/I2C3_SCL
GPP_H6/I2C3_SDA
2
DF25 GN20P1@ GN20P0@ GN20P0@
DF27 GPP_H9/I2C4_SCL/CNV_MFUART2_TXD RC1142 RC1142 RC1144
GPP_H8/I2C4_SDA/CNV_MFUART2_RXD 10K_0201_5% 10K_0201_5% 10K_0201_5%
1
TGL-U_BGA1449
@
GPIO Reserve
+3VS
B
teknisi-indonesia.com +3VS
B
1
4.7K_0201_5%
RC278
4.7K_0201_5%
RC277
@ @
GPP_B18
2
No Reboot
INTERNAL PD 20K
SOC_GPP_B18 HIGH: No Reboot
LOW: Reboot Enable (Default)
HDA_SPKR
SPKR
TOP SWAP OVERRIDE
INTERNAL PD 20K
1
20K_0201_5%
RC281
20K_0201_5%
RC282
HIGH: Top swap enable
LOW: Disable (Default)
@ @
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(7/14)GPIO
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.A
UC1I
BT7 REV 1.6 CV4
<51> PCIE_CTX_DRX_P12 PCIE12_TXP/SATA1_TXP USB2P_10 USB20_P10 <52>
BT8 CY3 NGFF WLAN+BT
LAN <51>
<51>
PCIE_CTX_DRX_N12
PCIE_CRX_DTX_P12 CE2 PCIE12_TXN/SATA1_TXN USB2N_10 USB20_N10 <52>
CE1 PCIE12_RXP/SATA1_RXP DD5
<51> PCIE_CRX_DTX_N12 PCIE12_RXN/SATA1_RXN USB2P_9
D DD4 D
BT9 USB2N_9
<67> SATA_CTX_DRX_P0 BV9 PCIE11_TXP/SATA0_TXP CW9
HDD <67> SATA_CTX_DRX_N0 CF4 PCIE11_TXN/SATA0_TXN USB2P_8 DA9
USB20_P8
USB20_N8
<64>
<64>
IT8176
<67> SATA_CRX_DTX_P0 CF3 PCIE11_RXP/SATA0_RXP USB2N_8
<67> SATA_CRX_DTX_N0 PCIE11_RXN/SATA0_RXN DD1
<68> PCIE_CTX_DRX_P10 BV7 USB2P_7 DD2
USB20_P7
USB20_N7
<64>
<64>
KB RGB
BV8 PCIE10_TXP USB2N_7
<68> PCIE_CTX_DRX_N10 PCIE10_TXN
<68> PCIE_CRX_DTX_P10 CG2 DA1
<68> PCIE_CRX_DTX_N10 CG1 PCIE10_RXP USB2P_6 DA2
USB20_P6
USB20_N6
<38>
<38>
Camera
PCIE10_RXN USB2N_6
SSD2 BY7 DA12
2280 <68> PCIE_CTX_DRX_P9
BY8 PCIE9_TXP USB2P_5 DA11
<68> PCIE_CTX_DRX_N9 PCIE9_TXN USB2N_5
<68> PCIE_CRX_DTX_P9 CG5
CG4 PCIE9_RXP DC8
<68> PCIE_CRX_DTX_N9 PCIE9_RXN USB2P_4 DC7
CB8 USB2N_4
<27> PCIE_CTX_DRX_P8 PCIE8_TXP
CB7 DB4
<27> PCIE_CTX_DRX_N8 PCIE8_TXN USB2P_3 USB20_P3 <42>
<27> PCIE_CRX_DTX_P8 CK5 DB3 USB2.0 / 3.0 Port (Type-C)
PCIE8_RXP USB2N_3 USB20_N3 <42>
<27> PCIE_CRX_DTX_N8 CK4
PCIE8_RXN DA5
<27> PCIE_CTX_DRX_P7
CD9 USB2P_2 DA4
USB20_P2
USB20_N2
<71>
<71>
USB2.0 / 3.0 Port (IO - 2)
CD8 PCIE7_TXP USB2N_2
<27> PCIE_CTX_DRX_N7 PCIE7_TXN
<27> PCIE_CRX_DTX_P7 CK1 DC11
PCIE7_RXP USB2P_1 USB20_P1 <71>
<27> PCIE_CRX_DTX_N7 CK2 DC9 USB2.0 / 3.0 Port (IO - 1)
PCIE7_RXN USB2N_1 USB20_N1 <71>
GPU CG8 DP4
<27> PCIE_CTX_DRX_P6 PCIE6_TXP GPP_E0/SATAXPCIE0/SATAGP0
<27> PCIE_CTX_DRX_N6 CG7 DF41
CL4 PCIE6_TXN GPP_A12/SATAXPCIE1/SATAGP1/I2S3_SFRM
<27> PCIE_CRX_DTX_P6 PCIE6_RXP
C CL3 DD8 USB_OC0# C
<27> PCIE_CRX_DTX_N6 PCIE6_RXN GPP_E9/USB_OC0# USB_OC0# <71>
DJ45 USB_OC3#
CJ8 GPP_A16/USB_OC3#/I2S4_SFRM
<27> PCIE_CTX_DRX_P5 PCIE5_TXP
CJ7 DN6
<27> PCIE_CTX_DRX_N5 PCIE5_TXN GPP_E5/DEVSLP1
<27> PCIE_CRX_DTX_P5 CN2 DG8
CN1 PCIE5_RXP GPP_E4/DEVSLP0
<27> PCIE_CRX_DTX_N5 PCIE5_RXN DN29
CR8 GPP_H15/M2_SKT2_CFG3 DK29
<52> PCIE_CTX_DRX_P4 PCIE4_TXP/USB31_4_TXP GPP_H14/M2_SKT2_CFG2
<52> PCIE_CTX_DRX_N4 CR7 DT31
NGFF WLAN+BT <52> PCIE_CRX_DTX_P4 CN5 PCIE4_TXN/USB31_4_TXN GPP_H13/M2_SKT2_CFG1 DR32
CN4 PCIE4_RXP/USB31_4_RXP GPP_H12/M2_SKT2_CFG0
<52> PCIE_CRX_DTX_N4 PCIE4_RXN/USB31_4_RXN DV9 PCIE_RCOMPP RC100 1 2 100_0201_1%
CU8 PCIE_RCOMP_P DT9 PCIE_RCOMPN
<42> USB3_CTX_DRX_P3 PCIE3_TXP/USB31_3_TXP PCIE_RCOMP_N
<42> USB3_CTX_DRX_N3 CU7
Type-C <42> USB3_CRX_DTX_P3 CT2 PCIE3_TXN/USB31_3_TXN DC12 USB2_VBUSSENSE RC354 1 2 10K_0201_1%
CT1 PCIE3_RXP/USB31_3_RXP USB_VBUSSENSE DF1 USB2_ID RC355 1 2 10K_0201_1%
<42> USB3_CRX_DTX_N3 PCIE3_RXN/USB31_3_RXN USB_ID DE1 USB2_COMP RC356 1 2 113_0201_1%
CW8 USB2_COMP
<71> USB3_CTX_DRX_P2 PCIE2_TXP/USB31_2_TXP
CW7 E3 RSVD_BDCAN 1 T328
<71> USB3_CTX_DRX_N2 PCIE2_TXN/USB31_2_TXN RSVD_BSCAN TP@
USB2.0 / 3.0 Port (IO - 2) <71> USB3_CRX_DTX_P2 CU3
CT4 PCIE2_RXP/USB31_2_RXP
<71> USB3_CRX_DTX_N2 PCIE2_RXN/USB31_2_RXN
DA8 +3V_PRIM
<71> USB3_CTX_DRX_P1 PCIE1_TXP/USB31_1_TXP USB_OC0# Strap refer RVP
<71> USB3_CTX_DRX_N1 DA7
USB2.0 / 3.0 Port (IO - 1) <71> USB3_CRX_DTX_P1 CV2 PCIE1_TXN/USB31_1_TXN USB_OC0# RC401 1 2 10K_0201_5%
CV1 PCIE1_RXP/USB31_1_RXP USB_OC3# RC403 1 2 10K_0201_5%
<71> USB3_CRX_DTX_N1 PCIE1_RXN/USB31_1_RXN
TGL-U_BGA1449
@ check list needs stuff even un-use
B B
UC1H
P5 REV 1.6 V5
<68> PCIE4_CTX_DRX_P3 PCIE4_TX_P_3 PCIE4_TX_P_1 PCIE4_CTX_DRX_P1 <68>
P7 V7
<68> PCIE4_CTX_DRX_N3 PCIE4_TX_N_3 PCIE4_TX_N_1 PCIE4_CTX_DRX_N1 <68>
N1 T1
<68> PCIE4_CRX_DTX_P3 PCIE4_RX_P_3 PCIE4_RX_P_1 PCIE4_CRX_DTX_P1 <68>
N2 T2
<68> PCIE4_CRX_DTX_N3 PCIE4_RX_N_3 PCIE4_RX_N_1 PCIE4_CRX_DTX_N1 <68>
SSD1 T5 Y5
SSD2
2242 <68> PCIE4_CTX_DRX_P2 T7 PCIE4_TX_P_2 PCIE4_TX_P_0 Y7
PCIE4_CTX_DRX_P0 <68> 2242
<68> PCIE4_CTX_DRX_N2 PCIE4_TX_N_2 PCIE4_TX_N_0 PCIE4_CTX_DRX_N0 <68>
R1 V1
<68> PCIE4_CRX_DTX_P2 PCIE4_RX_P_2 PCIE4_RX_P_0 PCIE4_CRX_DTX_P0 <68>
R2 V2
<68> PCIE4_CRX_DTX_N2 PCIE4_RX_N_2 PCIE4_RX_N_0 PCIE4_CRX_DTX_N0 <68>
Y12 PCIE4_RCOMPP RC188 1 2 2.2K_0201_1%
PCIE4_RCOMP_P V12 PCIE4_RCOMPN
PCIE4_RCOMP_N
TGL-U_BGA1449
A A
@
UC1J
REV 1.6
D22 DK47 CNV_CTX_DRX_P1 <52>
B22 CSI_F_DP_1 CNVI_WT_D1P DM47
CSI_F_DN_1 CNVI_WT_D1N CNV_CTX_DRX_N1 <52>
E22 DN49 CNV_CTX_DRX_P0 <52>
D20 CSI_F_DP_0 CNVI_WT_D0P DR49
CSI_F_DN_0 CNVI_WT_D0N CNV_CTX_DRX_N0 <52>
A20 DN45 CLK_CNV_CTX_DRX_P <52>
B20 CSI_F_CLK_P CNVI_WT_CLKP DN47
D CLK_CNV_CTX_DRX_N <52> D
CSI_F_CLK_N CNVI_WT_CLKN
B18 DU43
CSI_E_DP_1/CSI_F_DP_2 CNVI_WR_D1P CNV_CRX_DTX_P1 <52>
A18 DV43
CSI_E_DN_1/CSI_F_DN_2 CNVI_WR_D1N CNV_CRX_DTX_N1 <52>
D18 DR44
CSI_E_DP_0/CSI_F_DP_3 CNVI_WR_D0P CNV_CRX_DTX_P0 <52>
E18 DT43
CSI_E_DN_0/CSI_F_DN_3 CNVI_WR_D0N CNV_CRX_DTX_N0 <52>
C16 DV44
CSI_E_CLK_P CNVI_WR_CLKP CLK_CNV_CRX_DTX_P <52>
D16 DW44
CSI_E_CLK_N CNVI_WR_CLKN CLK_CNV_CRX_DTX_N <52>
D15 DN51 CNV_WT_RCOMP RC109 1 2 150_0201_1%
E15 CSI_C_DP_2 CNVI_WT_RCOMP
A15 CSI_C_DN_2 DJ13
CSI_C_DP_3 GPP_F3/CNV_RGI_RSP/UART0_CTS# CNV_RGI_CRX_DTX <52>
B15 DG13 CNV_RGI_CTX_DRX <52>
CSI_C_DN_3 GPP_F2/CNV_RGI_DT/UART0_TXD DF15
GPP_F1/CNV_BRI_RSP/UART0_RXD CNV_BRI_CRX_DTX <52>
L18 DF17 CNV_BRI_CTX_DRX <52>
N18 CSI_C_DP_1 GPP_F0/CNV_BRI_DT/UART0_RTS#
L20 CSI_C_DN_1 DJ10 SOC_GPP_F5 1
CSI_C_DP_0 GPP_F5/MODEM_CLKREQ/CRF_XTAL_CLKREQ TP@ T53
N20 DV15
G20 CSI_C_DN_0 GPP_F6/CNV_PA_BLANKING DK10 SOC_GPP_F4
H20 CSI_C_CLK_P GPP_F4/CNV_RF_RESET#
CSI_C_CLK_N
H16
G16 CSI_B_DP_1
G18 CSI_B_DN_1
H18 CSI_B_DP_0
L16 CSI_B_DN_0
C
N16 CSI_B_CLK_P CNV_RGI_CTX_DRX (M.2 CNVI MODES) C
CSI_B_CLK_N
0 = Integrated CNVi enable. +1.8V_PRIM
G14
H14 CSI_B_DP_2 1 = Integrated CNVi disable.
CSI_B_DN_2 CNV_RGI_CTX_DRX RC1140 1 2 100K_0201_5%
L14
CSI_B_DP_3
N14
CSI_B_DN_3 PD on CNVi Card
RC357 1 2 150_0201_1% CSI_RCOMP K14
CSI_RCOMP
+1.8V_PRIM
DK25
DM25 GPP_H23/IMGCLKOUT4
GPP_H22/IMGCLKOUT3 CNV_BRI_CRX_DTX RC181 1 @ 2 20K_0201_5%
DN25 CNV_RGI_CRX_DTX
GPP_H21/IMGCLKOUT2 RC182 1 @ 2 20K_0201_5%
DJ25
DR30 GPP_H20/IMGCLKOUT1
GPP_D4/IMGCLKOUT_0/BK4/SBK4
+1.8V_PRIM
TGL-U_BGA1449
@
1
RC227
4.7K_0201_5%
@
CNV_BRI_CTX_DRX (XTAL SEL)
2
B B
1
WEAK INTERNAL PD 20K RC644
20K_0201_5%
@
2
SOC_GPP_F4
1
RC627
75K_0201_5%
@
2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(9/14)CSI,CNV
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.A
+VCCIN +VCCIN
D D
UC1M EMI CAPS-PLACE
A24
VCCIN_1
REV 1.6
VCCIN_66
G32 < 5mm from SOC VCCIN
A26 H24 +VCCIN
A29 VCCIN_2 VCCIN_67 H26
A30 VCCIN_3 VCCIN_68 H30
A33 VCCIN_4 VCCIN_69 H32
A35 VCCIN_5 VCCIN_70 J1
0.1U_0201_10V6K
CC375
12P_0201_50V8J
CC376
100P_0201_50V8J
CC377
VCCIN_6 VCCIN_71 1 1 1
AY39 J2
B24 VCCIN_7 VCCIN_72 K1
B26 VCCIN_8 VCCIN_73 K2
B29 VCCIN_9 VCCIN_74 K24 2 2 2
EMI@
EMI@
EMI@
B30 VCCIN_10 VCCIN_75 K26
B33 VCCIN_11 VCCIN_76 K30
B35 VCCIN_12 VCCIN_77 K32
BA10 VCCIN_13 VCCIN_78 L24
BA40 VCCIN_14 VCCIN_79 L26
BB39 VCCIN_15 VCCIN_80 L30
BB9 VCCIN_16 VCCIN_81 L32
BC10 VCCIN_17 VCCIN_82 N24
BC40 VCCIN_18 VCCIN_83 N26
BD39 VCCIN_19 VCCIN_84 N30
BD9 VCCIN_20 VCCIN_85 N32
BE10 VCCIN_21 VCCIN_86 P24 +1.05V_VCCST
BE40 VCCIN_22 VCCIN_87 P26
C C
BF9 VCCIN_23 VCCIN_88 P28
VCCIN_24 VCCIN_89
1
BG10 P30
BG40 VCCIN_25 VCCIN_90 P32 RC148
BH12 VCCIN_26
VCCIN_27
VCCIN_91
VCCIN_92
T21 SVID DATA 100_0201_1%
BH39 T23
BH9 VCCIN_28 VCCIN_93 T25
VCCIN_29 VCCIN_94
2
BJ10 T27
BJ40 VCCIN_30 VCCIN_95 T31 SOC_SVID_DAT RC362 1 @ 2 0_0201_5% SOC_SVID_DAT_R
VCCIN_31 VCCIN_96 SOC_SVID_DAT_R <97>
BK39 U23
BL10 VCCIN_32 VCCIN_97 U27
BL40 VCCIN_33 VCCIN_98 U29
BM39 VCCIN_34 VCCIN_99 U31 +1.05V_VCCST
BN40 VCCIN_35 VCCIN_100 U33
BP12 VCCIN_36 VCCIN_101 V23
VCCIN_37 VCCIN_102
1
BP39 V25
BR10 VCCIN_38 VCCIN_103 V27 RC146
BR40 VCCIN_39
VCCIN_40
VCCIN_104
VCCIN_105
V29 SVID ALERT 56_0201_1%
BT12 V31
BT39 VCCIN_41 VCCIN_106 V33
VCCIN_42 VCCIN_107
2
BU10 W22
BU40 VCCIN_43 VCCIN_108 W24 SOC_SVID_ALERT# RC363 1 @ 2 0_0201_5% SOC_SVID_ALERT#_R
VCCIN_44 VCCIN_109 SOC_SVID_ALERT#_R <97>
BV12 W28
BY12 VCCIN_45 VCCIN_110 W32
CA10 VCCIN_46 VCCIN_111
CB12 VCCIN_47 R38
B VCCIN_48 VCCIN_SENSE VCCIN_VCCSENSE <97> +1.05V_VCCST B
D24 R37
VCCIN_49 VSSIN_SENSE VCCIN_VSSSENSE <97>
D26
D29 VCCIN_50 M12 SOC_SVID_DAT
D30 VCCIN_51 VIDSOUT M11 SOC_SVID_CLK
VCCIN_52 VIDSCK
1
D33 P12 SOC_SVID_ALERT#
D35 VCCIN_53
VCCIN_54
VIDALERT# SVID CLOCK RC147
E24 100_0201_1%
E26 VCCIN_55 @
E27 VCCIN_56
VCCIN_57
2
E29
E30 VCCIN_58 SOC_SVID_CLK RC364 1 @ 2 0_0201_5% SOC_SVID_CLK_R
VCCIN_59 SOC_SVID_CLK_R <97>
E32
E33 VCCIN_60
G2 VCCIN_61
G24 VCCIN_62
G26 VCCIN_63
G30 VCCIN_64
VCCIN_65
TGL-U_BGA1449
@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(10/14)Power, SVID
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.A
+1.05VS_VCCSTG_OUT_FUSE
EMI CAPS-PLACE +1.2V UC1O
+1.05VS_VCCSTG_FUSE
< 4mm from SOC VDDQ REV 1.6
AF9
+1.05VS_VCCSTG_OUT_FUSE +1.05VS_VCCSTG_FUSE
VCCSTG_OUT_1
with each pair < 12mm Apart +1.2V +1.2V +1.2V AA39
AB40 VDD2_1 VCCSTG_1
AF12
AD12 +VCCFPGM
VDD2_2 VCCSTG_2 RC239 1 @ 2 0_0402_5%
12pF* 3 (EMI@) AC39
AD40 VDD2_3 AN10 +VCCFPGM
2.2P_0201_50V8C
CC218
12P_0201_50V8J
CC219
2.2P_0201_50V8C
CC220
12P_0201_50V8J
CC221
2.2P_0201_50V8C
CC222
12P_0201_50V8J
CC223
2.2pF* 3 (EMI@) AD51
AD52
VDD2_4
VDD2_5
VCCSTG_OUT_2
VCCSTG_OUT_3
AM9
AG10 +1.05V_VCCIO_OUT
1 1 1 1 1 1 VDD2_6 VCCSTG_OUT_4 RC240 1 @ 2 0_0402_5%
AE39 +1.05VS_VCCSTG_OUT_LGC
D AF40 VDD2_7 V15 1 D
VDD2_8 VCCIO_OUT TP@ T60
AG39
EMI@
EMI@
EMI@
EMI@
EMI@
EMI@
2 2 2 2 2 2 AH40 VDD2_9 M9 +1.05V_VCCST
AJ39 VDD2_10 VCCSTG_OUT_LGC
AK40
AK51
VDD2_11
VDD2_12 VCCST_1
BT2
BT1 +1.8VALW TO +1.8V_PRIM
AK52 VDD2_13 VCCST_2 BT4 +1.05VS_VCCSTG
AL39 VDD2_14 VCCST_3
AM40 VDD2_15 BP2
VDD2_16 VCCSTG_3 +1.8VALW +1.8V_PRIM
AN39 BP1
AP40 VDD2_17 VCCSTG_4 BP4
VDD2_18 VCCSTG_5 RC243 1 @ 2 0_0603_5%
AR39
AT52 VDD2_19
AU40 VDD2_20 1
AW40 VDD2_21 CC753
VDD2_22 4.7U_0402_6.3V6M
AW51
AW52 VDD2_23
VDD2_24 2
BD51
BD52 VDD2_25
BK51 VDD2_26
BK52 VDD2_27
BV51 VDD2_28
+1.05VO_OUT_FET BV52 VDD2_29
+1.05VS_VCCSTG CA40 VDD2_30
CC40 VDD2_31
+1.05VS_VCCSTG_R RC622 1 @ 2 0_0402_5% CC49 VDD2_32
CC50
CE40
VDD2_33
VDD2_34
RF
1U_0201_6.3V6M
CC750
Imax : 0.445 A 1 Imax : 0.445 A 1 +1.2V +1.05V_VCCST +1.05VS_VCCSTG +1.05VS_VCCSTG_OUT_FUSE +1.05VS_VCCSTG_FUSE +VCCFPGM
CC60 CG40 VDD2_35
CH39 VDD2_36
VCCSTG
0.1U_0201_10V6K
CJ40 VDD2_37
1U_0201_6.3V6M
2 2 VDD2_38
1U_0201_6.3V6M
1U_0201_6.3V6M
CL40
CC29 @
2
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
CC56 @
CC57 @
+5VALW CN40 VDD2_39 2 2
CC55 @
UC5 2 2 2 2
1 10 CP47 VDD2_40
10P_0201_50V8J
0 for 65us
CC52
CC53
CC54
2 2
10P_0201_50V8J
IN1 OUT1 CR40 VDD2_41
CC789
CC58
CC790
0.1U_0201_10V6K VCCSTG_EN_LS 2 9 CC62 1 @ 2 1000P_0402_50V7K D50 VDD2_42 1
EN1 CT1 VDD2_43 1 1
2 1 @ 3 8 E51 1 1 1 1
RF@
VCCST_EN_LS 4 VBIAS GND 7 CC63 1 @ 2 1000P_0402_50V7K +1.05V_VCCST F49 VDD2_44 1 1
RF@
EN2 CT2 T51 VDD2_45
C
5 6 +1.05V_VCCST_R RC619 1 @ 2 0_0402_5% T52 VDD2_46 C
IN2 OUT2 VDD2_47
11 Imax : 0.119 A 1
+1.05VO_OUT_FET GND PAD CC61 TGL-U_BGA1449
0.1U_0201_10V6K @
G2894KD1U TDFN2X3_14
2
SA0000D5C00
1U_0201_6.3V6M
CC59
2
VCCST
RDS(on) = 20mΩ at VIN = 1.05V (VBIAS = 5V) Place on CPU Side www.teknisi-indonesia.com
10μs <= EN asserted to VOUT stable <= 65μs 1uF* 10
CPU_C10_GATE# stable to +1.05VS_VCCSTG <= 65us (tCPU26) 10uF* 16
47uF * 2
+1.2V +1.2V +1.2V
Close to UC5
CC761
22U_0603_6.3V6M
CC760
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
+1.05V_VCCST +1.05VS_VCCSTG 1 1 1 1 1 1 1 1 1 1 1 1
CC77
CC78
CC79
CC80
CC81
CC403
CC404
CC405
CC409
CC410
CC406
CC407
CC408
CC411
CC402
CC92
CC67
CC68
CC69
CC70
CC71
CC72
CC73
CC74
CC75
CC401
1 1 @ @ @ @ 2 @2 2 @2 @2 @2 @2 @2 @2 2 2 @2 2 @2 @2 2
CC754 CC755 2 2 2 2 2 2 2 2 2 2 2 2
0.1U_0201_10V6K 0.1U_0201_10V6K
@RF@ @RF@
2 2
B B
VCCST/VCCSTG Enable
DC7
@
SUSP# RC303 1 2 0_0201_5% 2
<40,58,78,110> SUSP# VCCST_EN_LS
1
3
LRB715FT1G_SOT323-3
DC8
2
1 VCCSTG_EN_LS
CPU_C10_GATE# RC331 1 @ 2 0_0201_5% 3
<11> CPU_C10_GATE#
LRB715FT1G_SOT323-3
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(11/14)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.A
Package size
+3VALW +3VALW_DSW +3VALW TO +3V_PRIM +3V_PRIM +3V_PRIM +3.3V_VCCPGPPR EMI CAPS-PLACE
RC6081 @ 2 0_0402_5%
< 5mm from SOC VCCIN_AUX
RC216 1 @ 2 0_0402_5% +3VALW +3V_PRIM 1
215mA +VCCIN_AUX
CC168
RC643 1 @ 2 0_0402_5%
@ 4.7U_0402_6.3V6M
2
1
0.1U_0201_10V6K
CC99
12P_0201_50V8J
CC98
100P_0201_50V8J
CC100
2.2P_0201_50V8C
CC97
1 1 1 1
D CC101 D
4.7U_0402_6.3V6M
2
2 2 2 2
EMI@
EMI@
EMI@
@
+1.8V_PRIM +1.8V_VCCA_CLKLDO
RC2181 @ 2 0_0402_5%
CC741
22U_0603_6.3V6M
CC246
22U_0603_6.3V6M
1 1
+VCCIN_AUX +1.8V_PRIM
UC1N
@
2 2 REV 1.6
AB12 CY18
AC10 VCCIN_AUX_1 VCCPRIM_1P8_1 CY20
AE10 VCCIN_AUX_2 VCCPRIM_1P8_2 CY24
AK2 VCCIN_AUX_3 VCCPRIM_1P8_3 CY26
AR10 VCCIN_AUX_4 VCCPRIM_1P8_4 DA18
AT12 VCCIN_AUX_5 VCCPRIM_1P8_5 DA20
AU10 VCCIN_AUX_6 VCCPRIM_1P8_6 DA22
AW10 VCCIN_AUX_7 VCCPRIM_1P8_7 DA24
BV1 VCCIN_AUX_8 VCCPRIM_1P8_8 DA26
BV39 VCCIN_AUX_9 VCCPRIM_1P8_9 DC18
BW40 VCCIN_AUX_10 VCCPRIM_1P8_10 DC20
BY39 VCCIN_AUX_11 VCCPRIM_1P8_11 DC22
CC1 VCCIN_AUX_12 VCCPRIM_1P8_12 DC24
CD12 VCCIN_AUX_13 VCCPRIM_1P8_13 DC26
CF10 VCCIN_AUX_14 VCCPRIM_1P8_14 DD20
CG12 VCCIN_AUX_15 VCCPRIM_1P8_15 DD22
+1.05VO_VNNBYPASS CH10 VCCIN_AUX_16 VCCPRIM_1P8_16 DV22 +3V_PRIM
CJ1 VCCIN_AUX_17 VCCPRIM_1P8_17
C C
CJ12 VCCIN_AUX_18 DA35 +VO_VCCDCPRTC
CK10 VCCIN_AUX_19 VCCPRIM_3P3_1 DC28
+1.05VO_EXTBYPASS CL12 VCCIN_AUX_20 VCCPRIM_3P3_2 DC30
CM10 VCCIN_AUX_21 VCCPRIM_3P3_3 DD30
RC601
100K_0201_5%
1 CP1 VCCIN_AUX_22 VCCPRIM_3P3_4 +0.85VO_VCCLDOSTD
CP10 VCCIN_AUX_23 DV34
CR12 VCCIN_AUX_24 DCPRTC
@ CT10 VCCIN_AUX_25 DV46 +1.8V_VCCA_CLKLDO
CU12 VCCIN_AUX_26 VCCLDOSTD_0P85
RC600
100K_0201_5%
VCCIN_AUX_27
2
1
DD38 +1.05VO_OUT_FET
DD17 VCCDSW_1P05
DD18 VCC_VNNEXT_1P05_1 BR3
VCC_VNNEXT_1P05_2 VCC1P05_OUT_FET BR4
DA15 VCC1P05_OUT_FET BT5 +1.05VO_OUT_PCH
DA17 VCC_V1P05EXT_1P05_1 VCC1P05_OUT_FET
VCC_V1P05EXT_1P05_2 DA31 +3VL_RTC
RC222 1 @ 2 0_0201_5% VCCIN_AUX_CORE_ALERT# DB39 VCCPRIM_1P05_1 DC33
<7> VCCIN_AUX_CORE_ALERT#_R VNN_CTRL GPP_B2/VRALERT# VCCPRIM_1P05_2
1 DV12 DC31 +3VALW_DSW
T194 TP@ 1 V1.05P_CTRL DT12 GPP_F22/VNN_CTRL VCCPRIM_1P05_3
T195 TP@ GPP_F23/V1P05_CTRL DC35 +3.3V_VCCPGPPR
RC223 1 @ 2 0_0201_5% VCCIN_AUX_CORE_VID0 DB37 VCCRTC DD37
<95> VCCIN_AUX_CORE_VID0_R GPP_B0/CORE_VID0 VCCDSW_3P3
RC224 1 @ 2 0_0201_5% VCCIN_AUX_CORE_VID1 DB38 DA28 +3V_PRIM
<95> VCCIN_AUX_CORE_VID1_R GPP_B1/CORE_VID1 VCCPGPPR ?
CY31
? +1.8V_PRIM
VCCPRIM_3P3_5 CY33
VCCPRIM_3P3_6 CV39 +VCCANA_EHV
VCCPRIM_1P8_18
AP12 1 TP@T84
RSVD_1
B TGL-U_BGA1449 B
@
NOTE:
576591-tgl-pch-lp-eds-vol1of2-rev0p5
VCCPGPPR: Audio Power 3.3V, 1.8V, or 1.5V
Need to sync with codec VDDIO.
607872_TGL_UY_PDG_Rev0p5
When configured as 3.3V or 1.8V, VCCPGPPR can be merged directly with
either VCCPRIM_1P8 or VCCPRIM_3P3 depending on their operating voltage.
1U_0201_6.3V6M
CC745
2.2U_0402_6.3V6M
CC747
1U_0201_6.3V6M
CC743
0.1U_0201_10V6K
CC749
1 1 1
4.7U_0402_6.3V6M
CC746
1
0.1U_0201_10V6K
CC748
1U_0201_6.3V6M
CC744
1
1
RC141 2 @ 1 0_0402_5%
2 2 2
2
1U_0201_6.3V6M
CC258
0.1U_0201_10V6K
CC129
2 1 1
2
@
@
2 2
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(12/14)Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.A
UC1R
UC1P
REV 1.6
UC1Q REV 1.6
D REV 1.6 DP53 K34 D
A27 B19 VSS_2 VSS_46
VSS_223 VSS_289 BY44 CY44 DR11 K48
A32 B2 VSS_109 VSS_169 VSS_3 VSS_47
VSS_224 VSS_290 BY45 CY45 DR16 K5
A45 B23 VSS_110 VSS_170 VSS_4 VSS_48
VSS_225 VSS_291 BY47 CY47 DR22 L22
A49 B27 VSS_111 VSS_171 VSS_5 VSS_49
VSS_226 VSS_292 BY49 CY5 DR28 L28
AA41 B32 VSS_112 VSS_172 VSS_6 VSS_50
VSS_227 VSS_293 BY9 D27 DR34 L34
AA48 B36 VSS_113 VSS_173 VSS_7 VSS_51
VSS_228 VSS_294 C13 D32 DR40 L39
AB5 B39 VSS_114 VSS_174 VSS_8 VSS_52
VSS_229 VSS_295 C19 D36 DR46 L41
AB7 B42 VSS_115 VSS_175 VSS_9 VSS_53
VSS_230 VSS_296 C23 D42 DT4 L42
AB8 B48 VSS_116 VSS_176 VSS_10 VSS_54
VSS_231 VSS_297 CA48 D49 DT50 L44
AC44 B52 VSS_117 VSS_177 VSS_11 VSS_55
VSS_232 VSS_298 CB41 D5 DU11 L45
AC49 B8 VSS_118 VSS_178 VSS_12 VSS_56
VSS_233 VSS_299 CC10 DA30 DU16 L47
AD4 BA48 VSS_119 VSS_179 VSS_13 VSS_57
VSS_234 VSS_300 CC3 DA33 DU22 L49
AD48 BA53 VSS_120 VSS_180 VSS_14 VSS_58
VSS_235 VSS_301 CC5 DA53 DU28 M1
AD8 BB4 VSS_121 VSS_181 VSS_15 VSS_59
VSS_236 VSS_302 CD44 DC17 DU34 M2
AF4 BB8 VSS_122 VSS_182 VSS_16 VSS_60
VSS_237 VSS_303 CD48 DD15 DU40 M50
AF8 BC1 VSS_123 VSS_183 VSS_17 VSS_61
VSS_238 VSS_304 CD7 DD24 DU46 N22
AG41 BC2 VSS_124 VSS_184 VSS_18 VSS_62
VSS_239 VSS_305 CE49 DD26 DV1 N28
AG42 BD12 VSS_125 VSS_185 VSS_19 VSS_63
VSS_240 VSS_306 CG48 DD28 DV40 N34
AG44 BD4 VSS_126 VSS_186 VSS_20 VSS_64
VSS_241 VSS_307 CG51 DD31 DV52 N39
AG45 BD48 VSS_127 VSS_187 VSS_21 VSS_65
VSS_242 VSS_308 CG52 DD33 DW51 N41
AG47 BD8 VSS_128 VSS_188 VSS_22 VSS_66
VSS_243 VSS_309 CG9 DD35 E13 N48
AG48 BF39 VSS_129 VSS_189 VSS_23 VSS_67
VSS_244 VSS_310 CH41 DD39 E19 P11
AG53 BF4 VSS_130 VSS_190 VSS_24 VSS_68
VSS_245 VSS_311 CH42 DD45 E35 P14
AH4 BF41 VSS_131 VSS_191 VSS_25 VSS_69
VSS_246 VSS_312 CH44 DD51 E48 P16
AH8 BF42 VSS_132 VSS_192 VSS_26 VSS_70
VSS_247 VSS_313 CH45 DD52 G22 P18
AK12 BF44 VSS_133 VSS_193 VSS_27 VSS_71
VSS_248 VSS_314 CH47 DE3 G28 P20
AK4 BF45 VSS_134 VSS_194 VSS_28 VSS_72
VSS_249 VSS_315 CJ3 DE5 G34 P22
AK48 BF47 VSS_135 VSS_195 VSS_29 VSS_73
VSS_250 VSS_316 CJ5 DF19 G39 P33
AK5 BF5 VSS_136 VSS_196 VSS_30 VSS_74
C VSS_251 VSS_317 CJ9 DF37 G48 P35 C
AK7 BF7 VSS_137 VSS_197 VSS_31 VSS_75
VSS_252 VSS_318 CK39 DG15 G51 P4
AK8 BF8 VSS_138 VSS_198 VSS_32 VSS_76
VSS_253 VSS_319 CK48 DG21 G52 P49
AM1 BG48 VSS_139 VSS_199 VSS_33 VSS_77
VSS_254 VSS_320 CK53 DG27 H12 P8
AM2 BG53 VSS_140 VSS_200 VSS_34 VSS_78
VSS_255 VSS_321 CL9 DG33 H22 R39
AM4 BH1 VSS_141 VSS_201 VSS_35 VSS_79
VSS_256 VSS_322 CN12 DG39 H28 R44
AM8 BH2 VSS_142 VSS_202 VSS_36 VSS_80
VSS_257 VSS_323 CN48 DG45 H34 T19
AN41 BH4 VSS_143 VSS_203 VSS_37 VSS_81
VSS_258 VSS_324 CN51 DG5 H8 T29
AN42 BH8 VSS_144 VSS_204 VSS_38 VSS_82
VSS_259 VSS_325 CN52 DG53 J39 T33
AN44 BK12 VSS_145 VSS_205 VSS_39 VSS_83
VSS_260 VSS_326 CN9 DG6 J49 T4
AN45 BK4 VSS_146 VSS_206 VSS_40 VSS_84
VSS_261 VSS_327 CP3 DJ1 K16 T48
AN47 BK48 VSS_147 VSS_207 VSS_41 VSS_85
VSS_262 VSS_328 CP41 DJ2 K18 T8
AN48 BK8 VSS_148 VSS_208 VSS_42 VSS_86
VSS_263 VSS_329 CP42 DJ4 K20 U19
AN53 BL49 VSS_149 VSS_209 VSS_43 VSS_87
VSS_264 VSS_330 CP44 DK51 K22 U25
AP4 BM1 VSS_150 VSS_210 VSS_44 VSS_88
VSS_265 VSS_331 CP45 DL3 K28 U39
AP8 BM4 VSS_151 VSS_211 VSS_45 VSS_89
VSS_266 VSS_332 CP5 DL5 U49
AT4 BM41 VSS_152 VSS_212 VSS_90
VSS_267 VSS_333 CR48 DM10 V19
Follow AT48 BM42
CR53 VSS_153 VSS_213 DM15 VSS_91 V4
AT51 VSS_268 VSS_334 BM44
612304_TGL_UP3_LPDDR4x_RVP_TDK_Rev0p7 VSS_269 VSS_335 CR9 VSS_154 VSS_214 DM21 VSS_92 V8
AT8 BM45 VSS_155 VSS_215 VSS_93
VSS_270 VSS_336 CT5 DM27 W1
T85 TP@ 1 AV12 BM47 VSS_156 VSS_216 VSS_94
VSS_271 VSS_337 CU4 DM33 W16
AV39 BM8 VSS_157 VSS_217 VSS_95
VSS_272 VSS_338 CU9 DM39 W26
AV4 BN48 VSS_158 VSS_218 VSS_96
VSS_273 VSS_339 CV10 DM4 W30
AV5 BP41 VSS_159 VSS_219 VSS_97
VSS_274 VSS_340 CV48 DM45 W39
AV7 BP49 VSS_160 VSS_220 VSS_98
VSS_275 VSS_341 CV5 DN1 W41
AV8 BP5 VSS_161 VSS_221 VSS_99
VSS_276 VSS_342 CV51 DN2 W42
AW1 BP50 VSS_162 VSS_222 VSS_100
VSS_277 VSS_343 CV52 W44
AW2 BP7 VSS_163 VSS_101
VSS_278 VSS_344 CY17 W45
AW48 BT44 VSS_164 VSS_102
VSS_279 VSS_345 CY22 W47
B AY4 BT48 VSS_165 VSS_103 B
VSS_280 VSS_346 CY35 W48
AY41 BU49 VSS_166 VSS_104
VSS_281 VSS_347 CY41 Y4
AY42 BV3 VSS_167 VSS_105
VSS_282 VSS_348 CY42 Y49
AY44 BV48 VSS_168 VSS_106
VSS_283 VSS_349 Y50
AY45 BV5 VSS_107
VSS_284 VSS_350 Y8
AY47 BW10 TGL-U_BGA1449 VSS_108
AY8 VSS_285 VSS_351 BY41
VSS_286 VSS_352 @
AY9 BY42 TGL-U_BGA1449
B13 VSS_287 VSS_353
VSS_288 @
TGL-U_BGA1449
@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(13/14)GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.A
D UC1T D
REV 1.6
T15 A51
CFG14 V17 CFG_15 RSVD_TP_7 B51
U15 CFG_14 RSVD_TP_8
K11 CFG_13 C1
CFG11 K12 CFG_12 RSVD_TP_9 D2
CFG10 K9 CFG_11 RSVD_TP_10
CFG9 T17 CFG_10 CP39
K7 CFG_9 RSVD_TP_11 CU40
CFG7 H7 CFG_8 RSVD_TP_12 AK9
K8 CFG_7 RSVD_12
H9 CFG_6 AH9
CFG Signals CFG_5 RSVD_13
CFG4 E6
(For Strap & XDP) CFG3 H5 CFG_4 DW6
CFG2 E9 CFG_3 RSVD_14 DV6
CFG1 D9 CFG_2 RSVD_15
E7 CFG_1 DV4
CFG_0 RSVD_TP_13 DW3
CFG_RCOMP B5 RSVD_TP_14
CFG_RCOMP DU1
RSVD_TP_15
1
U17 DT2
RC228 H11 CFG_17 RSVD_TP_16
49.9_0201_1% CFG_16 DW2
Y1 RSVD_TP_17 DV2
M4 BPM#_3 RSVD_TP_18
BPM#_2
2
AB4 E1
RC233 1 2 1K_0201_5% CFG4 Y2 BPM#_1 RSVD_TP_19 F1
BPM#_0 RSVD_TP_20
C C
A3 AB2
B3 RSVD_6 RSVD_16
CFG4 RSVD_7
Display port presence strap DR1
TCSS_RCOMP AR2 RSVD_TP_21 DR2
LOW : Enable TCP0_MBIAS_RCOMP RSVD_TP_22
An external display port device is connected to AL10
RSVD_TP_2
1
AM12 DR53
the embedded displayport RC335 AH12 RSVD_TP_3 RSVD_TP_23 DW5
HIGH : Disable AJ10 RSVD_TP_4 RSVD_TP_24
2.2K_0201_1%
No physical display port attached to embedded display port AR1 RSVD_TP_5 DV51
RSVD_TP_6 VSS_1 DW52
TP_3
2
BN10 DV53
BM12 RSVD_8 TP_4 W34
DD13 RSVD_9 RSVD_17 V35
DF13 RSVD_10 RSVD_18
+1.05V_VCCIO_OUT RSVD_11 D52 SKTOCC# 1
SKTOCC# TP@ T112
TGL-U_BGA1449
@
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TGL-UP3(14/14)RSVD,CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
Non-Interleaved Memory
<8> DDR_M0_CLK#0 DDR_M0_CLK1 CK0#(C) DQ1 DDR_M0_D56
<8> DDR_M0_CLK1
138 20
DDR_M0_CLK#1 140 CK1(T) DQ2 21 DDR_M0_D59
<8> DDR_M0_CLK#1 CK1#(C) DQ3 DDR_M0_D60
4
DDR_M0_CKE0 109 DQ4 3 DDR_M0_D62
TOP: JDIMM1 CONN Non-ECC DIMM <8> DDR_M0_D[0..15]
<8>
<8>
DDR_M0_CKE0
DDR_M0_CKE1
DDR_M0_CKE1 110 CKE0
CKE1
DQ5
DQ6
DQ7
16
17
DDR_M0_D61
DDR_M0_D57
DDR_M0_CS#0 149 13 DDR_M0_DQS7
<8> DDR_M0_CS#0 DDR_M0_CS#1 S0# DQS0(T) DDR_M0_DQS#7 DDR_M0_DQS7 <8>
157 11
+3VS +3VS +3VS <8> DDR_M0_D[16..31] <8> DDR_M0_CS#1 S1# DQS0#(C) DDR_M0_DQS#7 <8>
162
165 S2#/C0 28 DDR_M0_D51
<8> DDR_M0_D[32..47] S3#/C1 DQ8 DDR_M0_D53
29
DQ9
1
1
D DDR_M0_ODT0 155 41 DDR_M0_D49 D
<8> DDR_M0_D[48..63] <8> DDR_M0_ODT0 DDR_M0_ODT1 ODT0 DQ10 DDR_M0_D54
RD3 RD4 RD5 161 42
<8> DDR_M0_ODT1 ODT1 DQ11 DDR_M0_D48
@ 0_0402_5% @ 0_0402_5% @ 0_0402_5% 24
JDIMM1B DDR_M0_BG0 115 DQ12 25 DDR_M0_D52
<8> DDR_M0_BG0 DDR_M0_BG1 BG0 DQ13 DDR_M0_D55
REVERSE 113 38
<8> DDR_M0_BG1 BG1 DQ14
2
2
SA0_CHA_DIM1 SA1_CHA_DIM1 SA2_CHA_DIM1 111 141 DDR_M0_BA0 150 37 DDR_M0_D50
+1.2V 112 VDD1 VDD11 142
+1.2V <8> DDR_M0_BA0 DDR_M0_BA1 145 BA0 DQ15 34 DDR_M0_DQS6
VDD2 VDD12 <8> DDR_M0_BA1 BA1 DQS1(T) DDR_M0_DQS#6 DDR_M0_DQS6 <8>
117 147 32
VDD3 VDD13 DQS1#(C) DDR_M0_DQS#6 <8>
1
1
118 148 DDR_M0_MA0 144
VDD4 VDD14 <8> DDR_M0_MA0 DDR_M0_MA1 A0 DDR_M0_D45
@ @ @ 123 153 133 50
VDD5 VDD15 <8> DDR_M0_MA1 DDR_M0_MA2 A1 DQ16 DDR_M0_D47
RD1 RD6 RD2 124 154 132 49
VDD6 VDD16 <8> DDR_M0_MA2 DDR_M0_MA3 A2 DQ17 DDR_M0_D41
0_0402_5% 0_0402_5% 0_0402_5% 129 159 131 62
VDD7 VDD17 <8> DDR_M0_MA3 DDR_M0_MA4 A3 DQ18 DDR_M0_D40
130 160 128 63
VDD8 VDD18 <8> DDR_M0_MA4 A4 DQ19
2
2
135 163 DDR_M0_MA5 126 46 DDR_M0_D44
+3VS VDD9 VDD19 <8> DDR_M0_MA5 DDR_M0_MA6 A5 DQ20 DDR_M0_D46
136 127 45
VDD10 <8> DDR_M0_MA6 DDR_M0_MA7 A6 DQ21 DDR_M0_D42
122 58
<8> DDR_M0_MA7 DDR_M0_MA8 A7 DQ22 DDR_M0_D43
255 258 125 59
VDDSPD VTT +0.6VS <8> DDR_M0_MA8 DDR_M0_MA9 121 A8 DQ23 55 DDR_M0_DQS5
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM 164 257
<8> DDR_M0_MA9 DDR_M0_MA10 146 A9 DQS2(T) 53 DDR_M0_DQS#5 DDR_M0_DQS5 <8>
0.1U_0201_10V6K
+0.6V_DDRA_VREFCA VREFCA VPP1 259
+2.5V <8> DDR_M0_MA10 DDR_M0_MA11 120 A10_AP DQS2#(C) DDR_M0_DQS#5 <8>
2.2U_0402_6.3V6M
2 1 VPP2 <8> DDR_M0_MA11 A11
DDR_M0_MA12 119 70 DDR_M0_D36
<8> DDR_M0_MA12 DDR_M0_MA13 A12 DQ24 DDR_M0_D38
1 99 158 71
CD1
CD2
VSS VSS <8> DDR_M0_MA13 DDR_M0_MA14_WE# A13 DQ25 DDR_M0_D33
2 102 151 83
SPD ADDRESS FOR CHANNEL A : 1 2 5 VSS
VSS
VSS
VSS
103
<8>
<8>
DDR_M0_MA14_W E#
DDR_M0_MA15_CAS#
DDR_M0_MA15_CAS#
DDR_M0_MA16_RAS#
156 A14_WE#
A15_CAS#
DQ26
DQ27
84 DDR_M0_D35
DDR_M0_D39
6 106 152 66
WRITE ADDRESS: 0XA0 9
10
VSS
VSS
VSS
VSS
107
167
<8> DDR_M0_MA16_RAS#
DDR_M0_ACT# 114
A16_RAS# DQ28
DQ29
67
79
DDR_M0_D37
DDR_M0_D34
READ ADDRESS: 0XA1 PLACE NEAR TO PIN 14
15
VSS
VSS
VSS
VSS
168
171
+1.2V <8> DDR_M0_ACT#
DDR_M0_PAR 143
ACT# DQ30
DQ31
80
76
DDR_M0_D32
DDR_M0_DQS4
SA0 = 0; SA1 = 0; SA2 = 0. 18
19
VSS
VSS
VSS
VSS
172
175 RD7 2
<8>
<8>
1
DDR_M0_PAR
DDR_M0_ALERT#
DDR_M0_ALERT#
DDR_M0_EVENT#
116
134
PARITY
ALERT#
DQS3(T)
DQS3#(C)
74 DDR_M0_DQS#4 DDR_M0_DQS4
DDR_M0_DQS#4
<8>
<8>
DDR4 POR OPERATING SPEED: 1867 MT/S 22
23
VSS
VSS
VSS
VSS
176
180
240_0402_1%
<8,24> DDR_DRAMRST#_R
DDR_DRAMRST#_R 108 EVENT#
RESET# DQ32
174
173
DDR_M0_D11
DDR_M0_D10
STRETCH GOAL IS 2133 MT/S 26
27
VSS
VSS
VSS
VSS
181
184 SOC_SMBDATA 254
DQ33
DQ34
187
186
DDR_M0_D14
DDR_M0_D8
VSS VSS <9,24> SOC_SMBDATA SOC_SMBCLK SDA DQ35 DDR_M0_D12
30 185 253 170
VSS VSS <9,24> SOC_SMBCLK SCL DQ36 DDR_M0_D9
31 188 169
35 VSS VSS 189 SA2_CHA_DIM1 166 DQ37 183 DDR_M0_D15
36 VSS VSS 192
To SOC SA1_CHA_DIM1 260 SA2 DQ38 182 DDR_M0_D13
39 VSS VSS 193 SA0_CHA_DIM1 256 SA1 DQ39 179 DDR_M0_DQS1
VSS VSS SA0 DQS4(T) DDR_M0_DQS#1 DDR_M0_DQS1 <8>
40 196 177
VSS VSS DQS4#(C) DDR_M0_DQS#1 <8>
43 197
C VSS VSS DDR_M0_D5 C
44 201 92 195
47 VSS VSS 202 91 CB0_NC DQ40 194 DDR_M0_D7
48 VSS VSS 205 101 CB1_NC DQ41 207 DDR_M0_D0
51 VSS VSS 206 105 CB2_NC DQ42 208 DDR_M0_D2
+1.2V 52 VSS VSS 209 88 CB3_NC DQ43 191 DDR_M0_D6
56 VSS VSS 210 +1.2V 87 CB4_NC DQ44 190 DDR_M0_D4
57 VSS VSS 213 100 CB5_NC DQ45 203 DDR_M0_D3
VSS VSS CB6_NC DQ46 DDR_M0_D1
DIMM Side CPU Side
60 214 104 204
61 VSS VSS 217 RD8 2 1 240_0402_1% 97 CB7_NC DQ47 200 DDR_M0_DQS0
VSS VSS DQS8(T) DQS5(T) DDR_M0_DQS#0 DDR_M0_DQS0 <8>
64 218 RD9 2 1 240_0402_1% 95 198
VSS VSS DQS8#(C) DQS5#(C) DDR_M0_DQS#0 <8>
2
65 222
RD10 +0.6V_DDRA_VREFCA +0.6V_A_VREFCA 68 VSS VSS 223 216 DDR_M0_D31
69 VSS VSS 226 12 DQ48 215 DDR_M0_D24
1K_0402_1% +1.2V
72 VSS VSS 227 33 DM0#/DBI0# DQ49 228 DDR_M0_D26
73 VSS VSS 230 54 DM1#/DBI1# DQ50 229 DDR_M0_D30
VSS VSS DM2#/DBI2# DQ51
1
CD3 89 244
RD12 0.022U_0402_25V6K 90 VSS VSS 247
VSS VSS 2
2 93 248 CD4
1K_0402_1%
94 VSS VSS 251 0.1U_0201_10V6K 237 DDR_M0_D17
VSS VSS DQ56
2
245 DDR_M0_D22
LOTES_ADDR0206-P001A DQ62 246 DDR_M0_D16
CONN@ PLACE NEAR TO SODIMM DQ63
DQS7(T)
242 DDR_M0_DQS2
DDR_M0_DQS#2 DDR_M0_DQS2 <8>
240
DQS7#(C) DDR_M0_DQS#2 <8>
LOTES_ADDR0206-P001A
CONN@
+1.2V
B
Decopling Cap._Channel A Part Number:SP07001JH00
B
@EMI@
@EMI@
@EMI@
@EMI@
Layout Note: Layout Note: Layout Note:
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
2 2 2 2
Place near JDIMM2.257,259 Place near JDIMM2.258 PLACE THE CAP near JDIMM2. 164
1 1 1 1
CD5
CD6
CD7
CD8
teknisi-indonesia.com
+2.5V +0.6VS +0.6V_DDRA_VREFCA
2.2uF *1
10uF *1 10uF *1+1uF *2 0.1uF *1
1uF *1
Follow Intel RVP
2 2
10U_0402_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 @
CD10 CD13
CD9
CD11
CD12
CD14
CD15
0.1U_0201_10V6K 2.2U_0402_6.3V6M
1 1
2 2 2 2 2
EMC CAPS-PLACE
< 4mm from SO-DIMM VDDQ
with each pair < 12mm Apart
12pF* 5 (EMI@)
2.2pF* 5 (EMI@)
1 1 1 1 1 1 1 1 1 1
follow RVP 1p0
CD16
CD17
CD18
CD19
CD20
CD21
CD22
CD23
CD24
CD25
12P_0201_50V8J
12P_0201_50V8J
12P_0201_50V8J
12P_0201_50V8J
12P_0201_50V8J
2.2P_0201_50V8C
2.2P_0201_50V8C
2.2P_0201_50V8C
2.2P_0201_50V8C
2.2P_0201_50V8C
A
10uF*8 A
+1.2V 1uF*8 +1.2V 2 2 2 2 2 2 2 2 2 2
@330uF*1
EMI@
EMI@
EMI@
EMI@
EMI@
EMI@
EMI@
EMI@
EMI@
EMI@
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD26
CD27
CD28
CD29
CD30
CD31
CD32
CD33
CD34
CD35
CD36
CD37
CD38
CD39
CD40
CD41
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4_CHM0: DIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: Wednesday, March 10, 2021 Sheet 23 of 121
5 4 3 2 1
5 4 3 2 1
1
17 DDR_M1_D44
RD14 @ RD15 DDR_M1_CS#0 149 DQ7 13 DDR_M1_DQS5
<8> DDR_M1_D[48..63] <8> DDR_M1_CS#0 DDR_M1_CS#1 S0# DQS0(T) DDR_M1_DQS#5 DDR_M1_DQS5 <8>
0_0402_5% RD18 @ 0_0402_5% 157 11
@ <8> DDR_M1_CS#1 S1# DQS0#(C) DDR_M1_DQS#5 <8>
0_0402_5% JDIMM2B 162
D STD 165 S2#/C0 28 DDR_M1_D34 D
S3#/C1 DQ8
2
2
2
SA0_CHB_DIM2 SA1_CHB_DIM2 SA2_CHB_DIM2 111 141 29 DDR_M1_D36
+1.2V 112 VDD1 VDD11 142
+1.2V DDR_M1_ODT0 155 DQ9 41 DDR_M1_D32
VDD2 VDD12 <8> DDR_M1_ODT0 ODT0 DQ10
1
117 147 DDR_M1_ODT1 161 42 DDR_M1_D37
VDD3 VDD13 <8> DDR_M1_ODT1 ODT1 DQ11
1
1
RD19 118 148 24 DDR_M1_D35
@ @ @ 123 VDD4 VDD14 153 DDR_M1_BG0 115 DQ12 25 DDR_M1_D33
0_0402_5% <8> DDR_M1_BG0
RD16 RD17 124 VDD5 VDD15 154 DDR_M1_BG1 113 BG0 DQ13 38 DDR_M1_D38
VDD6 VDD16 <8> DDR_M1_BG1 DDR_M1_BA0 BG1 DQ14 DDR_M1_D39
0_0402_5% 0_0402_5% 129 159 150 37
VDD7 VDD17 <8> DDR_M1_BA0 BA0 DQ15
2
2
135 163 32 DDR_M1_DQS#4
+3VS VDD9 VDD19 DDR_M1_MA0 DQS1#(C) DDR_M1_DQS#4 <8>
136 144
VDD10 <8> DDR_M1_MA0 DDR_M1_MA1 A0 DDR_M1_D58
133 50
<8> DDR_M1_MA1 DDR_M1_MA2 A1 DQ16 DDR_M1_D62
255 258 132 49
VDDSPD VTT +0.6VS <8> DDR_M1_MA2 DDR_M1_MA3 131 A2 DQ17 62 DDR_M1_D60
<8> DDR_M1_MA3 DDR_M1_MA4 A3 DQ18 DDR_M1_D57
164 257 128 63
0.1U_0201_10V6K
+0.6V_DDRB_VREFCA VREFCA VPP1 259
+2.5V <8> DDR_M1_MA4 DDR_M1_MA5 126 A4 DQ19 46 DDR_M1_D59
PLACE ALL THE BELOW RESISTORS CLOSE TO SODIMM
2.2U_0402_6.3V6M
2 1 VPP2 <8> DDR_M1_MA5 A5 DQ20
DDR_M1_MA6 127 45 DDR_M1_D61
<8> DDR_M1_MA6 DDR_M1_MA7 A6 DQ21 DDR_M1_D63
1 99 122 58
CD43
CD42
VSS VSS <8> DDR_M1_MA7 DDR_M1_MA8 A7 DQ22 DDR_M1_D56
2 102 125 59
1 2 VSS VSS <8> DDR_M1_MA8 DDR_M1_MA9 A8 DQ23 DDR_M1_DQS7
5 103 121 55
SPD ADDRESS FOR CHANNEL B : 6 VSS
VSS
VSS
VSS
106
<8>
<8>
DDR_M1_MA9
DDR_M1_MA10
DDR_M1_MA10
DDR_M1_MA11
146 A9
A10_AP
DQS2(T)
DQS2#(C)
53 DDR_M1_DQS#7 DDR_M1_DQS7
DDR_M1_DQS#7
<8>
<8>
9 107 120
WRITE ADDRESS: 0XA4 10 VSS VSS 167
<8> DDR_M1_MA11 DDR_M1_MA12 119 A11 70 DDR_M1_D54
PLACE NEAR TO PIN 14 VSS VSS 168
<8> DDR_M1_MA12 DDR_M1_MA13 158 A12 DQ24 71 DDR_M1_D49
READ ADDRESS: 0XA3 15
18
VSS
VSS
VSS
VSS
171
172
<8>
<8>
DDR_M1_MA13
DDR_M1_MA14_WE#
DDR_M1_MA14_WE#
DDR_M1_MA15_CAS#
151
156
A13
A14_WE#
DQ25
DQ26
83
84
DDR_M1_D52
DDR_M1_D50
SA0 = 0; SA1 = 1; SA2 = 0. 19
22
VSS
VSS
VSS
VSS
175
176
<8>
<8>
DDR_M1_MA15_CAS#
DDR_M1_MA16_RAS#
DDR_M1_MA16_RAS# 152 A15_CAS#
A16_RAS#
DQ27
DQ28
66
67
DDR_M1_D55
DDR_M1_D51
DDR4 POR OPERATING SPEED: 1867 MT/S 23
26
VSS
VSS
VSS
VSS
180
181 +1.2V <8> DDR_M1_ACT#
DDR_M1_ACT# 114
ACT#
DQ29
DQ30
79
80
DDR_M1_D53
DDR_M1_D48
STRETCH GOAL IS 2133 MT/S 27
30
VSS
VSS
VSS
VSS
184
185
<8> DDR_M1_PAR
DDR_M1_PAR
DDR_M1_ALERT#
143
116 PARITY
DQ31
DQS3(T)
76
74
DDR_M1_DQS6
DDR_M1_DQS#6 DDR_M1_DQS6 <8>
VSS VSS <8> DDR_M1_ALERT# DDR_M1_EVENT# ALERT# DQS3#(C) DDR_M1_DQS#6 <8>
31 188 RD20 2 1 134
35 VSS VSS 189 240_0402_1% DDR_DRAMRST#_R 108 EVENT# 174 DDR_M1_D8
VSS VSS <8,23> DDR_DRAMRST#_R RESET# DQ32 DDR_M1_D14
36 192 173
39 VSS VSS 193 DQ33 187 DDR_M1_D10
40 VSS VSS 196 SOC_SMBDATA 254 DQ34 186 DDR_M1_D12
VSS VSS <9,23> SOC_SMBDATA SOC_SMBCLK SDA DQ35 DDR_M1_D15
43 197 253 170
VSS VSS <9,23> SOC_SMBCLK SCL DQ36 DDR_M1_D13
44 201 169
47 VSS VSS 202 SA2_CHB_DIM2 166 DQ37 183 DDR_M1_D9
48 VSS VSS 205
To SOC SA1_CHB_DIM2 260 SA2 DQ38 182 DDR_M1_D11
+1.2V 51 VSS VSS 206 SA0_CHB_DIM2 256 SA1 DQ39 179 DDR_M1_DQS1
C VSS VSS SA0 DQS4(T) DDR_M1_DQS#1 DDR_M1_DQS1 <8> C
52 209 177
VSS VSS DQS4#(C) DDR_M1_DQS#1 <8>
56 210
57 VSS VSS 213 92 195 DDR_M1_D7
60 VSS VSS 214 91 CB0_NC DQ40 194 DDR_M1_D6
61 VSS VSS 217 101 CB1_NC DQ41 207 DDR_M1_D2
64 VSS VSS 218 105 CB2_NC DQ42 208 DDR_M1_D3
65 VSS VSS 222 88 CB3_NC DQ43 191 DDR_M1_D0
VSS VSS +1.2V CB4_NC DQ44 DDR_M1_D5
DIMM Side
68 223 87 190
VSS VSS CB5_NC DQ45 DDR_M1_D1
CPU Side
69 226 100 203
VSS VSS CB6_NC DQ46
2
@ESD@
1
2
237 DDR_M1_D21
FOX_AS0A826-H4SB-7H DQ56
RD26 Follow 573129_ICL_U_DDR4_SODIMM_HW_SCH_Rev1P0 236 DDR_M1_D17
CONN@ DQ57 249 DDR_M1_D16
24.9_0402_1%
DQ58 250 DDR_M1_D20
DQ59 232 DDR_M1_D19
DQ60
1
233 DDR_M1_D23
DQ61 245 DDR_M1_D18
PLACE NEAR TO SODIMM DQ62 246 DDR_M1_D22
DQ63 242 DDR_M1_DQS2
DQS7(T) DDR_M1_DQS#2 DDR_M1_DQS2 <8>
240
DQS7#(C) DDR_M1_DQS#2 <8>
FOX_AS0A826-H4SB-7H
Part Number:SP07001HY00
Part Value:S SOCKET LOTES ADDR0207-P001A 260P DDR4
Layout Note:
Layout Note: Layout Note: PLACE THE CAP WITHIN 200 MILS
Place near JDIMM1.257,259 Place near JDIMM1.258 FROM THE JDIMM1
Refer for DDR4 SO-DIMM Decoupling Caps
607872_TGL_UY_PDG_Rev0p5
+2.5V 10uF *1 +0.6VS 10uF *1+1uF *2 +0.6V_DDRB_VREFCA
2.2uF *1
1uF *1 0.1uF *1
2 2
1U_0201_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 @
10U_0402_6.3V6M
CD51 CD52
CD46
CD47
CD48
CD49
CD50
0.1U_0201_10V6K 2.2U_0402_6.3V6M
1 1
2 2 2 2 2
Layout Note:
Place near JDIMM1
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CD53
CD54
CD55
CD56
CD57
CD58
CD59
CD60
CD61
CD62
CD63
CD64
CD65
CD66
CD67
CD68
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR4_CHM1: DIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size
Size DocumentNumber
Document Number Rev
Rev
1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date:
Date: Wednesday, March 10, 2021 Sheet
Sheet 24 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for DDR2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.A
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve for DDR3
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.A
1 2 +1V8_AON
2
RG1
10K_0201_5% RG1632
5
10K_0201_5%
GND VCC
DGPU_HOLD_RST# 1
<12,34> DGPU_HOLD_RST# IN B
1
4 RG2 1 @ 2 0_0201_5% DGPU_PEX_RST#
2 OUT Y DGPU_PEX_RST# <28,34>
<11,34,51,52,58,68> PCI_RST# IN A
1
@
@ UG1 RG3
NL17SZ08DFT2G_SC70-5 100K_0201_5%
3
1 1
2
+1V8_MAIN
2
+1V8_AON UV1A
RG4
10K_0201_5% 1/17 PCI_EXPRESS
2
+0.95VS_S0 +0.95VS_S0
1
RG5
10K_0201_5% T12 @ PAD~D AP11 AL27
PEX_WAKE_N PEX_DVDD_1 AL28
PEX_DVDD_2
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
2
1 @ 2 DGPU_PEX_RST#_R AN11 AL29
PEX_DVDD
RG6
G
PEX_RST_N PEX_DVDD_3 1 1 1 1 1 1 1 1 1
1
0_0201_5% AM26
CG1409
CG1410
CG1411
CG1412
CG1413
CG1414
CG1415
CG1416
CG1417
1 3 CLKREQ_PCIE#4_GPU_R AU11 PEX_DVDD_4 AM28
<11> CLKREQ_PCIE#4_GPU PEX_CLKREQ_N PEX_DVDD_5
PEX_CVDD
AM29
S
AR12 PEX_DVDD_6 AM30 2 2 2 2 2 2 2 2 2
<11> CLK_PCIE_P4 PEX_REFCLK PEX_DVDD_7
PCIE CLK AT12 AN29
QG1 <11> CLK_PCIE_N4 PEX_REFCLK_N PEX_DVDD_8 AN30
MESS138W -G_SOT323-3 CV543 1 2 0.22U_0201_6.3V6M PCIE_CRX_C_DTX_P5 AN13 PEX_DVDD_9 AP30
<13> PCIE_CRX_DTX_P5 PEX_TX0 PEX_DVDD_10
CV544 1 2 0.22U_0201_6.3V6M PCIE_CRX_C_DTX_N5 AP13 AR30
<13> PCIE_CRX_DTX_N5 PEX_TX0_N PEX_DVDD_11 AT30
CV545 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_P5 AV13 PEX_DVDD_12 AU30
<13> PCIE_CTX_DRX_P5 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_N5 AW13 PEX_RX0 PEX_DVDD_13 AV30
CV546
<13> PCIE_CTX_DRX_N5 PEX_RX0_N PEX_DVDD_14 AW30
CV547 1 2 0.22U_0201_6.3V6M PCIE_CRX_C_DTX_P6 AR14 PEX_DVDD_15 AY30
<13> PCIE_CRX_DTX_P6 1 2 0.22U_0201_6.3V6M PCIE_CRX_C_DTX_N6 AT14 PEX_TX1 PEX_DVDD_16
CV548
<13> PCIE_CRX_DTX_N6 PEX_TX1_N
CV549 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_P6 AW14
<13> PCIE_CTX_DRX_P6 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_N6 AY14 PEX_RX1
CV550
<13> PCIE_CTX_DRX_N6 PEX_RX1_N
2
PCIE X4 Bus 2
CV551 1 2 0.22U_0201_6.3V6M PCIE_CRX_C_DTX_P7 AN15
<13> PCIE_CRX_DTX_P7 PEX_TX2
CV552 1 2 0.22U_0201_6.3V6M PCIE_CRX_C_DTX_N7 AP15
<13> PCIE_CRX_DTX_N7 PEX_TX2_N
CV553 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_P7 AV15
<13> PCIE_CTX_DRX_P7 PEX_RX2
CV554 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_N7 AW15
<13> PCIE_CTX_DRX_N7 PEX_RX2_N AL24
CV555 1 2 0.22U_0201_6.3V6M PCIE_CRX_C_DTX_P8 AR16 PEX_CVDD_1 AL25
<13> PCIE_CRX_DTX_P8 1 2 0.22U_0201_6.3V6M PCIE_CRX_C_DTX_N8 AT16 PEX_TX3 PEX_CVDD_2 AL26
CV556
<13> PCIE_CRX_DTX_N8 PEX_TX3_N PEX_CVDD_3 AM24
1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_P8 AW16 PEX_CVDD_4
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
AL19
PEX_HVDD
PEX_HVDD_3 1 1 1 1 1 1 1 1
AV17 AL20
CG1418
CG1419
CG1420
CG1421
CG1422
CG1423
CG1424
CG1425
AW17 PEX_RX4 PEX_HVDD_4 AL21
PEX_RX4_N PEX_HVDD_5
PEX_PLL_HVDD
AL22
AR18 PEX_HVDD_6 AL23 2 2 2 2 2 2 2 2
AT18 PEX_TX5 PEX_HVDD_7 AM16
PEX_TX5_N PEX_HVDD_8 AM18
AW18 PEX_HVDD_9 AM20
AY18 PEX_RX5 PEX_HVDD_10
PEX_RX5_N
AN19
AP19 PEX_TX6 AM22
PEX_TX6_N PEX_PLL_HVDD
AV19
AW19 PEX_RX6
PEX_RX6_N
AR20
AT20 PEX_TX7
PEX_TX7_N
AW20
AY20 PEX_RX7
PEX_RX7_N
AN21
AP21 PEX_TX8
PEX_TX8_N
AV21
AW21 PEX_RX8
PEX_RX8_N
AR22
AT22 PEX_TX9
PEX_TX9_N
AW22
AY22 PEX_RX9
PEX_RX9_N
AN23
PEX_TX10
GPU
3 AP23 3
PEX_TX10_N
AV23
AW23 PEX_RX10
UV1 N18PG61A@ UV1 GN20P0@ UV1 GN20P1@ PEX_RX10_N
AR24
AT24 PEX_TX11
PEX_TX11_N
AW24
AY24 PEX_RX11
PEX_RX11_N
N18P-G61-A_R3 GN20-P0_QS1 GN20-P1_QS2
AN25
SA0000DVM60 SA0000E1W10 SA0000DXQ10 AP25 PEX_TX12
PEX_TX12_N
AV25
AW25 PEX_RX12
PEX_RX12_N
AR26
AT26 PEX_TX13
PEX_TX13_N
AW26
AY26 PEX_RX13
PEX_RX13_N
AN27
AP27 PEX_TX14
PEX_TX14_N
VRAM AV27
AW27 PEX_RX14
PEX_RX14_N AU29 PAD~D T25 @
AR28 PEX_CVDD_SENSE
UV13 M4G@ UV14 M4G@ UV11 M4G@ UV12 M4G@ AT28 PEX_TX15
PEX_TX15_N
AW28 AW29 PEX_TERMP 2 1
AY28 PEX_RX15 PEX_TERMP
PEX_RX15_N RG7
2.49K_0402_1%
MT61K256M32JE-14:A_R3 MT61K256M32JE-14:A_R3 MT61K256M32JE-14:A_R3 MT61K256M32JE-14:A_R3
SA0000BND70 SA0000BND70 SA0000BND70 SA0000BND70
QN20-P3_FCBGA1358~D
@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Title
N18E(1/9) PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Rev 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Size
LA-L161P
Document Number
+1V8_MAIN
RG8 1 2 0_0201_5%
5
1 1
QG2A
G
VGA_SMB_CK2 4 3 PJT138KA 2N SOT363-6
EC_SMB_CK2 <58,66>
D
2
QG2B For EC
PJT138KA 2N SOT363-6
G
UV1O VGA_SMB_DA2 1 6
EC_SMB_DA2 <58,66>
D
10/17 MISC1
+1V8_MAIN
U1 VGA_SMB_CK2
I2CS_SCL V1 VGA_SMB_DA2
I2CS_SDA For EC
OVERT# P1 RG9 1 2 0_0201_5%
<34> OVERT# OVERT I2CC_SCL_R
U2
AP8 I2CC_SCL V2 I2CC_SDA_R
TS_VREF I2CC_SDA For NVVDD/OVRM
2
@ M2 U3 EDP_I2CB_SCL_R
THERMDN I2CB_SCL
5
CG1101 V3 EDP_I2CB_SDA_R
M1 I2CB_SDA QG3A
0.01U_0402_16V7K
G
THERMDP
1
D
GPIO0 P7 NVVDD_VID <103>
2
GPU_GC6_FB_EN
GPIO1 R4 GPU_GC6_FB_EN <34>
QG3B For NVVDD/OVRM
G
@ T13 PAD~D JTAG_TCLK AY11 GPIO2 U6 RG296 1 N18P@ 2 0_0402_5% I2CC_SDA_R 1 6 PJT138KA 2N SOT363-6
JTAG_TMS AV11 JTAG_TCK GPIO3 U7 N20_NVVDD_EN 1 GN20P@ 2 0_0402_5% N18P_1V8_MAIN_EN <34> VGA_I2CC_SDA_R_Q <37,103>
@ T14 PAD~D RG297
D
JTAG_TDI JTAG_TMS GPIO4 V4 NVVDD_GPU_EN <34>
@ T15 PAD~D AW11
@ T16 PAD~D JTAG_TDO AW12 JTAG_TDI GPIO5 R7 NVVDD_PSI#
JTAG_TRST# AV12 JTAG_TDO GPIO6 M6 NVVDD_PSI# <103>
NVJTAG_SEL AY12 JTAG_TRST_N GPIO7 L8 VRAM_VDD_CTL
NVJTAG_SEL GPIO8 M7 THERM_ALERT# VRAM_VDD_CTL <108>
DG2
Y3 GPIO9 L5 MEM_VREF RB751S40T1G_SOD523-2
<37> ADC_IN_P ADC_IN GPIO10 R8 MEM_VREF <35,36>
Y4
<37> ADC_IN_N ADC_IN_N GPIO11 M3 GPU_PROHOT_NV 2 1
GPIO12 P6 GPU_PROCHOT# <58>
1
2 2
GPIO18 R3
GPIO19 R5
5
GPIO20 R2 +3VS
G
GPIO21 M5 ADC_MUX_SEL 4 3
GPIO22 U5 ADC_MUX_SEL <37>
D
Pin Name Default Function GPIO23 L7 QG4A @
GPIO24 R6
2
FBVDD_PSI# PJT138KA 2N SOT363-6
JTAG_TRST L JTAG support GPIO25 M4 ROM_WP# FBVDD_PSI# <108>
RG1606
GPIO26 R1 ROM_WP# <29,31> DGPU_PEX_RST# RG18 1 2 10K_0201_5%
@ @ 10K_0201_5%
GPIO27 M8 <27,34> DGPU_PEX_RST#
NVJTAG_SEL L Test Mode --> Disable RFU_GPIO28 P8
RFU_GPIO29 P9
1
2
RFU_GPIO30 R9
G
H Test Mode --> Enable RFU_GPIO31 U9 THERM_ALERT# 1 6
RFU_GPIO32 V9 THERM_ALERT#_EC_R <58>
D
RFU_GPIO33 U10 QG4B @
RFU_GPIO34 V10 PJT138KA 2N SOT363-6
RFU_GPIO35
QN20-P3_FCBGA1358~D
@
+1V8_AON
4 4
DP
UV1K
5/17 IFPAB
DVI DP
SL/DL
TXC/TXC
AV1
IFPA_L3_N AV2
TXC/TXC IFPA_L3
AP9
IFPAB_RSET
TXD0/0
AW3
1 IFPA_L2_N AY3 1
TXD0/0 IFPA_L2
AN9
IFPAB_PLLVDD AV5
TXD1/1 IFPA_L1_N
2
TXD1/1 AW5
RG1602 IFPA_L1
10K_0201_5%
TXD2/2
AY5
IFPA_L0_N AY6
TXD2/2 IFPA_L0
TXC
AW9 GDDR6 VRAM Strap2 Strap1 Strap0 RAMCFG
IFPB_L3_N
1
TXC
AV9
IFPB_L3
Samsung , K4Z80325BC-HC14 L L L 0X0 RG45 RG46 RG47 RG48 RG49 RG50 RG51 RG52 RG53
100K_0201_1% 100K_0201_1% 100K_0201_1% 100K_0201_1% 100K_0201_1% 100K_0201_1% 100K_0201_1% 10K_0201_1% 100K_0201_1%
AV8 Y8 ROM_CS#
TXD0/3 IFPB_L2_N Micron , MT61K256M32JE-14:A L L H 0X1 @ @ @ @ @ @
ROM_CS_N
@ @ GN20P@
TXD0/3
AW8
IFPB_L2
2
Y7 ROM_SI
Hynix , H56C8H24AIR-S2C L H L 0X2 ROM_SI ROM_SO
Y9
AW6 STRAP0 V5 ROM_SO Y10 ROM_SCLK
TXD1/4 IFPB_L1_N STRAP0 ROM_SCLK
TXD1/4 AV6 STRAP1 V8
IFPB_L1 STRAP2 Y5 STRAP1
STRAP3 V7 STRAP2
STRAP3
1
TXD2/5
AY8 STRAP4 U8
IFPB_L0_N AY9 STRAP5 V6 STRAP4
TXD2/5 IFPB_L0 Samsung RG58 X76_S@
100K_0201_1%
RG59 X76_S@
100K_0201_1%
RG60 X76_S@
100K_0201_1% STRAP5
RG55
100K_0201_1%
RG56
10K_0201_1%
RG57
100K_0201_1%
N18P@
1
AK7
IFPB_AUX_SDA_N
2
AL15 AJ7 Micron RG58 X76_M@ RG59 X76_M@ RG47 X76_M@ RG58 RG59 RG60 RG61 RG62 RG63
AL16 IFP_IOVDD_5 IFPB_AUX_SCL 100K_0201_1% 100K_0201_1% 100K_0201_1% 100K_0201_1% 100K_0201_1% 100K_0201_1% 100K_0201_1% 100K_0201_1% 100K_0201_1%
AM11 IFP_IOVDD_6 @ @ @
AM12 IFP_IOVDD_7
IFP_IOVDD_8
2
Hynix RG58 X76_H@
100K_0201_1%
RG46 X76_H@
100K_0201_1%
RG60 X76_H@
100K_0201_1%
QN20-P3_FCBGA1358~D
@
QN20-P3_FCBGA1358~D
@
2 2
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
GPCADC_AVDD
22U_0603_6.3V6M
4.7U_0402_6.3V6M
SM01000NV00 1 1 1 1 1 1 AK9
SP_PLLVDD
CG1431
CG1432
CG1433
CG1434
CG1435
CG1436
AJ10
VID_PLLVDD
2
N18P@
2 2 2 2 2 2 RG64 RG201 1
+1V8_AON 10K_0201_5% 10K_0201_5%
CG63
RG68 0.1U_0201_10V6K
1
L4 L3 XTALOUTBUFF_R 1 @ 2 2
EXT_REFCLK_FL XTAL_OUTBUFF UG2 GN20P@
ROM_CS# RG65 1 2 33_0201_5% ROM_CS#_R 1 8
100K_0201_5% CS# VCC
1
L2 L1 ROM_SO RG66 1 @ 2 0_0201_5% ROM_SO_R 2 7
XTAL_IN XTAL_OUT RG2921 2 0_0201_5% ROM_W P#_R 3 DO(IO1) HOLD#(IO3) 6 ROM_SCLK_R RG54 1 2 33_0201_5% ROM_SCLK
@ <28,31> ROM_W P# GN20P@ 4 WP#(IO2) CLK 5 ROM_SI_R RG67 1 2 33_0201_5% ROM_SI
QN20-P3_FCBGA1358~D
RG71 GND DI(IO0)
@
1
2
@ 100K_0201_5% GN20P@ W 25Q16JWSSIQ
2
RG69 RG70 RG218 SA0000DHJ00
10K_0402_5% 10K_0402_5% RG72 10K_0201_5%
10M_0402_5%
1 2
2
1
2M
UG2 N18P@
YG1
@ 1
CG67 XTALIN 1 3 XTALOUT
18P_0402_50V8J 1 3
2 NC NC 2
2 CG68 CG69 MX25U8035FM2I_SO8
3 2 4 3
12P_0402_50V8J 12P_0402_50V8J
1 1 SA0000DW700
27MHZ_10PF_7R27000001
TXC SJ1000TQ00
Murata SJ10000UI00
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E(3/9) Strap, XTAL, IFP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: W ednesday, March 10, 2021 Sheet 29 of 121
A B C D E
A B C D E
1
www.teknisi-indonesia.com 1
AN7 UV1M
IFPCD_RSET
7/17 IFPD
HDMI DP
AK4
IFPC_AUX_SDA_N AJ4
IFPC_AUX_SCL HDMI DP
AJ5
AM6 IFPD_AUX_SDA_N AK5
TXC IFPC_L3_N IFPD_AUX_SCL
AN8 TXC
AM5
IFPCD_PLLVDD IFPC_L3
2
AL13
AL14 IFP_IOVDD_3 AM14
IFP_IOVDD_4 AN12 IFP_IOVDD_9
IFP_IOVDD_10
QN20-P3_FCBGA1358~D
@ QN20-P3_FCBGA1358~D
@
UV1N
TYPEC SW
3 3
8/17 IFPE
AM7
IFPE_RSET
HDMI DP
AJ8
AM8 IFPE_AUX_SDA_N AK8
IFPE_PLLVDD IFPE_AUX_SCL
2
RG1604 AJ1
TXC IFPE_L3_N
10K_0201_5% TXC
AJ2
IFPE_L3
TXD0 AK1
IFPE_L2_N
1
TXD0 AK2
IFPE_L2
AM3
TXD1 IFPE_L1_N
TXD1
AM2
IFPE_L1
TXD2 AM1
IFPE_L0_N AN1
TXD2 IFPE_L0
AL11
AL12 IFP_IOVDD_1
IFP_IOVDD_2
QN20-P3_FCBGA1358~D
@
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E(4/9) eDP, HDMI, DP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.A
10K_0402_1%
1U_0402_6.3V
XVDD_10 XVDD_40 VDD_16 VDD_86 VDD_154 VDD_182 FBVDDQ_17 FBVDDQ_52
1
AB2 AF1 AA28 AJ18 T28 W26 AG35 K25 4 3
1U_0402_6.3V
XVDD_11 XVDD_41 VDD_17 VDD_87 VDD_155 VDD_183 FBVDDQ_18 FBVDDQ_53 VSS EN 1
AB4 AF2 AA29 AJ19 T29 W27 AH31 K26 QN20-P3_FCBGA1358~D
CG1100
RG219
AB6 XVDD_12 XVDD_42 AF3 AB12 VDD_18 VDD_88 AJ20 U12 VDD_156 VDD_184 W28 AH37 FBVDDQ_19 FBVDDQ_54 K30 APL3531S6I-TRG SC-70
XVDD_13 XVDD_43 VDD_19 VDD_89 VDD_157 VDD_185 FBVDDQ_20 FBVDDQ_55 @ 1
AB8 AF4 AB29 AJ21 U29 W29 AH39 L31 N18P@
CG1099
AB10 XVDD_14 XVDD_44 AF5 AC12 VDD_20 VDD_90 AJ22 V12 VDD_158 VDD_186 Y12 AJ31 FBVDDQ_21 FBVDDQ_56 M31 2 N18P@
XVDD_15 XVDD_45 VDD_21 VDD_91 VDD_159 VDD_187 FBVDDQ_22 FBVDDQ_57
2
AC1 AF6 AC13 AJ23 V13 Y13 B13 N31 N18P@
AC2 XVDD_16 XVDD_46 AF7 AC14 VDD_22 VDD_92 AJ24 V14 VDD_160 VDD_188 Y14 B16 FBVDDQ_23 FBVDDQ_58 U31 2
AC3 XVDD_17 XVDD_47 AF8 AC15 VDD_23 VDD_93 AJ25 V15 VDD_161 VDD_189 Y15 B19 FBVDDQ_24 FBVDDQ_59 V31 N18P@
AC4 XVDD_18 XVDD_48 AF9 AC16 VDD_24 VDD_94 AJ26 V16 VDD_162 VDD_190 Y16 B22 FBVDDQ_25 FBVDDQ_60 V33
AC5 XVDD_19 XVDD_49 AF10 AC17 VDD_25 VDD_95 AJ27 V17 VDD_163 VDD_191 Y21 D13 FBVDDQ_26 FBVDDQ_61 V35
AC6 XVDD_20 XVDD_50 AG1 AC18 VDD_26 VDD_96 AJ28 V18 VDD_164 VDD_192 Y22 D23 FBVDDQ_27 FBVDDQ_62 V37
AC7 XVDD_21 XVDD_51 AG2 AC19 VDD_27 VDD_97 AJ29 V19 VDD_165 VDD_193 Y23 E16 FBVDDQ_28 FBVDDQ_63 W33
AC8 XVDD_22 XVDD_52 AG3 AC20 VDD_28 VDD_98 M12 V20 VDD_166 VDD_194 Y24 E19 FBVDDQ_29 FBVDDQ_64 W35 RG281 1 N18P@ 2 0_0402_5%
XVDD_23 XVDD_53 VDD_29 VDD_99 VDD_167 VDD_195 FBVDDQ_30 FBVDDQ_65 <28,29> ROM_WP#
AC9 AG4 AC21 M13 Y29 E20 W36
AC10 XVDD_24 XVDD_54 AG5 AC22 VDD_30 VDD_100 M14 VDD_196 E22 FBVDDQ_31 FBVDDQ_66 W39
10K_0402_1%
XVDD_25 XVDD_55 VDD_31 VDD_101 FBVDDQ_32 FBVDDQ_67
1
AD1 AG6 AC23 M15 F14 Y31
AD2 XVDD_26 XVDD_56 AG7 AC24 VDD_32 VDD_102 M16 F16 FBVDDQ_33 FBVDDQ_68 Y34
RG299
AD3 XVDD_27 XVDD_57 AG8 AC25 VDD_33 VDD_103 M17 F18 FBVDDQ_34 FBVDDQ_69
AD4 XVDD_28 XVDD_58 AG9 AC26 VDD_34 VDD_104 M18 FBVDDQ_35
AD5 XVDD_29 XVDD_59 AG10 AC27 VDD_35 VDD_105 M19 N18P@
XVDD_30 XVDD_60 VDD_36 VDD_106
2
AC28 M20
AC29 VDD_37 VDD_107 M21
AD12 VDD_38 VDD_108 M22
AD29 VDD_39 VDD_109 M23
AE12 VDD_40 VDD_110 M24 RG1595 , RG1596 Near Ball K11 +1V8_AON
AE13 VDD_41 VDD_111 M25
AE14 VDD_42 VDD_112 M26 RG1595 1 @ 2 0_0201_5%
AE15 VDD_43 VDD_113 M27 FB_GND_SENSE <108>
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
AE16 VDD_44 VDD_114 M28 RG1596 1 @ 2 0_0201_5%
VDD_45 VDD_115 FB_VDDQ_SENSE <108> 1 1 1 1 1 1
AE17 M29
CG1449
CG1450
CG1451
CG1452
CG1453
CG1454
C AE18 VDD_46 VDD_116 N12 C
AE19 VDD_47 VDD_117 N29
AE20 VDD_48 VDD_118 P12 2 2 2 2 2 2
AE21 VDD_49 VDD_119 P13 K11 +1.35VS_VRAM
AE22 VDD_50 VDD_120 P14 FBVDDQ_SENSE
AE23 VDD_51 VDD_121 P15
AE24 VDD_52 VDD_122 P16 M9
AE25
AE26
AE27
VDD_53
VDD_54
VDD_55
VDD_123
VDD_124
VDD_125
P17
P18
P19
RFU_VMS_SENSE M10
RFU_GMS_SENSE
QN20-P3_FCBGA1358~D
MSVDD_VDD_SENSE
MSVDD_VSS_SENSE
<103>
<103> FB_CAL_PD_VDDQ
H32
J32
FBCAL_VDDQ RG90 1
FBCAL_GND RG91 1
2 40.2_0402_1%
2 40.2_0402_1% +1V8_AON
Near GPU
AE28 VDD_56 VDD_126 P20 FB_CAL_PU_GND
@
AE29 VDD_57 VDD_127 P21 J33 FBCAL_TERM RG92 1 2 40.2_0402_1%
AF12 VDD_58 VDD_128 P22 FB_CAL_TERM_GND
AF29 VDD_59 VDD_129 P23
1U_0201_6.3V6M
1U_0201_6.3V6M
AG12 VDD_60 VDD_130 P24
VDD_61 VDD_131 1 1
AG13 P25 QN20-P3_FCBGA1358~D
CG1455
CG1456
AG14 VDD_62 VDD_132 P26 @
AG15 VDD_63 VDD_133 P27
AG16 VDD_64 VDD_134 P28 2 2
AG17 VDD_65 VDD_135 P29
AG18
AG19
VDD_66
VDD_67
VDD_136
VDD_137
R12
R29
GPU Decoupling - NV Spec Recommendation
AG20 VDD_68 VDD_138 T12
AG21 VDD_69 VDD_139
VDD_70
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1
1UF_0402 X 12 pcs
CG1463
CG1464
CG1465
CG1466
CG1467
CG1468
B 2 2 2 2 2 2 B
10UF_0603 X 4 pcs
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1
CG1469
CG1470
CG1471
CG1472
CG1473
CG1474
2 2 2 2 2 2
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1 1 1
CG1475
CG1476
CG1477
CG1478
2 2 2 2
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1
CG1479
CG1480
2 2 Place near GPU
22UF_0603 X 5 pcs
A A
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 1 1
10UF_0603 X 2 pcs
CG1481
CG1482
CG1483
CG1484
CG1485
2 2 2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E(6/9) Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.A
UV1D UV1E
15/17 GND_1/2 16/17 GND_2/2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E(7/9) GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.A
UV1B
2/17 FBA UV1C
3/17 FBB
N35 K28
<35> FB_A_D0 FBA_D0 FB_PLLVDD_2 +FBX_PLLAVDD
M38 G9
<35> FB_A_D1 P34 FBA_D1 <36> FB_B_D0 H12 FBB_D0
<35> FB_A_D2 FBA_D2 <36> FB_B_D1 FBB_D1
N37 1 J8
<35> FB_A_D3 R32 FBA_D3 <36> FB_B_D2 E11 FBB_D2
<35> FB_A_D4 FBA_D4 <36> FB_B_D3 FBB_D3
U33 CG1457 G11
<35> FB_A_D5 U35 FBA_D5 1U_0201_6.3V6M <36> FB_B_D4 F7 FBB_D4
<35> FB_A_D6 U37 FBA_D6 2 <36> FB_B_D5 H10 FBB_D5
<35> FB_A_D7 FBA_D7 <36> FB_B_D6 FBB_D6
1 E38 E6 1
<35> FB_A_D8 J36 FBA_D8 <36> FB_B_D7 J4 FBB_D7
<35>
<35>
<35>
FB_A_D9
FB_A_D10
FB_A_D11
L35
J34
F37
FBA_D9
FBA_D10
FBA_D11
Under GPU <36>
<36>
<36>
FB_B_D8
FB_B_D9
FB_B_D10
D4
F5
G2
FBB_D8
FBB_D9
FBB_D10
<35> FB_A_D12 FBA_D12 <36> FB_B_D11 FBB_D11
N33 H7
<35> FB_A_D13 K37 FBA_D13 <36> FB_B_D12 J2 FBB_D12
<35> FB_A_D14 FBA_D14 <36> FB_B_D13 FBB_D13
E36 Y36 J6
<35> FB_A_D15 J40 FBA_D15 FBA_CMD0 AA39 FB_A_CMD0 <35> <36> FB_B_D14 H1 FBB_D14 D14
<35> FB_A_D16 D40 FBA_D16 FBA_CMD1 AA32 FB_A_CMD1 <35> <36> FB_B_D15 A5 FBB_D15 FBB_CMD0 A17 FB_B_CMD0 <36>
<35> FB_A_D17 FBA_D17 FBA_CMD2 FB_A_CMD2 <35> <36> FB_B_D16 FBB_D16 FBB_CMD1 FB_B_CMD1 <36>
E37 AC34 E1 J15
<35> FB_A_D18 J38 FBA_D18 FBA_CMD3 AA33 FB_A_CMD3 <35> <36> FB_B_D17 D2 FBB_D17 FBB_CMD2 E17 FB_B_CMD2 <36>
<35> FB_A_D19 FBA_D19 FBA_CMD4 FB_A_CMD4 <35> <36> FB_B_D18 FBB_D18 FBB_CMD3 FB_B_CMD3 <36>
C39 Y37 F2 H15
<35> FB_A_D20 C40 FBA_D20 FBA_CMD5 Y35 FB_A_CMD5 <35> <36> FB_B_D19 C5 FBB_D19 FBB_CMD4 D17 FB_B_CMD4 <36>
<35> FB_A_D21 H40 FBA_D21 FBA_CMD6 AA35 FB_A_CMD6 <35> <36> FB_B_D20 F1 FBB_D20 FBB_CMD5 E14 FB_B_CMD5 <36>
<35> FB_A_D22 FBA_D22 FBA_CMD7 FB_A_CMD7 <35> <36> FB_B_D21 FBB_D21 FBB_CMD6 FB_B_CMD6 <36>
G39 Y39 B4 G15
<35> FB_A_D23 U38 FBA_D23 FBA_CMD8 V40 FB_A_CMD8 <35> <36> FB_B_D22 A3 FBB_D22 FBB_CMD7 A15 FB_B_CMD7 <36>
<35> FB_A_D24 FBA_D24 FBA_CMD9 FB_A_CMD9 <35> <36> FB_B_D23 FBB_D23 FBB_CMD8 FB_B_CMD8 <36>
K39 Y40 A6 B14
<35> FB_A_D25 R38 FBA_D25 FBA_CMD10 Y38 FB_A_CMD10 <35> <36> FB_B_D24 A12 FBB_D24 FBB_CMD9 B15 FB_B_CMD9 <36>
<35> FB_A_D26 T39 FBA_D26 FBA_CMD11 W37 FB_A_CMD11 <35> <36> FB_B_D25 C8 FBB_D25 FBB_CMD10 A14 FB_B_CMD10 <36>
<35> FB_A_D27 FBA_D27 FBA_CMD12 FB_A_CMD12 <35> <36> FB_B_D26 FBB_D26 FBB_CMD11 FB_B_CMD11 <36>
L38 AA40 A11 F17
<35> FB_A_D28 L40 FBA_D28 FBA_CMD13 AA38 FB_A_CMD13 <35> <36> FB_B_D27 B7 FBB_D27 FBB_CMD12 B17 FB_B_CMD12 <36>
<35> FB_A_D29 FBA_D29 FBA_CMD14 FB_A_CMD14 <35> <36> FB_B_D28 FBB_D28 FBB_CMD13 FB_B_CMD13 <36>
M40 V38 B12 D15
<35> FB_A_D30 U40 FBA_D30 FBA_CMD15 V39 FB_A_CMD15 <35> <36> FB_B_D29 D12 FBB_D29 FBB_CMD14 C15 FB_B_CMD14 <36>
<35> FB_A_D31 AN32 FBA_D31 FBA_CMD16 AA37 FB_A_CMD16 <35> <36> FB_B_D30 A8 FBB_D30 FBB_CMD15 C14 FB_B_CMD15 <36>
<35> FB_A_D32 FBA_D32 FBA_CMD17 FB_A_CMD17 <35> <36> FB_B_D31 FBB_D31 FBB_CMD16 FB_B_CMD16 <36>
AP35 AC38 D28 E15
<35> FB_A_D33 AR36 FBA_D33 FBA_CMD18 AC33 FB_A_CMD18 <35> <36> FB_B_D32 F28 FBB_D32 FBB_CMD17 C17 FB_B_CMD17 <36>
<35> FB_A_D34 FBA_D34 FBA_CMD19 FB_A_CMD19 <35> <36> FB_B_D33 FBB_D33 FBB_CMD18 FB_B_CMD18 <36>
AM34 AC36 D24 J17
<35> FB_A_D35 AJ33 FBA_D35 FBA_CMD20 Y33 FB_A_CMD20 <35> <36> FB_B_D34 J26 FBB_D34 FBB_CMD19 D18 FB_B_CMD19 <36>
<35> FB_A_D36 AL33 FBA_D36 FBA_CMD21 Y32 FB_A_CMD21 <35> <36> FB_B_D35 G27 FBB_D35 FBB_CMD20 J14 FB_B_CMD20 <36>
<35> FB_A_D37 FBA_D37 FBA_CMD22 FB_A_CMD22 <35> <36> FB_B_D36 FBB_D36 FBB_CMD21 FB_B_CMD21 <36>
AK34 AC32 H24 H14
<35> FB_A_D38 AK36 FBA_D38 FBA_CMD23 AC39 FB_A_CMD23 <35> <36> FB_B_D37 F24 FBB_D37 FBB_CMD22 H17 FB_B_CMD22 <36>
<35> FB_A_D39 FBA_D39 FBA_CMD24 FB_A_CMD24 <35> <36> FB_B_D38 FBB_D38 FBB_CMD23 FB_B_CMD23 <36>
AW34 V34 C29 A18
<35> FB_A_D40 AP33 FBA_D40 FBA_CMD25_NC V36 <36> FB_B_D39 D35 FBB_D39 FBB_CMD24 F13 FB_B_CMD24 <36>
<35> FB_A_D41 AT35 FBA_D41 FBA_CMD26_NC V32 <36> FB_B_D40 E32 FBB_D40 FBB_CMD25_NC G14
<35> FB_A_D42 FBA_D42 FBA_CMD27 <36> FB_B_D41 FBB_D41 FBB_CMD26_NC
AU37 AD35 F30 H13
<35> FB_A_D43 AY33 FBA_D43 FBA_CMD28 AG38 FB_A_CMD28 <35> <36> FB_B_D42 G32 FBB_D42 FBB_CMD27 E18
<35> FB_A_D44 FBA_D44 FBA_CMD29 FB_A_CMD29 <35> <36> FB_B_D43 FBB_D43 FBB_CMD28 FB_B_CMD28 <36>
AR32 AD32 H28 A23
<35> FB_A_D45 AU32 FBA_D45 FBA_CMD30 AG37 FB_A_CMD30 <35> <36> FB_B_D44 C36 FBB_D44 FBB_CMD29 J18 FB_B_CMD29 <36>
<35> FB_A_D46 AW32 FBA_D46 FBA_CMD31 AD33 FB_A_CMD31 <35> <36> FB_B_D45 D37 FBB_D45 FBB_CMD30 F20 FB_B_CMD30 <36>
<35> FB_A_D47 FBA_D47 FBA_CMD32 FB_A_CMD32 <35> <36> FB_B_D46 FBB_D46 FBB_CMD31 FB_B_CMD31 <36>
AY36 AD37 D31 H18
<35> FB_A_D48 AW35 FBA_D48 FBA_CMD33 AD36 FB_A_CMD33 <35> <36> FB_B_D47 A33 FBB_D47 FBB_CMD32 B20 FB_B_CMD32 <36>
<35> FB_A_D49 FBA_D49 FBA_CMD34 FB_A_CMD34 <35> <36> FB_B_D48 FBB_D48 FBB_CMD33 FB_B_CMD33 <36>
AW37 AC37 B39 G18
<35> FB_A_D50 AU39 FBA_D50 FBA_CMD35 AD40 FB_A_CMD35 <35> <36> FB_B_D49 B37 FBB_D49 FBB_CMD34 D22 FB_B_CMD34 <36>
<35> FB_A_D51 AY35 FBA_D51 FBA_CMD36 AG33 FB_A_CMD36 <35> <36> FB_B_D50 B34 FBB_D50 FBB_CMD35 A20 FB_B_CMD35 <36>
<35> FB_A_D52 FBA_D52 FBA_CMD37 FB_A_CMD37 <35> <36> FB_B_D51 FBB_D51 FBB_CMD36 FB_B_CMD36 <36>
AT38 AF33 A38 E21
<35> FB_A_D53 AT40 FBA_D53 FBA_CMD38 AC40 FB_A_CMD38 <35> <36> FB_B_D52 A32 FBB_D52 FBB_CMD37 F21 FB_B_CMD37 <36>
<35> FB_A_D54 FBA_D54 FBA_CMD39 FB_A_CMD39 <35> <36> FB_B_D53 FBB_D53 FBB_CMD38 FB_B_CMD38 <36>
AV40 AF34 B38 A21
<35> FB_A_D55 AR40 FBA_D55 FBA_CMD40 AG39 FB_A_CMD40 <35> <36> FB_B_D54 C32 FBB_D54 FBB_CMD39 D21 FB_B_CMD39 <36>
<35> FB_A_D56 AJ39 FBA_D56 FBA_CMD41 AF38 FB_A_CMD41 <35> <36> FB_B_D55 B25 FBB_D55 FBB_CMD40 B23 FB_B_CMD40 <36>
<35> FB_A_D57 FBA_D57 FBA_CMD42 FB_A_CMD42 <35> <36> FB_B_D56 FBB_D56 FBB_CMD41 FB_B_CMD41 <36>
2 AP39 AF37 C26 C21 2
<35> FB_A_D58 AK40 FBA_D58 FBA_CMD43 AG40 FB_A_CMD43 <35> <36> FB_B_D57 A30 FBB_D57 FBB_CMD42 C20 FB_B_CMD42 <36>
<35> FB_A_D59 FBA_D59 FBA_CMD44 FB_A_CMD44 <35> <36> FB_B_D58 FBB_D58 FBB_CMD43 FB_B_CMD43 <36>
AJ37 AD38 C24 C23
<35> FB_A_D60 AJ40 FBA_D60 FBA_CMD45 AF39 FB_A_CMD45 <35> <36> FB_B_D59 A24 FBB_D59 FBB_CMD44 C18 FB_B_CMD44 <36>
<35> FB_A_D61 AN38 FBA_D61 FBA_CMD46 AF36 FB_A_CMD46 <35> <36> FB_B_D60 C30 FBB_D60 FBB_CMD45 B18 FB_B_CMD45 <36>
<35> FB_A_D62 FBA_D62 FBA_CMD47 FB_A_CMD47 <35> <36> FB_B_D61 FBB_D61 FBB_CMD46 FB_B_CMD46 <36>
AN40 AF32 A29 H20
<35> FB_A_D63 FBA_D63 FBA_CMD48 AG32 FB_A_CMD48 <35> <36> FB_B_D62 B31 FBB_D62 FBB_CMD47 J20 FB_B_CMD47 <36>
FBA_CMD49 FB_A_CMD49 <35> <36> FB_B_D63 FBB_D63 FBB_CMD48 FB_B_CMD48 <36>
AF40 J21
R35 FBA_CMD50 AG36 FB_A_CMD50 <35> FBB_CMD49 B21 FB_B_CMD49 <36>
<35> FB_A_DBI0 L33 FBA_DQM0 FBA_CMD51 AD39 FB_A_CMD51 <35> F10 FBB_CMD50 H21 FB_B_CMD50 <36>
<35> FB_A_DBI1 FBA_DQM1 FBA_CMD52 FB_A_CMD52 <35> <36> FB_B_DBI0 FBB_DQM0 FBB_CMD51 FB_B_CMD51 <36>
F38 AH35 G4 D20
<35> FB_A_DBI2 P40 FBA_DQM2 FBA_CMD53_NC AG34 <36> FB_B_DBI1 C3 FBB_DQM1 FBB_CMD52 G23 FB_B_CMD52 <36>
<35> FB_A_DBI3 FBA_DQM3 FBA_CMD54_NC <36> FB_B_DBI2 FBB_DQM2 FBB_CMD53_NC
AL35 AH33 B10 E23
<35> FB_A_DBI4 AU34 FBA_DQM4 FBA_CMD55 <36> FB_B_DBI3 F26 FBB_DQM3 FBB_CMD54_NC J23
<35> FB_A_DBI5 AV38 FBA_DQM5 <36> FB_B_DBI4 H30 FBB_DQM4 FBB_CMD55
<35> FB_A_DBI6 FBA_DQM6 <36> FB_B_DBI5 FBB_DQM5
AL39 C35
<35> FB_A_DBI7 FBA_DQM7 <36> FB_B_DBI6 A27 FBB_DQM6
<36> FB_B_DBI7 FBB_DQM7
R37
<35> FB_A_EDC0 H35 FBA_DQS_WP0 D10
<35> FB_A_EDC1 FBA_DQS_WP1 <36> FB_B_EDC0 FBB_DQS_WP0
F40 L37 H3
<35> FB_A_EDC2 R40 FBA_DQS_WP2 FBA_CLK0 M37 FB_A_CLK0 <35> <36> FB_B_EDC1 C1 FBB_DQS_WP1 D6
<35> FB_A_EDC3 FBA_DQS_WP3 FBA_CLK0_N FB_A_CLK#0 <35> <36> FB_B_EDC2 FBB_DQS_WP2 FBB_CLK0 FB_B_CLK0 <36>
AL37 AR38 C11 C6
<35> FB_A_EDC4 AV33 FBA_DQS_WP4 FBA_CLK1 AR37 FB_A_CLK1 <35> <36> FB_B_EDC3 D26 FBB_DQS_WP3 FBB_CLK0_N D29 FB_B_CLK#0 <36>
<35> FB_A_EDC5 AY38 FBA_DQS_WP5 FBA_CLK1_N FB_A_CLK#1 <35> <36> FB_B_EDC4 F33 FBB_DQS_WP4 FBB_CLK1 D30 FB_B_CLK1 <36>
<35> FB_A_EDC6 FBA_DQS_WP6 <36> FB_B_EDC5 FBB_DQS_WP5 FBB_CLK1_N FB_B_CLK#1 <36>
AK38 A35
<35> FB_A_EDC7 FBA_DQS_WP7 <36> FB_B_EDC6 A26 FBB_DQS_WP6
<36> FB_B_EDC7 FBB_DQS_WP7
P38
FBA_WCK01 P39 FB_A_W CK01 <35> E8
FBA_WCK01_N FB_A_W CK#01 <35> FBB_WCK01 FB_B_W CK01 <36>
E39 D8
FBA_WCK23 E40 FB_A_W CK23 <35> FBB_WCK01_N B2 FB_B_W CK#01 <36>
FBA_WCK23_N FB_A_W CK#23 <35> FBB_WCK23 FB_B_W CK23 <36>
AN36 B3
FBA_WCK45 AN37 FB_A_W CK45 <35> FBB_WCK23_N C27 FB_B_W CK#23 <36>
FBA_WCK45_N AW39 FB_A_W CK#45 <35> FBB_WCK45 B27 FB_B_W CK45 <36>
FBA_WCK67 FB_A_W CK67 <35> FBB_WCK45_N FB_B_W CK#45 <36>
AV39 B36
FBA_WCK67_N FB_A_W CK#67 <35> FBB_WCK67 A36 FB_B_W CK67 <36>
FBB_WCK67_N FB_B_W CK#67 <36>
H37
FBA_WCKB01 H38 FB_A_W CKB01 <35> F3
FBA_WCKB01_N N40 FB_A_W CKB#01 <35> FBB_WCKB01 E3 FB_B_W CKB01 <36>
FBA_WCKB23 FB_A_W CKB23 <35> FBB_WCKB01_N FB_B_W CKB#01 <36>
N39 A9
FBA_WCKB23_N AV35 FB_A_W CKB#23 <35> FBB_WCKB23 B9 FB_B_W CKB23 <36>
FBA_WCKB45 FB_A_W CKB45 <35> FBB_WCKB23_N FB_B_W CKB#23 <36>
AV36 D33
FBA_WCKB45_N AM40 FB_A_W CKB#45 <35> FBB_WCKB45 C33 FB_B_W CKB45 <36>
FBA_WCKB67 AM39 FB_A_W CKB67 <35> FBB_WCKB45_N A28 FB_B_W CKB#45 <36>
FBA_WCKB67_N FB_A_W CKB#67 <35> FBB_WCKB67 FB_B_W CKB67 <36>
B28
FB_VREF F35 R31 FBB_WCKB67_N FB_B_W CKB#67 <36>
FB_VREF FB_PLLVDD_3 +FBX_PLLAVDD
RG93 N18P@ K13
FB_PLLVDD_1 +FBX_PLLAVDD
1
1
HCB1005KF-300T25_2P 2
SD034499A80
22U_0603_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
Under GPU
1 1 1 SM01000NV00
CG1460
CG1461
CG1462
2 2 2 Under GPU
+1.35VS_VRAM +1.35VS_VRAM
+1.35VS_VRAM +1.35VS_VRAM
10K_0402_1%
10K_0402_1%
10K_0402_1%
1
1
RG98
RG99
RG202
RG203
10K_0402_1%
10K_0402_1%
10K_0402_1%
10K_0402_1%
1
1
RG100
RG101
RG204
RG205
2
FB_A_CMD14 FB_A_CMD17
2
FB_A_CMD44 FB_A_CMD41 FB_B_CMD14 FB_B_CMD17
FB_B_CMD31
2
2
10K_0402_1%
10K_0402_1%
RG102
RG103
For Reset
2
For Reset
1 1 1 1
10K_0402_1%
10K_0402_1%
RG104
RG105
C767 C768 C769 C770
1
1
4
Partition B CMD Return Path 4
1 1 1 1
C771 C772 C773 C774
1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M 1U_0201_6.3V6M
2 2 2 2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N18E(8/9) MEM Interface_AB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: W ednesday, March 10, 2021 Sheet 33 of 121
A B C D E
5 4 3 2 1
D D
+1V8_AON / +1V8_MAIN
+5VALW +1V8_GPU
+1V8_AON
UG5
1 14
1 2 2 VIN1 VOUT1 13
10U_0402_6.3V6M
CG623 @ VIN1 VOUT1 CG174 1
1V8_AON_EN 3 12 1 2 220P_0402_50V8J
CG175
1U_0201_6.3V6M
ON1 CT1
4 11
VBIAS GND CG176 2
1 GN20P@ 2 1V8_MAIN_EN_R 5 10 1 2 220P_0402_50V8J +1V8_MAIN
RG258 0_0402_5% ON2 CT2
6 9
0.1U_0201_10V6K
VIN2 VOUT2
1
1V8_MAIN_EN 1 N18P@ 2 1 7 8
VIN2 VOUT2
10U_0402_6.3V6M
CG177
RG1631 0_0402_5% RG1633 RG123
15
1U_0201_6.3V6M
100K_0402_5% 100K_0402_5% 2 GPAD 1
CG624
CG178
@
N18P@ 2 EM5209VF_DFN14_3X2
2
1 2
Change UG5 from SA00006U300 to SA00007PM00
+3VS +3VALW
1
@
RG1634 RG1635
0_0402_5% 0_0402_5% UV51
C C
2
2
0.1U_0201_10V6K 2 1 CV541 1 20 RG1621 1 N18P@ 2 0_0201_5% 1V8_MAIN_EN
VDD 1V8_MAIN_EN
RG1612 1 N18P@ 2 0_0201_5%
<28> N18P_1V8_MAIN_EN
RG1630 1 GN20P@ 2 0_0201_5% 2 19 RG1622 1 @ 2 0_0201_5%
DGPU_PEX_RST# <27,28>
<28> NVVDD_GPU_EN 1V8_MAIN_EN_GPU PEGX_RST#
From PCH <12,58> RG1613 1 @ 2 0_0201_5% 3 18 RG1623 1 @ 2 0_0201_5%
0.95VS_DGPU_EN <110>
DGPU_PWR_EN DGPU_PWR_EN PEX_VDD_EN
RG1614 1 @ 2 0_0201_5% 4
<28> GPU_GC6_FB_EN GC6_FB_EN_GPU 17 RG1624 1 @ 2 0_0201_5%
1.35VSDGPU_EN <108>
RG1615 1 @ 2 0_0201_5% 5 FB_VDD_EN
<103> NVVDD_PGOOD PEX_VDD_PG
11
GND
SLG4U44431VTR
SA0000E4Q00
B
1V8 NVVDD PEXVDD VPP FBVDD B
+0.95VS_S0
1
@
+5VS RG286 RG1698
+1V8_AON 51_0201_5% 51_0201_5%
+1V8_MAIN +1.35VS_VRAM +NVVDD
2
2
1
RG287
PJT138KA_SOT363-6
1
10_0603_1%
10_0603_1%
RG138
RG139
3
47_0603_5% 51_0201_5% 51_0201_5% 1
QG27B
2
2
2
2
RG140 5
PJT138KA_SOT363-6
PJT138KA_SOT363-6
PJT138KA_SOT363-6
10K_0201_5% 10K_0201_5% 10K_0201_5%
4
3
1
6
QG10B
1
QG11B
QG26B
QG27A
5
QG12B
A 5 5 5 0.95VS_DGPU_EN 2 A
PJT138KA_SOT363-6
PJT138KA_SOT363-6
PJT138KA_SOT363-6
PJT138KA_SOT363-6
4
1
6
6
QG10A
QG26A
1V8_AON_EN 2
QG11A
QG12A
Date:
Date: Wednesday, March 10, 2021 Sheet
Sheet 34 of 121
5 4 3 2 1
A B C D E
VRAM A
1 1
UV11 @ UV12 @
C2 B4 C2 B4
<33> FB_A_EDC1 C13 EDC0_A DQ0_A A3 FB_A_D9 <33> <33> FB_A_EDC4 C13 EDC0_A DQ0_A A3 FB_A_D35 <33>
<33> FB_A_EDC0 EDC1_A DQ1_A FB_A_D13 <33> <33> FB_A_EDC5 EDC1_A DQ1_A FB_A_D34 <33>
T2 B3 T2 B3
<33> FB_A_EDC2 T13 EDC0_B DQ2_A B2 FB_A_D10 <33> <33> FB_A_EDC7 T13 EDC0_B DQ2_A B2 FB_A_D33 <33>
<33> FB_A_EDC3 EDC1_B DQ3_A E3 FB_A_D14 <33> <33> FB_A_EDC6 EDC1_B DQ3_A E3 FB_A_D32 <33>
DQ4_A FB_A_D12 <33> DQ4_A FB_A_D39 <33>
E2 E2
D2 DQ5_A F2 FB_A_D15 <33> D2 DQ5_A F2 FB_A_D37 <33>
<33> FB_A_DBI1 DBI0#_A DQ6_A FB_A_D8 <33> <33> FB_A_DBI4 DBI0#_A DQ6_A FB_A_D38 <33>
D13 G2 D13 G2
<33> FB_A_DBI0 R2 DBI1#_A DQ7_A B11 FB_A_D11 <33> <33> FB_A_DBI5 R2 DBI1#_A DQ7_A B11 FB_A_D36 <33>
<33> FB_A_DBI2 R13 DBI0#_B DQ8_A A12 FB_A_D6 <33> <33> FB_A_DBI7 R13 DBI0#_B DQ8_A A12 FB_A_D40 <33>
<33> FB_A_DBI3 DBI1#_B DQ9_A FB_A_D4 <33> <33> FB_A_DBI6 DBI1#_B DQ9_A FB_A_D47 <33>
B12 B12
DQ10_A B13 FB_A_D5 <33> DQ10_A B13 FB_A_D44 <33>
DQ11_A FB_A_D7 <33> DQ11_A FB_A_D46 <33>
J10 E12 J10 E12
<33> FB_A_CLK0 K10 CK_T DQ12_A E13 FB_A_D1 <33> <33> FB_A_CLK1 K10 CK_T DQ12_A E13 FB_A_D41 <33>
<33> FB_A_CLK#0 G10 CK_C DQ13_A F13 FB_A_D2 <33> <33> FB_A_CLK#1 G10 CK_C DQ13_A F13 FB_A_D45 <33>
<33> FB_A_CMD14 CKE#_A DQ14_A FB_A_D0 <33> <33> FB_A_CMD44 CKE#_A DQ14_A FB_A_D43 <33>
M10 G13 M10 G13
<33> FB_A_CMD17 CKE#_B DQ15_A FB_A_D3 <33> <33> FB_A_CMD41 CKE#_B DQ15_A FB_A_D42 <33>
U4 U4
DQ0_B V3 FB_A_D16 <33> DQ0_B V3 FB_A_D63 <33>
DQ1_B U3 FB_A_D22 <33> DQ1_B U3 FB_A_D61 <33>
DQ2_B FB_A_D23 <33> DQ2_B FB_A_D60 <33>
J5 U2 J5 U2
<33> FB_A_CMD10 K5 CABI#_A DQ3_B P3 FB_A_D17 <33> <33> FB_A_CMD37 K5 CABI#_A DQ3_B P3 FB_A_D57 <33>
<33> FB_A_CMD9 CABI#_B DQ4_B FB_A_D19 <33> <33> FB_A_CMD38 CABI#_B DQ4_B FB_A_D59 <33>
P2 P2
DQ5_B N2 FB_A_D21 <33> DQ5_B N2 FB_A_D62 <33>
DQ6_B M2 FB_A_D20 <33> DQ6_B M2 FB_A_D58 <33>
DQ7_B FB_A_D18 <33> DQ7_B FB_A_D56 <33>
U11 U11
DQ8_B V12 FB_A_D25 <33> DQ8_B V12 FB_A_D54 <33>
DQ9_B FB_A_D29 <33> DQ9_B FB_A_D51 <33>
RG144 2 1 121_0402_1% J14 U12 RG145 2 1 121_0402_1% J14 U12
2 1 K14 ZQ_A DQ10_B U13 FB_A_D28 <33> 2 1 K14 ZQ_A DQ10_B U13 FB_A_D53 <33>
RG143 121_0402_1% RG146 121_0402_1%
ZQ_B DQ11_B P12 FB_A_D30 <33> ZQ_B DQ11_B P12 FB_A_D55 <33>
DQ12_B FB_A_D27 <33> DQ12_B FB_A_D48 <33>
P13 P13
DQ13_B N13 FB_A_D26 <33> DQ13_B N13 FB_A_D50 <33>
DQ14_B FB_A_D31 <33> DQ14_B FB_A_D49 <33>
M13 M13
DQ15_B FB_A_D24 <33> DQ15_B FB_A_D52 <33>
N5 H3 N5 H3
F10 TCK CA0_A G11 FB_A_CMD1 <33> F10 TCK CA0_A G11 FB_A_CMD33 <33>
TDI CA1_A FB_A_CMD13 <33> TDI CA1_A FB_A_CMD45 <33>
N10 G4 N10 G4
F5 TDO CA2_A H12 FB_A_CMD12 <33> F5 TDO CA2_A H12 FB_A_CMD35 <33>
TMS CA3_A H5 FB_A_CMD24 <33> TMS CA3_A H5 FB_A_CMD46 <33>
CA4_A FB_A_CMD11 <33> CA4_A FB_A_CMD36 <33>
2 H10 H10 2
CA5_A J12 FB_A_CMD15 <33> CA5_A J12 FB_A_CMD43 <33>
CA6_A FB_A_CMD22 <33> CA6_A FB_A_CMD48 <33>
D4 J11 D4 J11
<33> FB_A_W CKB01 D5 WCK0_T_A CA7_A J4 FB_A_CMD23 <33> <33> FB_A_W CK45 D5 WCK0_T_A CA7_A J4 FB_A_CMD47 <33>
<33> FB_A_W CKB#01 D11 WCK0_C_A CA8_A J3 FB_A_CMD0 <33> <33> FB_A_W CK#45 D11 WCK0_C_A CA8_A J3 FB_A_CMD34 <33>
<33> FB_A_W CK01 WCK1_T_A CA9_A FB_A_CMD2 <33> <33> FB_A_W CKB45 WCK1_T_A CA9_A FB_A_CMD32 <33>
D10 D10
<33> FB_A_W CK#01 WCK1_C_A L3 <33> FB_A_W CKB#45 WCK1_C_A L3
CA0_B FB_A_CMD5 <33> CA0_B FB_A_CMD29 <33>
M11 M11
+1.35VS_VRAM R4 CA1_B M4 FB_A_CMD18 <33> R4 CA1_B M4 FB_A_CMD52 <33>
<33> FB_A_W CK23 R5 WCK0_T_B CA2_B L12 FB_A_CMD7 <33> <33> FB_A_W CKB67 R5 WCK0_T_B CA2_B L12 FB_A_CMD40 <33>
<33> FB_A_W CK#23 WCK0_C_B CA3_B FB_A_CMD20 <33> <33> FB_A_W CKB#67 WCK0_C_B CA3_B FB_A_CMD50 <33>
R11 L5 R11 L5
<33> FB_A_W CKB23 WCK1_T_B CA4_B FB_A_CMD8 <33> <33> FB_A_W CK67 WCK1_T_B CA4_B FB_A_CMD39 <33>
1
RG148 @ J1 E1 J1 E1
CG180
CG181
1 1
1K_0402_1%
820P_0402_25V7
D VDDQ3 VDDQ3
1
L1 L1
2 Q1 @ @ B1 VDDQ4 P1 B1 VDDQ4 P1
<28,36> MEM_VREF 2 2 D1 VSS1 VDDQ5 T1 D1 VSS1 VDDQ5 T1
G @
VSS2 VDDQ6 VSS2 VDDQ6
2
S MESS138W -G_SOT323-3 F1 J2 F1 J2
VSS3 VDDQ7 VSS3 VDDQ7
3
G1 K2 G1 K2
M1 VSS4 VDDQ8 C4 M1 VSS4 VDDQ8 C4
N1 VSS5 VDDQ9 F4 N1 VSS5 VDDQ9 F4
R1 VSS6 VDDQ10 N4 R1 VSS6 VDDQ10 N4
U1 VSS7 VDDQ11 T4 U1 VSS7 VDDQ11 T4
A2 VSS8 VDDQ12 B5 A2 VSS8 VDDQ12 B5
V2 VSS9 VDDQ13 U5 V2 VSS9 VDDQ13 U5
C3 VSS10 VDDQ14 B10 C3 VSS10 VDDQ14 B10
D3 VSS11 VDDQ15 U10 D3 VSS11 VDDQ15 U10
F3 VSS12 VDDQ16 C11 F3 VSS12 VDDQ16 C11
G3 VSS13 VDDQ17 F11 G3 VSS13 VDDQ17 F11
M3 VSS14 VDDQ18 N11 M3 VSS14 VDDQ18 N11
N3 VSS15 VDDQ19 T11
10UF_0603 X 2 pcs N3 VSS15 VDDQ19 T11
R3 VSS16 VDDQ20 J13 22UF_0603 X 6 pcs R3 VSS16 VDDQ20 J13
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
L4 L14 L4 L14
10UF_0603 X 2 pcs P4 VSS22 VDDQ26 P14
1 1 1 1 1 1 1 1
P4 VSS22 VDDQ26 P14
22UF_0603 X 6 pcs
CG1520
CG1521
CG1522
CG1523
CG1524
CG1525
CG1526
CG1527
V4 VSS23 VDDQ27 T14 V4 VSS23 VDDQ27 T14
Around GDDR6 UG11
+1.35VS_VRAM
C5 VSS24 VDDQ28 +1.35VS_VRAM C5 VSS24 VDDQ28 +1.35VS_VRAM
T5 VSS25 2 2 2 2 2 2 2 2 T5 VSS25
C10 VSS26 A1 C10 VSS26 A1
T10 VSS27 VDD1 V1 T10 VSS27 VDD1 V1
VSS28 VDD2 VSS28 VDD2
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
3
1 1 1 1 1 1 1 1 A11 H2 A11 H2 3
E11 VSS29 VDD3 L2 E11 VSS29 VDD3 L2
CG1486
CG1487
CG1488
CG1489
CG1490
CG1491
CG1492
CG1493
330U_D1_2VY_R9M
F14 G5 F14 G5
teknisi-indonesia.com
VSS47 NC1 1 VSS47 NC1
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
G14 M5 1 1 1 1 G14 M5
M14 VSS48 NC2 + M14 VSS48 NC2
1UF_0402 X 4 pcs +1.35VS_VRAM
C3001
CG1528
CG1529
CG1530
CG1531
+1V8_AON N14 VSS49 N14 VSS49
1
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
+ MT61K256M32JE-13-A_FBGA180~D MT61K256M32JE-13-A_FBGA180~D
C3000
1 1 1 1
CG1494
CG1495
CG1496
CG1497
MT61K256M32JE-13-A_FBGA_180P MT61K256M32JE-13-A_FBGA_180P
2
2 2 2 2
RF
1UF_0402 X 18 pcs
10UF_0603 X 4 pcs Close to GDDR6 UG12 +1.35VS_VRAM +1.35VS_VRAM
CG1532
CG1533
CG1534
CG1535
CG1536
CG1537
CG1538
CG1539
CG1540
CG1541
CG1542
CG1543
CG1544
CG1545
CG1546
CG1547
CG1548
CG1549
CG1550
CG1551
CG1552
CG1553
10P_0201_50V8J
CG1624 @RF@
10P_0201_50V8J
CG1625 @RF@
10P_0201_50V8J
CG1626 @RF@
10P_0201_50V8J
CG1627 @RF@
10P_0201_50V8J
CG1628 @RF@
10P_0201_50V8J
CG1629 @RF@
10P_0201_50V8J
CG1630 @RF@
10P_0201_50V8J
CG1631 @RF@
10P_0201_50V8J
CG1632 @RF@
10P_0201_50V8J
CG1633 @RF@
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2
1UF_0402 X 18 pcs
10UF_0603 X 4 pcs Close to GDDR6 UG11 +1.35VS_VRAM
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
CG1498
CG1499
CG1500
CG1501
CG1502
CG1503
CG1504
CG1505
CG1506
CG1507
CG1508
CG1509
CG1510
CG1511
CG1512
CG1513
CG1514
CG1515
CG1516
CG1517
CG1518
CG1519
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
4 4
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GDDR6_A_CH2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: W ednesday, March 10, 2021 Sheet 35 of 121
A B C D E
A B C D E
VRAM B
1 1
UV13 @ UV14 @
C2 B4 C2 B4
<33> FB_B_EDC1 C13 EDC0_A DQ0_A A3 FB_B_D11 <33> <33> FB_B_EDC4 C13 EDC0_A DQ0_A A3 FB_B_D38 <33>
<33> FB_B_EDC0 EDC1_A DQ1_A FB_B_D13 <33> <33> FB_B_EDC5 EDC1_A DQ1_A FB_B_D35 <33>
T2 B3 T2 B3
<33> FB_B_EDC2 T13 EDC0_B DQ2_A B2 FB_B_D15 <33> <33> FB_B_EDC7 T13 EDC0_B DQ2_A B2 FB_B_D37 <33>
<33> FB_B_EDC3 EDC1_B DQ3_A E3 FB_B_D8 <33> <33> FB_B_EDC6 EDC1_B DQ3_A E3 FB_B_D34 <33>
DQ4_A FB_B_D12 <33> DQ4_A FB_B_D39 <33>
E2 E2
D2 DQ5_A F2 FB_B_D14 <33> D2 DQ5_A F2 FB_B_D36 <33>
<33> FB_B_DBI1 DBI0#_A DQ6_A FB_B_D9 <33> <33> FB_B_DBI4 DBI0#_A DQ6_A FB_B_D33 <33>
D13 G2 D13 G2
<33> FB_B_DBI0 R2 DBI1#_A DQ7_A B11 FB_B_D10 <33> <33> FB_B_DBI5 R2 DBI1#_A DQ7_A B11 FB_B_D32 <33>
<33> FB_B_DBI2 R13 DBI0#_B DQ8_A A12 FB_B_D0 <33> <33> FB_B_DBI7 R13 DBI0#_B DQ8_A A12 FB_B_D41 <33>
<33> FB_B_DBI3 DBI1#_B DQ9_A FB_B_D7 <33> <33> FB_B_DBI6 DBI1#_B DQ9_A FB_B_D44 <33>
B12 B12
DQ10_A B13 FB_B_D5 <33> DQ10_A B13 FB_B_D42 <33>
DQ11_A FB_B_D2 <33> DQ11_A FB_B_D47 <33>
J10 E12 J10 E12
<33> FB_B_CLK0 K10 CK_T DQ12_A E13 FB_B_D3 <33> <33> FB_B_CLK1 K10 CK_T DQ12_A E13 FB_B_D40 <33>
<33> FB_B_CLK#0 G10 CK_C DQ13_A F13 FB_B_D6 <33> <33> FB_B_CLK#1 G10 CK_C DQ13_A F13 FB_B_D46 <33>
<33> FB_B_CMD14 CKE#_A DQ14_A FB_B_D4 <33> <33> FB_B_CMD44 CKE#_A DQ14_A FB_B_D45 <33>
M10 G13 M10 G13
<33> FB_B_CMD17 CKE#_B DQ15_A FB_B_D1 <33> <33> FB_B_CMD41 CKE#_B DQ15_A FB_B_D43 <33>
U4 U4
DQ0_B V3 FB_B_D16 <33> DQ0_B V3 FB_B_D63 <33>
DQ1_B U3 FB_B_D22 <33> DQ1_B U3 FB_B_D58 <33>
DQ2_B FB_B_D20 <33> DQ2_B FB_B_D61 <33>
J5 U2 J5 U2
<33> FB_B_CMD10 K5 CABI#_A DQ3_B P3 FB_B_D23 <33> <33> FB_B_CMD37 K5 CABI#_A DQ3_B P3 FB_B_D62 <33>
<33> FB_B_CMD9 CABI#_B DQ4_B FB_B_D17 <33> <33> FB_B_CMD38 CABI#_B DQ4_B FB_B_D56 <33>
P2 P2
DQ5_B N2 FB_B_D18 <33> DQ5_B N2 FB_B_D57 <33>
DQ6_B M2 FB_B_D19 <33> DQ6_B M2 FB_B_D60 <33>
DQ7_B FB_B_D21 <33> DQ7_B FB_B_D59 <33>
U11 U11
DQ8_B V12 FB_B_D31 <33> DQ8_B V12 FB_B_D53 <33>
DQ9_B FB_B_D25 <33> DQ9_B FB_B_D48 <33>
RG150 2 1 121_0402_1% J14 U12 RG151 2 1 121_0402_1% J14 U12
2 1 K14 ZQ_A DQ10_B U13 FB_B_D30 <33> 2 1 K14 ZQ_A DQ10_B U13 FB_B_D51 <33>
RG152 121_0402_1% RG153 121_0402_1%
ZQ_B DQ11_B P12 FB_B_D29 <33> ZQ_B DQ11_B P12 FB_B_D50 <33>
DQ12_B FB_B_D27 <33> DQ12_B FB_B_D55 <33>
P13 P13
DQ13_B N13 FB_B_D26 <33> DQ13_B N13 FB_B_D52 <33>
DQ14_B FB_B_D28 <33> DQ14_B FB_B_D54 <33>
M13 M13
DQ15_B FB_B_D24 <33> DQ15_B FB_B_D49 <33>
N5 H3 N5 H3
F10 TCK CA0_A G11 FB_B_CMD1 <33> F10 TCK CA0_A G11 FB_B_CMD33 <33>
TDI CA1_A FB_B_CMD13 <33> TDI CA1_A FB_B_CMD45 <33>
N10 G4 N10 G4
F5 TDO CA2_A H12 FB_B_CMD12 <33> F5 TDO CA2_A H12 FB_B_CMD35 <33>
TMS CA3_A H5 FB_B_CMD24 <33> TMS CA3_A H5 FB_B_CMD46 <33>
CA4_A FB_B_CMD11 <33> CA4_A FB_B_CMD36 <33>
2 H10 H10 2
CA5_A J12 FB_B_CMD15 <33> CA5_A J12 FB_B_CMD43 <33>
CA6_A FB_B_CMD22 <33> CA6_A FB_B_CMD48 <33>
D4 J11 D4 J11
<33> FB_B_W CKB01 D5 WCK0_T_A CA7_A J4 FB_B_CMD23 <33> <33> FB_B_W CK45 D5 WCK0_T_A CA7_A J4 FB_B_CMD47 <33>
<33> FB_B_W CKB#01 D11 WCK0_C_A CA8_A J3 FB_B_CMD0 <33> <33> FB_B_W CK#45 D11 WCK0_C_A CA8_A J3 FB_B_CMD34 <33>
<33> FB_B_W CK01 WCK1_T_A CA9_A FB_B_CMD2 <33> <33> FB_B_W CKB45 WCK1_T_A CA9_A FB_B_CMD32 <33>
D10 D10
+1.35VS_VRAM <33> FB_B_W CK#01 WCK1_C_A L3 <33> FB_B_W CKB#45 WCK1_C_A L3
CA0_B FB_B_CMD5 <33> CA0_B FB_B_CMD29 <33>
M11 M11
R4 CA1_B M4 FB_B_CMD18 <33> R4 CA1_B M4 FB_B_CMD52 <33>
<33> FB_B_W CK23 WCK0_T_B CA2_B FB_B_CMD7 <33> <33> FB_B_W CKB67 WCK0_T_B CA2_B FB_B_CMD40 <33>
1
@ R5 L12 R5 L12
<33> FB_B_W CK#23 WCK0_C_B CA3_B FB_B_CMD20 <33> <33> FB_B_W CKB#67 WCK0_C_B CA3_B FB_B_CMD50 <33>
RG293 R11 L5 R11 L5
<33> FB_B_W CKB23 R10 WCK1_T_B CA4_B L10 FB_B_CMD8 <33> <33> FB_B_W CK67 R10 WCK1_T_B CA4_B L10 FB_B_CMD39 <33>
549_0402_1%
<33> FB_B_W CKB#23 WCK1_C_B CA5_B FB_B_CMD16 <33> <33> FB_B_W CK#67 WCK1_C_B CA5_B FB_B_CMD42 <33>
K12 K12
CA6_B K11 FB_B_CMD21 <33> CA6_B K11 FB_B_CMD49 <33>
W=16mils CA7_B FB_B_CMD19 <33> CA7_B FB_B_CMD51 <33>
2
K4 K4
+FBB_VREFC CA8_B FB_B_CMD6 <33> CA8_B FB_B_CMD28 <33>
1 2 K3 K3
+FBB_VREFC K1 CA9_B FB_B_CMD4 <33> +1.35VS_VRAM +FBB_VREFC K1 CA9_B FB_B_CMD30 <33> +1.35VS_VRAM
VREFC VREFC
1
RG294 @ 1 1
CG1109
CG1110
1K_0402_1%
820P_0402_25V7
820P_0402_25V7
931_0402_1% C1 C1
RG295
D VDDQ1 VDDQ1
1
J1 E1 J1 E1
<33> FB_B_CMD3 RESET# VDDQ2 <33> FB_B_CMD31 RESET# VDDQ2
2 Q2 @ @ H1 H1
<28,35> MEM_VREF 2 2 VDDQ3 L1 VDDQ3 L1
G @
VDDQ4 VDDQ4
2
S MESS138W -G_SOT323-3 B1 P1 B1 P1
VSS1 VDDQ5 VSS1 VDDQ5
3
D1 T1 D1 T1
F1 VSS2 VDDQ6 J2 F1 VSS2 VDDQ6 J2
G1 VSS3 VDDQ7 K2 G1 VSS3 VDDQ7 K2
M1 VSS4 VDDQ8 C4 M1 VSS4 VDDQ8 C4
N1 VSS5 VDDQ9 F4 N1 VSS5 VDDQ9 F4
R1 VSS6 VDDQ10 N4 R1 VSS6 VDDQ10 N4
U1 VSS7 VDDQ11 T4 U1 VSS7 VDDQ11 T4
A2 VSS8 VDDQ12 B5 A2 VSS8 VDDQ12 B5
V2 VSS9 VDDQ13 U5 V2 VSS9 VDDQ13 U5
C3 VSS10 VDDQ14 B10 C3 VSS10 VDDQ14 B10
D3 VSS11 VDDQ15 U10 D3 VSS11 VDDQ15 U10
F3 VSS12 VDDQ16 C11 F3 VSS12 VDDQ16 C11
G3 VSS13 VDDQ17 F11 G3 VSS13 VDDQ17 F11
M3 VSS14 VDDQ18 N11 M3 VSS14 VDDQ18 N11
N3 VSS15 VDDQ19 T11 N3 VSS15 VDDQ19 T11
R3 VSS16 VDDQ20 J13 R3 VSS16 VDDQ20 J13
T3 VSS17 VDDQ21 K13
10UF_0603 X 2 pcs T3 VSS17 VDDQ21 K13
A4 VSS18 VDDQ22 C14 22UF_0603 X 6 pcs A4 VSS18 VDDQ22 C14
10UF_0603 X 2 pcs
Around GDDR6 UG14
+1.35VS_VRAM
E4 VSS19 VDDQ23 E14 E4 VSS19 VDDQ23 E14
22UF_0603 X 6 pcs H4 VSS20 VDDQ24 H14 H4 VSS20 VDDQ24 H14
Around GDDR6 UG13
+1.35VS_VRAM
L4 VSS21 VDDQ25 L14 L4 VSS21 VDDQ25 L14
P4 VSS22 VDDQ26 P14 P4 VSS22 VDDQ26 P14
VSS23 VDDQ27 VSS23 VDDQ27
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
V4 T14 1 1 1 1 1 1 1 1 V4 T14
C5 VSS24 VDDQ28 +1.35VS_VRAM C5 VSS24 VDDQ28 +1.35VS_VRAM
CG1588
CG1589
CG1590
CG1591
CG1592
CG1593
CG1594
CG1595
VSS25 VSS25
10U_0402_6.3V6M
10U_0402_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1 1 1 1 1 1 1 1 T5 T5
C10 VSS26 A1 C10 VSS26 A1
CG1554
CG1555
CG1556
CG1557
CG1558
CG1559
CG1560
CG1561
Close to GDDR6 UG13 Close to GDDR6 UG13 VSS47 NC1 VSS47 NC1
330U_D1_2VY_R9M
G14 M5 1 G14 M5
VSS48 NC2 VSS48 NC2
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
M14 1 1 1 1 M14
N14 VSS49 + N14 VSS49
C3003
CG1596
CG1597
CG1598
CG1599
VSS50 VSS50
330U_D1_2VY_R9M
1 R14 R14
U14 VSS51 U14 VSS51
180-BALL 180-BALL
VSS52 VSS52
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1
@
CG1562
CG1563
CG1564
CG1565
2 MT61K256M32JE-13-A_FBGA180~D MT61K256M32JE-13-A_FBGA180~D
2 2 2 2 @ MT61K256M32JE-13-A_FBGA_180P MT61K256M32JE-13-A_FBGA_180P
1UF_0402 X 18 pcs
10UF_0603 X 4 pcs Close to GDDR6 UG14 +1.35VS_VRAM
1UF_0402 X 18 pcs
10UF_0603 X 4 pcs Close to GDDR6 UG13 +1.35VS_VRAM
CG1600
CG1601
CG1602
CG1603
CG1604
CG1605
CG1606
CG1607
CG1608
CG1609
CG1610
CG1611
CG1612
CG1613
CG1614
CG1615
CG1616
CG1617
CG1618
CG1619
CG1620
CG1621
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CG1566
CG1567
CG1568
CG1569
CG1570
CG1571
CG1572
CG1573
CG1574
CG1575
CG1576
CG1577
CG1578
CG1579
CG1580
CG1581
CG1582
CG1583
CG1584
CG1585
CG1586
CG1587
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GDDR6_B_CH2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: W ednesday, March 10, 2021 Sheet 36 of 121
A B C D E
A B C D E
680P_0402_50V7K .1U_0402_16V7K
1
1
C8100
0_0402_5%
0_0402_5%
Power Monitor(OVR-M)
@
2 RG289
2 RG288
@
SH_IN_N1 2
1 RG290 1
1 @ 2
SH_IN_P2_R
1 1 0_0402_5%
CG1623
CG612
@
1U_0402_6.3V6K
SH_IN_N2 2 2
UG19 @ +3V_OVRM
1000P_0402_50V7K
1000P_0402_50V7K
RG175 1 2 0_0402_5% BS_IN4 14 1 SH_IN_N1 RG176 1 2 0_0402_5% CSSN_B+
BS_IN4 SH_IN_N1 CSSN_B+ <104>
1
5 SH_IN_P2 RG177 1 @ 2 49.9_0402_1% SH_IN_P2_R RG291 1 @ 2 49.9_0402_1% CSSP_FBVDD
SH_IN_P2 SH_IN_N2 CSSN_FBVDD CSSP_FBVDD <104>
CG614 CG613 RG178 1 45492@ 2 649_0402_1% 4 RG179 1 2 0_0402_5%
1 45492@ 2 649_0402_1% 9 SH_IN_N2 12 CSSN_FBVDD <104>
45492@ 45492@ RG180
GND_FET SH_IN_P3
2
13
RG183 1 @ 2 0_0402_5% SH_IN_N3 15 RG1699 1 @ 2 0_0402_5% CSSP_FBVDD @
SH_O1 32 SH_IN_P4 16 RG1700 1 @ 2 0_0402_5% CG615 1 2 47P_0402_50V8J
SH_O2 7 SH_O1 SH_IN_N4
10 SH_O2 20
BG_REF_R SH_O4 SH_O3 DIFF_OUT_P ADC_IN_P <28>
RG239 1 45495@ 2 0_0402_5% 17 19
RG186
0.015U_0402_25V7K CG616
RG237
RG187
0.015U_0402_25V7K CG617
SH_O4 DIFF_OUT_N ADC_IN_N <28>
30 BS_OK
BS_OK
1
1 1
0_0402_5%
0_0402_5%
RG1901 2 0_0402_5% 29 8 MS_IMON RG2461 45495@ 2 0_0402_5%
2 RG191
2 RG192
<28> ADC_MUX_SEL MUX_SEL NC BV_REF BS_REF_R
2
18 RG2481 45495@ 2 0_0402_5%
NC 21 ADRS0 RG193 RG194 @ @
45492@
45492@
45495@
45492@
45492@
0_0402_5%
475_0402_1%
475_0402_1%
2 2 OVRM_EN# 28 NC 31 SYNC @ PAD~D T26 243K_0402_1% 365K_0402_1%
ENABLE NC
2
@ 45492@
23 BG_REF_OUT RG2521 45492@ 2 0_0402_5% BG_REF_R
47P_0402_50V8J
47P_0402_50V8J
BG_REF_OUT
1
PEM_SKIP_R BS_REF BS_REF_R
1
25 24 RG2511 45492@ 2 0_0402_5%
CG618
CG619
SKIP BS_REF 22 CM_REF_IN
CM_REF_IN @ @
2
MODE_SEL 26 33
MODE_SEL GND 1 2 2
2
CG620
CG621
1000p_0402_50V7K
1000p_0402_50V7K
CG622 45492@ RG196
NCP45495XMNTWG_QFN32_4X4 1000p_0402_50V7K RG195 681K_0402_1%
2 1 1 10K_0402_5% @
1
10K_0201_5%
10K_0402_5%
1
RG199
RG197
@
2
BG_REF_OUT RG2531 45495@ 2 0_0402_5%
BS_REF VGA_I2CC_SCL_R_Q <28,103>
RG2541 45495@ 2 0_0402_5%
VGA_I2CC_SDA_R_Q <28,103>
2 2
+3V_OVRM
45495
NCP45495 0_0402_5% 0_0402_5% 0_0402_5% 49.9_0402_1% 49.9_0402_1% 10K_0402_5% 31.6K_0402_1% .1U_0402_16V7K 0_0402_5% 0_0402_5% 680P_0402_50V7K 10K_0402_5%
SA0000DUX00 SD028000080 SD028000080 SD028000080 SD034499A80 SD034499A80 SD028100280 SD034316280 SE076104K80 SD028000080 SD028000080 SE074681K80 SD028100280
UG19 UPI@ RG171 UPI@ RG172 UPI@ RG174 UPI@ RG177 UPI@ RG291 UPI@ RG196 UPI@ RG193 UPI@ RG1700 UPI@ RG1605 UPI@ RG194 UPI@
45492
UPI
NCP45492 75K_0402_1% 75K_0402_1% 100_0402_1% 49.9_0402_1% 49.9_0402_1% 681K_0402_1% 243K_0402_1% .1U_0402_16V7K 0_0402_5% 0_0402_5% 680P_0402_50V7K 10K_0402_5%
SA0000CQX00 SD034750280 SD034750280 SD034100080 SD034499A80 SD034499A80 SD034681380 SD000004200 SE076104K80 SD028000080 SD028000080 SE074681K80 SD028100280
US5650QQKI 75K_0402_1% 75K_0402_1% 100_0402_1% 49.9_0402_1% 49.9_0402_1% 681K_0402_1% 324K_0402_1% 0_0402_5% 0_0402_5% 365K_0402_1%
SA0000CMA00 SD034750280 SD034750280 SD034100080 SD034499A80 SD034499A80 SD034681380 SD034324380 SD028000080 SD028000080 SD034365380
RG251 UPI@ RG178 UPI@ RG180 UPI@ CG613 UPI@ CG614 UPI@ RG186 UPI@ RG187 UPI@ CG616 UPI@ CG617 UPI@ CG622 UPI@ RG252 UPI@
0_0402_5% 487_0402_1% 487_0402_1% 1000P_0402_50V7K 1000P_0402_50V7K 357_0402_1% 357_0402_1% 0.015U_0402_25V7K 0.015U_0402_25V7K 1000P_0402_50V7K 0_0402_5%
SD028000080 SD00000EL80 SD00000EL80 SE074102K80 SE074102K80 SD034357080 SD034357080 SE075153K80 SE075153K80 SE074102K80 SD028000080
OVR-M Gen1 (Onsemi) (GN20) (Reserve Only) OVR-M Gen1 (UPI) (GN20) (Reserve Only)
RG194 UPI_ForGN20Gen1@
UG19 45492_ForGN20Gen1@
RG171 45492_ForGN20Gen1@
RG172 45492_ForGN20Gen1@
RG174 45492_ForGN20Gen1@
RG177 45492_ForGN20Gen1@
RG291 45492_ForGN20Gen1@
RG196 45492_ForGN20Gen1@
RG193 45492_ForGN20Gen1@
CG1623 45492_ForGN20Gen1@
RG183 45492_ForGN20Gen1@
RG1699 45492_ForGN20Gen1@
C8100 45492_ForGN20Gen1@
RG1605 45492_ForGN20Gen1@ UG19 UPI_ForGN20Gen1@
RG171 UPI_ForGN20Gen1@
RG172 UPI_ForGN20Gen1@
RG174 UPI_ForGN20Gen1@
RG177 UPI_ForGN20Gen1@
RG291 UPI_ForGN20Gen1@
RG196 UPI_ForGN20Gen1@
RG193 UPI_ForGN20Gen1@
RG1700 UPI_ForGN20Gen1@
RG1605 UPI_ForGN20Gen1@
45492 UPI
365K_0402_1%
NCP45492 75K_0402_1% 75K_0402_1% 100_0402_1% 49.9_0402_1% 49.9_0402_1% 681K_0402_1% 237K_0402_1% .1U_0402_16V7K 0_0402_5% 0_0402_5% 680P_0402_50V7K 10K_0402_5% US5650QQKI 75K_0402_1% 75K_0402_1% 100_0402_1% 49.9_0402_1% 49.9_0402_1% 681K_0402_1% 316K_0402_1% 0_0402_5% 0_0402_5% SD034365380
SA0000CQX00 SD034750280 SD034750280 SD034100080 SD034499A80 SD034499A80 SD034681380 SD034237380 SE076104K80 SD028000080 SD028000080 SE074681K80 SD028100280 SA0000CMA00 SD034750280 SD034750280 SD034100080 SD034499A80 SD034499A80 SD034681380 SD034316380 SD028000080 SD028000080
RG178 45492_ForGN20Gen1@
RG180 45492_ForGN20Gen1@
CG613 45492_ForGN20Gen1@
CG614 45492_ForGN20Gen1@
RG186 45492_ForGN20Gen1@
RG187 45492_ForGN20Gen1@
CG616 45492_ForGN20Gen1@
CG617 45492_ForGN20Gen1@
CG622 45492_ForGN20Gen1@ RG251 UPI_ForGN20Gen1@
RG178 UPI_ForGN20Gen1@
RG180 UPI_ForGN20Gen1@
CG613 UPI_ForGN20Gen1@
CG614 UPI_ForGN20Gen1@
RG186 UPI_ForGN20Gen1@
RG187 UPI_ForGN20Gen1@
CG616 UPI_ForGN20Gen1@
CG617 UPI_ForGN20Gen1@
CG622 UPI_ForGN20Gen1@ RG252 UPI_ForGN20Gen1@
4 665_0402_1% 665_0402_1% 1000P_0402_50V7K 1000P_0402_50V7K 340_0402_1% 634_0402_1% 0.015U_0402_25V7K 0.015U_0402_25V7K 1000P_0402_50V7K 0_0402_5% 499_0402_1% 499_0402_1% 1000P_0402_50V7K 1000P_0402_50V7K 255_0402_1% 475_0402_1% 0.015U_0402_25V7K 0.015U_0402_25V7K 1000P_0402_50V7K 0_0402_5% 4
SD00000JJ00 SD00000JJ00 SE074102K80 SE074102K80 SD00000KT80 SD00000Z280 SE075153K80 SE075153K80 SE074102K80 SD028000080 SD034499080 SD034499080 SE074102K80 SE074102K80 SD034255080 SD034475080 SE075153K80 SE075153K80 SE074102K80 SD028000080
RG251 45492_ForGN20Gen1@
RG252 45492_ForGN20Gen1@
RG194 45492_ForGN20Gen1@
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
OVR-M
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: W ednesday, March 10, 2021 Sheet 37 of 121
A B C D E
5 4 3 2 1
C4 4 3 C3
1U_0201_6.3V6M EN OC 4.7U_0402_6.3V6M
EM5203AJ-20 SOT23 5P 2
D D
2
SA00008R900
<6> PCH_ENVDD
1
HOT PLUG DETECT
R4 R6 1 @ 2 0_0402_5% EDP_HPD_R
<6> EDP_HPD
100K_0402_5%
1
R8
2
100K_0402_5%
2
DISPLAY OFF eDP CONNECTOR
R5 1 @ 2 0_0402_5% DISPOFF#
<12,58> BKOFF#
2
R7
100K_0402_5%
1
C C
JEDP1
44
43 GND
GND
+19VB 0_0805_5% +LEDVDD
R9753 1 @ 2 0_0402_5% 42
41 GND
+LCDVDD_CONN GND
R9 1 @ 2 40
39 40
1 39
R5414 1 @ 2 10K_0402_5% @ 38
37 38
4.7U_0805_25V6-K C7 W=60mils 36 37
2 +LCDVDD_CONN 36
R5413 1 @ 2 10K_0402_5% 35
34 35
PANEL_OD#_R 33 34
R9751 1 @ 2 0_0402_5% INVPWM_R 32 33
<6> INVPWM 32
DISPOFF# 31
R5412 1 2 0_0402_5% PANEL_OD#_R EDP_HPD_R 30 31
<12> PANEL_OD# 30
29
DG21 EDP_TXN3_C 29
Over Drive enable eDP C17 1 2 0.1U_0201_10V6K 28
<6> EDP_TXN3 EDP_TXP3_C 28
1 2 C16 1 2 0.1U_0201_10V6K 27
pull high(1): OD on <6> EDP_TXP3
26 27
@ pull low(0): OD off C15 1 2 0.1U_0201_10V6K EDP_TXN2_C 25 26
RB751S40T1G_SOD523-2 <6> EDP_TXN2 EDP_TXP2_C 25
C14 1 2 0.1U_0201_10V6K 24
<6> EDP_TXP2 24
23
C13 1 2 0.1U_0201_10V6K EDP_TXN1_C 22 23
<6> EDP_TXN1 EDP_TXP1_C 22
C12 1 2 0.1U_0201_10V6K 21
<6> EDP_TXP1 21
20
C11 1 2 0.1U_0201_10V6K EDP_TXN0_C 19 20
<6> EDP_TXN0 EDP_TXP0_C 19
C10 1 2 0.1U_0201_10V6K 18
<6> EDP_TXP0 18
17
C9 1 2 0.1U_0201_10V6K EDP_AUXP_C 16 17
<6> EDP_AUXP EDP_AUXN_C 16
<6> EDP_AUXN C8 1 2 0.1U_0201_10V6K 15
B 14 15 B
13 14
12 13
11 12
<13> USB20_P6 11
10
<13> USB20_N6 10
Camera +3VS R359 1 @ 2 0_0402_5% +3V_CMOS 9
R360 1 @ 2 0_0402_5% +3V_DMIC 8 9
+1.8VS DMIC_CLK_R 8
0_0402_5% 1 EMI@ 2 R9730 7
<10> DMIC_CLK 7
6
<10> DMIC_DAT 6
DMIC 5
R9752 1 @ 2 0_0402_5% MIC_DET 4 5
R5408 1 @ 2 0_0402_5% 3 4
+3VL 3
R5409 1 @ 2 0_0402_5% 2
<58> LID_SW# 2
LID 1
1
1 ACES_50473-0400M-P01
C249
27P_0201_25V8 @EMI@ CONN@
2
DMIC_DAT RA35 1 @ 2 0_0402_5%
CODEC_DMIC_DAT_R <56>
DMIC_CLK LA1 1 @ 2
CODEC_DMIC_CLK_R <56>
HCB1005KF-221T15_2P
1
@ESD@ @ESD@
D6 @ESD@ D61 D62
3 6 DMIC_CLK PESD5V0H1BSF_SOD962-2-2 PESD5V0H1BSF_SOD962-2-2
I/O2 I/O4
2 5
GND VDD
2
A A
DMIC_DAT 1 4
I/O1 I/O3
AZC399-04S.R7G SOT23-6
SC300005Y00
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP / Camera / Touch
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
10U_0402_6.3V6M
10U_0402_6.3V6M
EN PGOOD
1
JUMP@
10K_0402_1%
1
CH29
CH30
10U_0402_6.3V6M
10U_0402_6.3V6M
1
1
11 J2104
FB_1.2V
CH26
CH27
CH28
RH20
1U_0201_6.3V6M
PAD 1 2
+1.2VALWP 1 2 +V1P2A_HDMI
2
2
2
JUMP_43X39
2
JUMP@
DH1 @ESD@ DH2 @ESD@ DH3 @ESD@
HDMI_CTRL_CLK 9 10 1 1 HDMI_CTRL_CLK HDMI_L_TX_N1 9 10 1 1 HDMI_L_TX_N1 HDMI_L_CLKN 9 10 1 1 HDMI_L_CLKN
0.8V
1
D +1.2VALWP HDMI_CTRL_DAT 8 9 2 2 HDMI_CTRL_DAT HDMI_L_TX_P1 8 9 2 2 HDMI_L_TX_P1 HDMI_L_CLKP 8 9 2 2 HDMI_L_CLKP D
20K_0402_1%
RH21
RH23 HDMI_HPD_CONN 7 7 4 4 HDMI_HPD_CONN HDMI_L_TX_N2 7 7 4 4 HDMI_L_TX_N2 HDMI_L_TX_N0 7 7 4 4 HDMI_L_TX_N0
0_0402_5% RH24
2
1 2 100K_0402_5% +5V_Display 6 6 5 5 +5V_Display HDMI_L_TX_P2 6 6 5 5 HDMI_L_TX_P2 HDMI_L_TX_P0 6 6 5 5 HDMI_L_TX_P0
<16,58,78,110> SUSP# 1 2 1.2V_PGOOD
3 3 3 3 3 3
.1U_0402_16V7K
EN :H>1.2V ; L<0.4V 8 8 8
CH33
1
L05ESDL5V0NA-4_SLP2510P8-10-9 L05ESDL5V0NA-4_SLP2510P8-10-9 L05ESDL5V0NA-4_SLP2510P8-10-9
SC300002C00 SC300002C00 SC300002C00
@
+V1P2A_HDMI +3VS_HDMI
close to pin 43 & 46 close to pin 30 close to pin 15&18 close to pin 6&11
HDMI_R_CLKN HDMI_L_CLKN
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0402_16V7K
CH37
CH39
CH36
CH43
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
0.01U_0402_16V7K
4.7U_0402_6.3V6M
+3VS +3VS_HDMI
CH35
CH42
CH41
CH40
CH38
CH34
CH11
CH12
CH13
CH14
CH15
CH16
close to pin 24
LH1
close to pin1
2
2 2 2 2 4 3
2 2 2 2 2 2 2 2 2 2 2 2 RH1 1 @ 2 0_0402_5% RH227
150_0402_5%
1 2 @
1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
1
HCM1012GH900BP_4P
SM070002R00
EMI@ +5VS +5V_Display
3
W=40mils
OUT
1 1
HDMI_R_TX_N0 RH221 1 EMI@ 2 2.2_0402_1% HDMI_L_TX_N0 IN CH5
1
+V1P2A_HDMI +3VS_HDMI CH6 2 0.1U_0201_10V6K
C
0.1U_0201_10V6K GND C
UH1 @ 2
6 1 2 AP2330W-7_SC59-3
30 VDD12 VDD33 24
VDD12 VDD33 SA00004ZA00
2
11
43 VDDA12 RH228
46 VDDRX12 23 HDMI_R_TX_P2 150_0402_5%
15 VDDRX12 OUT_D2p 22 HDMI_R_TX_N2 @
18 VDDTX12 OUT_D2n
VDDTX12
1
37 20 HDMI_R_TX_P1
POWERSWITCH OUT_D1p 19 HDMI_R_TX_N1
CH17 1 2 0.1U_0201_10V K X5R HDMI_TX_P2 38 OUT_D1n
<6> CPU_DP2_P0 HDMI_TX_N2 IN_D2p HDMI_R_TX_P0
CH18 1 2 0.1U_0201_10V K X5R 39 17
<6> CPU_DP2_N0 IN_D2n OUT_D0p HDMI_R_TX_N0 HDMI_R_TX_P0 HDMI_L_TX_P0
16 RH222 1 EMI@ 2 2.2_0402_1%
CH19 1 2 0.1U_0201_10V K X5R HDMI_TX_P1 41 OUT_D0n
<6> CPU_DP2_P1 HDMI_TX_N1 IN_D1p HDMI_R_CLKP
CH20 1 2 0.1U_0201_10V K X5R 42 14
<6> CPU_DP2_N1 IN_D1n OUT_CLKp HDMI_R_CLKN
13
CH21 1 2 0.1U_0201_10V K X5R HDMI_TX_P0 44 OUT_CLKn
<6> CPU_DP2_P2 HDMI_TX_N0 IN_D0p CPU_DP2_CTRL_DATA_R CPU_DP2_CTRL_DATA HDMI_R_TX_N1 HDMI_L_TX_N1
CH22 1 2 0.1U_0201_10V K X5R 45 33 RH2 1 2 0_0402_5% RH224 1 EMI@ 2 2.2_0402_1%
<6> CPU_DP2_N2 IN_D0n SDA_SRC/AUXN CPU_DP2_CTRL_DATA <6>
HDMI_CLKP SCL_SRC/AUXP
34 CPU_DP2_CTRL_CLK_R
HDMI_CTRL_DAT_R
RH3 1 2 0_0402_5% CPU_DP2_CTRL_CLK
HDMI_CTRL_DAT CPU_DP2_CTRL_CLK <6> From CPU
CH23 1 2 0.1U_0201_10V K X5R 47 8 RH4 1 2 0_0402_5%
<6> CPU_DP2_P3 IN_CLKp SDA_SNK
<6> CPU_DP2_N3
CH24 1 2 0.1U_0201_10V K X5R HDMI_CLKN 48
IN_CLKn SCL_SNK
7 HDMI_CTRL_CLK_R RH5 1 2 0_0402_5% HDMI_CTRL_CLK From HDMI CONN
2
DCIN_ENB 3 40 CPU_DP2_HPD_R RH231 1 2 1K_0402_5%
EQ 5 DCIN_ENB HPD_SRC 21 HDMI_HPD_CONN CPU_DP2_HPD <6> From CPU RH229
I2C_ADDR 31 EQ HPD_SNK From HDMI CONN 150_0402_5%
I2C_ADDR @
10
RSV1
1
25 32 HDMI_ID JHDMI1
NC HDMI_ID HDMI_HPD_CONN
close to U50 26
RSV2 HDMI_CEC
9
12
19
18 HP_DET
CEC_EN +5V_Display +5V
17
RH217 1 2 4.99K_0402_1% 36 29 @ PAD~D T2420 HDMI_R_TX_P1 RH223 1 EMI@ 2 2.2_0402_1% HDMI_L_TX_P1 HDMI_CTRL_DAT 16 DDC/CEC_GND
4 REXT CSCL 28 @ PAD~D T2421 +3VS +3VS +5V_Display HDMI_CTRL_CLK 15 SDA
RST# 35 PDB CSDA 14 SCL
PRE 27 RESETB 13 Reserved
2 PRE 49 HDMI_L_CLKN 12 CEC
TESTMODEB EPAD HDMI_R_TX_N2 RH225 1 EMI@ 2 2.2_0402_1% HDMI_L_TX_N2 11 CK-
4.7K_0402_5%
RH13
4.7K_0402_5%
RH14
2.2K_0402_5%
RH25
2.2K_0402_5%
RH26
CK_shield
1
1
HDMI_L_CLKP 10
PS8409AQFN48GTR2-A2_QFN48_6X6 HDMI_L_TX_N0 9 CK+
D0-
2
8
G HDMI_L_TX_P0 D0_shield
7
HDMI_L_TX_N1 6 D0+
D1-
2
2
B 5 B
CPU_DP2_CTRL_DATA 1 6 HDMI_CTRL_DAT RH230 HDMI_L_TX_P1 4 D1_shield 20
S
D2- GND
5
+3VS_HDMI @ 2 22
G
1
2N7002KDW_SOT363-6
RST# RH218 1 2 10K_0402_5% @ ACON_HMRB4-AK120C
CPU_DP2_CTRL_CLK 4 3 HDMI_CTRL_CLK
CONN@
S
+3VS_HDMI
www.teknisi-indonesia.com
EQ 4.7K_0402_5% 2 @ 1 RH15
Receiver equalization setting; Internal pull up ,3.3V I/O
L; Compensation for channel loss up to 13dB
4.7K_0402_5% 2 @ 1 RH16
H; Default, Compensation for channel loss up to 17dB
M; Compensation for channel loss up to 11dB
PRE 4.7K_0402_5% 2 @ 1 RH17 Output pre-emphasis setting; Internal pull up 3.3V I/O
L; Pre-emphasis=2.5dB
H;Default, No Pre-emphasis
A I2C_ADDR 4.7K_0402_5% A
2 @ 1 RH18
I2C Slave Address selection; Internal pull down 3.3V I/O
L; Default Slave address 0x10-0x2F
H;Alternative salve address 0x90-0x9F,0xD0-0xDF
+3VS_HDMI
HDMI_ID enable ; Internal pull down ,3.3 I/O.
HDMI_ID 4.7K_0402_5% 2 @ 1 RH19 L; Default HDMI ID enable
H;HDMI ID disable Security Classification Compal Secret Data Compal Electronics, Inc.
2020/0914 2021/09/04
HDMI
Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: Wednesday, March 10, 2021 Sheet 40 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
+3VALW +3VALW
USB3.1 Re-Driver
0.01U_0402_16V7K
1 1
CT1
+3VALW
0.1U_0201_10V6K
CT2
2 2
1 @ 2 UT3_TST
RT164 100K_0402_5% UT3
1
1 @ 2 UT3_I2C_EN VDD 13 +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW
RT165 100K_0402_5% VDD
UT3_B_EQ1 4
NC
1
UT3_B_DE0 3 15 UT3_A_EQ1_SDA
Type-C MUX UT3_B_EQ0
UT3_B_DE1
2 DE_A
EQ_A
NC
DE_B
16 UT3_A_DE0_SCL
UT3_A_EQ0 From CPU RT160 @ RT161 @ RT162 RT163 @ RT172 @ RT170 @ RT173 RT174 @
6 17 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%
NC EQ_B 18 UT3_A_DE1
0.1U_0201_10V6K NC
2
D USB3_CTX_C_DRX_P0 1 2 CT5 USB3_CTX_RD_DRX_P0 12 19 USB3_CTX_C_RD_DRX_P3 CT6 2 1 0.1U_0201_10V6K UT3_A_EQ1_SDA UT3_A_DE0_SCL UT3_A_EQ0 UT3_A_DE1 UT3_B_EQ1 UT3_B_DE0 UT3_B_EQ0 UT3_B_DE1 D
USB3_CTX_C_DRX_N0 USB3_CTX_RD_DRX_N0 TXB+ RXB+ USB3_CTX_C_RD_DRX_N3 USB3_CTX_DRX_P3 <13>
1 2 CT3 11 20 CT4 2 1 0.1U_0201_10V6K
TXB- RXB- USB3_CTX_DRX_N3 <13>
1
0.1U_0201_10V6K
0.1U_0201_10V6K RT166 @ RT167 @ RT168 @ RT169 @ RT176 @ RT177 @ RT178 @ RT179 @
USB3_CRX_C_DTX_P0 1 2 CT9 USB3_CRX_RD_DTX_P0 9 22 USB3_CRX_C_RD_DTX_P3 CT10 1 2 0.1U_0201_10V6K 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5% 4.7K_0402_5%
USB3_CRX_C_DTX_N0 USB3_CRX_RD_DTX_N0 RXA+ TXA+ USB3_CRX_C_RD_DTX_N3 USB3_CRX_DTX_P3 <13>
1 2 CT7 8 23 CT8 1 2 0.1U_0201_10V6K
RXA- TXA- USB3_CRX_DTX_N3 <13>
0.1U_0201_10V6K
2
5 UT3_R_PD# RT171 1 @ 2 4.7K_0402_5%
10 RXD_EN 7 UT3_R_REXT RT175 2 @ 1 4.99K_0402_1%
21 EN_A# NC 14 UT3_TST
25 EN_B# NC 24 UT3_I2C_EN
GPAD NC
PS8719ETQFN24GTR2-A0
Type-C MUX
+5VALW +5V_IN_5448 +5VALW +VBUS_5448
+5V_IN_5448 +5VALW
RT181 1 @ 2 0_0603_5% +VBUS_5448 +5VALW
1
CC1_5448 CC2_5448
10U_0603_25V6M
CT51
2
1
+5VALW +VCON_IN_5448 +VCON_IN_5448 +LDO_3V3_5448
.1U_0402_16V7K
CT52
UT4 RT186
RT180 1 @ 2 0_0603_5% 1 1 5 1 RT184 RT185 @ 10K_0402_5%
IN OUT
1
1
10U_0402_6.3V6M
@ 200K_0402_1% 10K_0402_5%
2
CT11 CT12 OCP_DET_5448 3
1 1 1 1 FLAG
2
VBUS_EN_5448 4 2
CT14
220P_0402_50V8J 220P_0402_50V8J
USB3_MRX_C_DTX_P1 RT241 1 2 220K_0402_5% 2 2 CT13 CT15 CT16 EN(#EN) GND VMON_5448 VBUS_EN_5448 OCP_DET_5448
USB3_MRX_C_DTX_N1 RT242 1 2 220K_0402_5% 0.1U_0201_10V K X5R 4.7U_0402_6.3V6M 0.1U_0201_10V K X5R G518A1TO1U TSOT-23 5P
2 2 2 2
1
USB3_MRX_C_DTX_N0 1 2
10U_0402_6.3V6M
RT243 220K_0402_5% SA0000AOU00
1
USB3_MRX_C_DTX_P0 RT244 1 2 220K_0402_5% @ 1
CT50
RT187 RT189 @
10K_0402_1% RT188 10K_0402_5%
13
20
19
UT5 10K_0402_5%
2
USB3_MRX_C_DTX_P1 CT45 1 2 0.33U_0201_6.3V6M USB3_MRX_DTX_P1 1 2
LDO_3V3
VCON_IN
5V_IN
C_RX2_1N/2P
2
USB3_MRX_C_DTX_N0 CT46 1 2 0.33U_0201_6.3V6M USB3_MRX_DTX_N0 2 14 CC2_5448 @
USB3_MRX_C_DTX_P0 CT47 1 2 0.33U_0201_6.3V6M USB3_MRX_DTX_P0 3 C_RX1_1P/2N CC2 15 VBUS_EN_5448
USB3_CRX_C_DTX_N0 4 C_RX1_1N/2P VBUS_EN 16 OCP_DET_5448
USB3_CRX_C_DTX_P0 5 SSRX_1P/2N OCP_DET 17 VMON_5448
USB3_CTX_C_DRX_N0 6 SSRX_1N/2P VMON 18 1 2 For C_VBUS For C_VBUS
C USB3_CTX_C_DRX_P0 SSTX_1P/2N REXT C
7 RT182 6.2K_0402_1% power switch enable pin power switch enable pin
USB3_MTX_C_DRX_N0 CT17 1 2 0.1U_0201_10V6K USB3_MTX_DRX_N0 8 SSTX_1N/2P
USB3_MTX_C_DRX_P0 CT18 1 2 0.1U_0201_10V6K USB3_MTX_DRX_P0 9 C_TX1_1P/2N 21 TYPEC_LIMIT_CTL1
USB3_MTX_C_DRX_P1 CT19 1 2 0.1U_0201_10V6K USB3_MTX_DRX_P1 10 C_TX1_1N/2P RP_SEL_M1 22 TYPEC_LIMIT_CTL0
USB3_MTX_C_DRX_N1 CT20 1 2 0.1U_0201_10V6K USB3_MTX_DRX_N1 11 C_TX2_1N/2P RP_SEL_M0 23
CC1_5448 12 C_TX2_1P/2N NC 24 USB3_MRX_DTX_N1 0.33U_0201_6.3V6M
1 2 CT48 USB3_MRX_C_DTX_N1
CC1 C_RX2_1P/2N 25
GND
1
RTS5448-GR QFN 24P TYPE-C RT183
10K_0402_1%
+LDO_3V3_5448 +LDO_3V3_5448
2
2
3 3 3 3
RT192 @ RT193 @
10K_0402_5% 10K_0402_5% 8 8
2
AZ176S-04F.R7G_SLP2510P8-10-9 AZ176S-04F.R7G_SLP2510P8-10-9
SC300006T00 SC300006T00
7
RPD_G1
B 6 B
RPD_G2
CC1_5448 12 4 CC1_5448_CONN
CC1 C_CC1
CC2_5448 11 TPD8S300 5 CC2_5448_CONN
CC2 C_CC2 +VBUS_5448 +VBUS_5448
15 1
SBU1 C_SBU1
14 2
SBU2 C_SBU2 JUSBC1
A1 B12
GND GND
20 USB3_MTX_C_DRX_P0 A2 B11 USB3_MRX_C_DTX_P0
D1 USB3_MTX_C_DRX_N0 A3 SSTXP1 SSRXP1 B10 USB3_MRX_C_DTX_N0
19 SSTXN1 SSRXN1
+LDO_3V3_5448 0.1U_0402_50V7K 2 1 CT25 3 D2 CT21 1 2 0.47U_0402_25V6K A4 B9 CT22 1 2 0.47U_0402_25V6K
VBIAS 17 VBUS VBUS
@ 10 D3 CC1_5448_CONN A5 B8
VPWR 16 CC1 SBU2
D4 USB20_P3_L A6 B7 USB20_N3_L
RT194 USB20_N3_L DP1 DN2 USB20_P3_L
A7 B6
2 1 9 18 DN1 DP2
1 FLT GND1 8 A8 B5 CC2_5448_CONN
CT26 GND2 13 SBU1 CC2
10K_0201_5% GND3 21 CT23 1 2 0.47U_0402_25V6K A9 B4 CT24 1 2 0.47U_0402_25V6K
0.1U_0201_10V K X5R
2 @ PAD VBUS VBUS
@ USB3_MRX_C_DTX_N1 A10 B3 USB3_MTX_C_DRX_N1
USB3_MRX_C_DTX_P1 A11 SSRXN2 SSTXN2 B2 USB3_MTX_C_DRX_P1
@ TPD8S300_QFN20_3X3
SSRXP2 SSTXP2 L7 EMI@
A12 B1 1 2 USB20_N3_L
GND GND <13> USB20_N3 1 2
1 4 4 3 USB20_P3_L
CC1_5448 CC1_5448_CONN GND GND <13> USB20_P3 4 3
RT195 2 @ 1 0_0402_5% ESD Diode structure should be located 2 5
3 GND GND 6 DLM0NSN900HY2D_4P
as close as possible to connector GND GND
SM070005U00
CC2_5448 RT196 2 @ 1 0_0402_5% CC2_5448_CONN
Type-C Connector PN
TMP DC231703291 2
GND VDD
5
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TYPE-C_Port0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: Wednesday, March 10, 2021 Sheet 42 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
TYPE-C_Port1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
RJ-45 CONN.
0.1U_0201_10V7K
HPC252012NF-2R2M PR4+
8111H_SW@ RJ45_RX1- 6
1
0.1U_0201_10V7K
PR2-
4.7U_0402_6.3V6K
1 1
CL1 CL2 CL3 RJ45_TX2- 5
+3VALW +3V_LAN 8111H_LDO@ PR3- LANGAN
D 2 RJ45_TX2+ 4 D
8111H_SW@
8111H_SW@
2 2 PR3+
W=40mils RL2 1 @ 2 0_0603_5%
W=40mils RJ45_RX1+ 3
PR2+
1U_0201_6.3V6M
2 RJ45_TX0- 2
+3V_LAN rising time (10%~90%) need >0.5mS and <100mS PR1- 10
CL4
RJ45_TX0+ 1 GND
PR1+ 9
1 LL1, CL16, and CL17 close to Pin24 GND
( Should be place within 200 mils )
SDAN_601051-008041
CONN@
+LAN_VDD
+3VS
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
0.1U_0201_10V7K
1U_0201_6.3V6M
1
1 1 1 1 1 LANGAN1
RL3
CL5 CL6 CL7 CL8 CL9 1K_0402_5%
2 2 2 2 2
2
ISOLATE#
1
RL4
www.teknisi-indonesia.com
15K_0201_5%
Pin3 Pin8 Pin22 Pin30 Pin22
2
+LAN_VDD
C C
For surge UL1
CL23, CL22 close to UL1 Pin17,18
+3V_LAN LAN_MDIP0 1 17 PCIE_CRX_C_DTX_P12 .1U_0402_16V7K 2 1 CL10
LAN_MDIN0 2 MDIP0 HSOP 18 PCIE_CRX_C_DTX_N12 2 1 CL11 PCIE_CRX_DTX_P12 <13>
.1U_0402_16V7K
MDIN0 HSON PCIE_CRX_DTX_N12 <13>
3 19 PCI_RST# <11,27,34,52,58,68>
LAN_MDIP1 4 AVDD10 PERSTB 20 ISOLATE#
4.7U_0402_6.3V6M
0.1U_0201_10V7K
4.7U_0402_6.3V6K
1 1 XTLI 3 1
CL17 RL11 2 @ 1 0_0402_5% 3 1
CL16 TXC SJ10000TO00 NC NC
2 2
8111H_SW@
2 2 Murata SJ10000UH00 CL18 4 2 CL19
LANGAN 33P_0402_50V8K 33P_0402_50V8K
1 1
B B
RL12 2 @ 1 0_0402_5%
LANGAN1
TL1 CL21
LAN_MDIP0 1 24 RJ45_TX0+ 1 2
TD1+ TX1+
LAN_MDIN0 2 23 RJ45_TX0- 1000P_0603_50V
TD1- TX1- EMI@
+V_DAC 3 22 RL14 1 EMI@ 2 75_0603_5%
CL20 TDCT1 TXCT1 LANGAN
1 2 +V_DAC 4 21 RL15 1 EMI@ 2 75_0603_5%
DL1 @ESD@ DL2 @ESD@ TDCT2 TXCT2
LAN_MDIP0 3 6 LAN_MDIP1 LAN_MDIP2 3 6 LAN_MDIP3 0.01U_0402_16V7K LAN_MDIP1 5 20 RJ45_RX1+
I/O2 I/O4 I/O2 I/O4 EMI@ TD2+ TX2+
LAN_MDIN1 6 19 RJ45_RX1-
TD2- TX2-
2 5 2 5 LAN_MDIP2 7 18 RJ45_TX2+
GND VDD GND VDD TD3+ TX3+
LAN_MDIN2 8 17 RJ45_TX2-
TD3- TX3-
LAN_MDIN1 1 4 LAN_MDIN0 LAN_MDIN3 1 4 LAN_MDIN2 +V_DAC 9 16 RL16 1 EMI@ 2 75_0603_5%
I/O1 I/O3 I/O1 I/O3 TDCT3 TXCT3
+V_DAC 10 15 RL17 1 EMI@ 2 75_0603_5%
AZC099-04SP.R7G AZC099-04SP.R7G TDCT4 TXCT4
SC300003S00 SC300003S00 LAN_MDIP3 11 14 RJ45_TX3+
TD4+ TX4+
LAN_MDIN3 12 13 RJ45_TX3-
TD4- TX4-
A A
TAIMA_IH-115-F
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN_RTL8111H/RTL8107E
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
C 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: Wednesday, March 10, 2021 Sheet 51 of 121
5 4 3 2 1
A B C D E
1
1 1 1 CW61
CW1 CW2 CW3 1U_0201_6.3V6M
10U_0402_6.3V6M 0.1U_0201_10V6K 0.01U_0402_16V7K CNVi@
2
CNVi@ CNVi@ CNVi@ UW1 CNVi@
2 2 2 5 1 +3VS_WLAN_R RW50 1 @ 2 0_0805_5%
IN OUT
2
Close to KEY E pin72,74 GND
RW41 1 @ 2 0_0402_5% CNVi_PW R_EN#_R 4 3
<58> CNVi_PW R_EN# EN(EN#) OC#
G524B2T11U_SOT23-5
+3VS_WLAN SA00007BW00
1
CW9
1U_0201_6.3V6M
2
CNVi@ I (Max) : 2.0 A(+3VS_WLAN)
1 1 1 RDS(Typ) : 70 mohm
CW4 CW5 CW6
10U_0402_6.3V6M 0.1U_0201_10V6K 0.01U_0402_16V7K
V drop : 0.14 V
CNVi@ CNVi@ CNVi@
2 2 2
Jefferson Peak:1360mA@peak current
Thunder_Peak_2:1100mA@peak current
Close to KEY E pin2,4
2 2
+3VS_WLAN
CNVi Module PIN Define
JW LAN1
GND 1 2 +3P3A
3 GND 3.3VAUX 4
<13> USB20_P10 USB_D+ USB_D+ / RSVD 3.3VAUX +3P3A
BT USB_D- 5 6 LED#1
<13> USB20_N10 USB_D- / RSVD LED1#
GND 7 8 PCM_CLK
GND PCM_CLK / RSVD
<14> CNV_CRX_DTX_N1 WGR_D1N 9
SIDO_CLK / WGR_D1N PCM_SYNC / LCP_RSTN
10 RF_RESET_B CNV_RF_RESET#_R RW4 1 CNVi@ 2 33_0402_5% CNV_RF_RESET# <10>
<14> CNV_CRX_DTX_P1 WGR_D1P 11 12 PCM_IN
13 SDIO_CMD / WGRD1P PCM_IN / RSVD 14 CLKREQ_CNV#_R RW6 1 CNVi@ 2 33_0402_5%
GND SDO_DAT0 / RSVD PCM_OUT / CLKREQ0 CLKREQ0 CLKREQ_CNV# <10>
<14> CNV_CRX_DTX_N0 WGR_D0N 15 16 LED2#
17 SDO_DAT1 / WGR_D0N LED2# 18
<14> CNV_CRX_DTX_P0 WGR_D0P SDO_DAT2 / WGR_D0P GND GND/LNA_EN
GND 19 20 UART WAKE#
21 SDO_DAT3 / RSVD UART_WAKE# / RSVD 22 CNV_BRI_CRX_R_DTX RW11 1 CNVi@ 2 49.9_0402_1%
<14> CLK_CNV_CRX_DTX_N WGR_CLKN SDIO_WAKE# / WGR_CLKN UART_RX / BRI_RSP BRI_RSP CNV_BRI_CRX_DTX <14>
WGR_CLKP 23 RW9 1 RMT@ 2 0_0402_5%
<14> CLK_CNV_CRX_DTX_P SDIO_RESET# / WGR_CLKP UART_2_CRXD_DTXD <12,58>
LOTES_APCI0128-P005A
CONN@
+3VS_WLAN
Note: The real behavior of BT_DISABLE are
BT_DISABLE=LOW, BT=OFF W LBT_OFF# RW58 2 @ 1 10K_0402_5%
BT_DISABLE=HIGH, BT=ON
W L_OFF# RW59 2 @ 1 10K_0402_5%
4 4
PCIE_W AKE# RC1147 1 2 10K_0201_5%
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NGFF WLAN / BT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
HDA_SYNC_R 1 2
ALC3287
@RF@ CA30 2.2P_0402_50V8C
HDA_BIT_CLK_R 1 2
Speaker
@RF@ CA31 2.2P_0402_50V8C
HDA_SDOUT_R @RF@ CA32 1 2 2.2P_0402_50V8C
HDA_SDIN0 @RF@ CA33 1 2 2.2P_0402_50V8C
UA1
34 PC_BEEP
6 PCBEEP
I2C_DATA 30 EXT_MIC_RING2 SPEAK 4 ohm : 40MIL
7 MIC2-L/RING2 SPEAK 8 ohm : 20MIL
I2C_CLK 31 EXT_MIC_SLEEVE JSPK1
HDA_SYNC_R 15 MIC2-R/SLEEVE SPK_R2+ RA5 1 @ 2 0_0603_5% SPK_R2+_CONN 1
<10> HDA_SYNC_R SYNC SPK_R1- SPK_R1-_CONN 1
36 RA6 1 @ 2 0_0603_5% 2
HDA_BIT_CLK_R 14 LINE2-L SPK_L2+ RA1 1 @ 2 0_0603_5% SPK_L2+_CONN 3 2
1 <10> HDA_BIT_CLK_R BCLK SPK_L1- SPK_L1-_CONN 3 1
35 RA3 1 @ 2 0_0603_5% 4
HDA_SDOUT_R 17 LINE2-R 4
<10> HDA_SDOUT_R SDATA-OUT SPK_L2+
42 5
13 SPK-OUT-L+ 6 GND1
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
RA2 DC_DET/EPAD 43 SPK_L1- GND2
SPK-OUT-L- 1 1 1 1
HDA_SDIN0 1 2 HDA_SDIN0_R 16
<10> HDA_SDIN0 Speaker JXT_WB201H-004G10M
CA2
CA3
CA4
CA5
33_0402_5% SDATA-IN 44 SPK_R1- CONN@
11 SPK-OUT-R-
NC 45 SPK_R2+ 2 2 2 2
10 SPK-OUT-R+
EMI@
EMI@
EMI@
EMI@
NC 27 HP_OUTL
HPOUT-L
Headphone
2
CA1 @EMI@ RA4 @EMI@ 9 26 HP_OUTR
2 1 HDA_BIT_CLK_R NC HPOUT-R DA2 DA5
12 TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
22P_0402_50V8J 33_0402_5% NC @ESD@ @ESD@
8
NC
1
1
Reserve Path CODEC_DMIC_DAT_R
SPDIF-OUT/GPIO2/DMIC-DATA34/DMIC-CLK-IN
4
<38> CODEC_DMIC_DAT_R GPIO0/DMIC-DATA12
CODEC_DMIC_CLK_R 5
<38> CODEC_DMIC_CLK_R GPIO1/DMIC-CLK
<58> EC_MUTE# RA8 1 @ 2 0_0402_5% PDB 2
PDB
PLUG_IN_R 48
JD1
47
JD2
CA7
VREF
1 2 2.2U_0402_6.3V6M LDO1 39
GNDA
CA8
2 LDO1-CAP 2
1 2 2.2U_0402_6.3V6M MIC2 32 33 1 2 10K_0402_5%
GNDA
CA9 RA9
MIC2-CAP 5VSTB
wide 40MIL
EXT_MIC_SLEEVE RA10 1 2 2.2K_0402_5% EXT_MIC_SLEEVE_R 29 AVDD1
40
SM010009U00
MIC2-VREFO-R 20 SM010009U00
EXT_MIC_RING2 EXT_MIC_RING2_R CPVDD/AVDD2 +1.8VDD_CODEC EXT_MIC_SLEEVE
RA11 1 2 2.2K_0402_5% 28 W=40mils EMI@ RA14 2 1 BLM15BD121SN1D_2P HGNDB
MIC2-VREFO-L 3 EXT_MIC_RING2 HGNDB <71>
+3VDD_CODEC W=40mils EMI@ RA13 2 1 BLM15BD121SN1D_2P HGNDA
DVDD +5VS HP_OUTL HPOUT_L HGNDA <71>
RA15 1 EMI@ 2 47_0402_5%
HP_OUTR HPOUT_R HPOUT_L <71>
18 +IOVDD_CODEC RA16 1 EMI@ 2 47_0402_5%
DVDD-IO HPOUT_R <71>
CA10 1 2 1U_0201_6.3V6M CPVEE 25 41 +5VS_PVDD RA12 1 2 0_0805_5%
GNDA
@
CPVEE PVDD1
CBN 24 46
CBN PVDD2
4.7U_0402_6.3V6M
0.1U_0201_10V6K
1 1
CA11 1 2 1U_0201_6.3V6M CBP 23 49 CA12 CA13
CBP Thermal_Pad
CA14 1 2 2.2U_0402_6.3V6M LDO2 21 37
GNDA
LDO2-CAP AVSS1 2 2
CA15 1 2 2.2U_0402_6.3V6M LDO3 19 22
LDO3-CAP AVSS2
Combo Jack
1
RT159
100K_0402_1% (Normal Open)
+5VS --> +5VDDA_CODEC +3VS --> +IOVDD_CODEC +3VS --> +3VDD_CODEC
2
PLUG_IN_R RA33 1 2 200K_0402_1% PLUG_IN
3
PLUG_IN <71> 3
+IOVDD_CODEC
+5VS +5VDDA_CODEC +3VS +3VS +3VDD_CODEC
RA20 1 @ 2 0_0603_5%
RA19 1 @ 2 0_0603_5% RA21 1 @ 2 0_0402_5%
RA31 1 @ 2 0_0402_5%
0.1U_0201_10V6K
0.1U_0201_10V6K
1
CA20 RA26 1 @ 2 0_0402_5%
0.1U_0201_10V6K
2.2U_0402_6.3V6M
1 1 CA22
2
CA21 CA28 2 RA28 1 @ 2 0_0402_5%
2 2
RA32 1 @ 2 0_0402_5%
1
+1.8VS +1.8VDD_CODEC Place near Pin34
RA30
RA25 1 @ 2 0_0402_5% 0_0402_5%
@
2
0.1U_0201_10V6K
2.2U_0402_6.3V6M
4 1 1 4
CA24 CA6
2 2
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
+3VL +3VL
L20
BLM15AX601SN1D_2P
1 2 R189 1 @ 2 0_0603_5% +3VL_VCC0 R9748 1 @ 2 0_0402_5%
+3VALW_EC +EC_VCCA
SM01000KL00
+3VALW_EC
1 1 1 1
Close U11.96
0.1U_0201_10V K X5R
C180
4.7U_0402_6.3V6K
U11.33
Close U11.22 or
0.1U_0201_10V K X5R
C181
Close U11.9
0.1U_0201_10V K X5R
C182
1000P_0402_50V7K
C183
1 1 1
C8717
C184 C185 @ +1.05V_VCCST
1U_0201_6.3V6M
1000P_0402_50V7K 2 2 2 2 R588
Close U11.67 @
2 2 2 +EC_VCCST 1 2
0.1U_0201_10V K X5R
SM01000KL00
C8718
Close U11.117
1 1 0_0402_5%
1 2 ECAGND C179
BLM15AX601SN1D_2P 100P_0201_50V8J @
L21 @
2 2
ECAGND +1.8VALW +5VALW
D R3984 1 @ 2 0_0402_5% +1.8VALW _ESPI D
1
C8720 +EC_VCCA +V18R R560 1 @ 2 0_0402_5% USB_EN# R554 1 2 10K_0402_5%
+3VALW_EC
1U_0201_6.3V6M 1
0.1U_0201_10V K X5R
C192
Close U11.124
2
VCIN1_BATT_TEMP 1 2
117
124
111
2 C189 100P_0201_50V8J
22
33
96
67
U11
9
VCIN1_AC_IN 1 2
C190 100P_0201_50V8J
VCC_IO2
VCC0
VCC_LPC
PECI_VTT
VCC
VCC
VCC
AVCC
LPC/eSPI & MISC
1 21
+1.8VS GA20/GPIO00 PWM0/GPIO0F USB_EN# <71>
2 23
KBRST#/GPIO01 PWM1/GPIO10 BEEP# <56>
3 PWM Output 26 EC_FAN_PWM1 <77>
4 SERIRQ FANPWM0/GPIO12 27
<9> ESPI_CS# LFRAME#/ESPI_CS# FANPWM1/GPIO13 EC_FAN_PWM2 <77>
1
5
<9> ESPI_IO3_R LAD3/ESPI_IO3
R9736 7
<9> ESPI_IO2_R LAD2/ESPI_IO2
1K_0201_5% 8 63
<9> ESPI_IO1_R LAD1/ESPI_IO1 AD0/GPIO38 VCIN1_BATT_TEMP <82,85>
10 64
<9> ESPI_IO0_R LAD0/ESPI_IO0 AD1/GPIO39 VCIN1_BATT_DROP <87>
65
D58 AD2/GPIO3A ADP_I <85>
2
12 AD Input 66
EC_PCI_RST# <9> ESPI_CLK_R PCICLK/ESPICLK AD3/GPIO3B CUST_TEMP3 <66>
1 2 13 75
<11,27,34,51,52,68> PCI_RST# PCIRST#/GPIO05 AD4/GPIO42 ADP_ID <82>
ECRST# 37 76
ECRST# AD5/GPIO43 CUST_TEMP2 <66>
1 20
RB751S40T1G_SOD523-2 C240 38 SCI#/GPIO0E
100P_0201_50V8J 14 CLKRUN#/GPIO1D +3VALW_EC
<9> ESPI_RST# GPIO07/ESPI_RST#
ESD@ 2 68
2 DA0/GPIO3C NOVO# <71>
DA Output 70 SW TRAP R9729 1 2 10K_0402_5%
C187 EC_DBG_KSI0 55 DA1/GPIO3D 71
KSI0/GPIO30 DA2/GPIO3E DGPU_PW R_EN <12,34>
0.1U_0201_10V K X5R 56 72 Pin 70 SWTRAP
1 KSI1/GPIO31 DA3/GPIO3F INT_AG_EC <64>
57 SWTRAP = Pull-Up: eSPI (ESPI MAFS)
58 KSI2/GPIO32 83 EC_SMB_CK3
EC_DBG_KSI4 KSI3/GPIO33 SCL2/GPIO4A EC_SMB_DA3 SWTRAP = Pull-Down: LPC (INTEL WIRE-OR FLASH SHARING) +3VL
59 84
EC_DBG_KSI5 60 KSI4/GPIO34 SDA2/GPIO4B 85
EC_DBG_KSI6 KSI5/GPIO35 SCL3/GPIO4C EC_SMB_CK4 <64>
61 86
EC_DBG_KSI7 KSI6/GPIO36 SDA3/GPIO4D EC_SMB_DA4 <64> To KB Controller IT8176
62 87
KSI7/GPIO37 PSCLK3/GPIO4E CNVi_PWR_EN# <52>
39 PS2 Interface 88 NOVO# R9732 1 2 100K_0402_5%
KSO0/GPIO20 PSDAT3/GPIO4F VR_PWRGD <97> LID_SW#
40 R9733 1 2 100K_0402_5%
41 KSO1/GPIO21 ON/OFF# R9734 1 2 100K_0402_5%
KSO2/GPIO22 1
EC_DBG_KSO3 42 97 C123
C KSO3/GPIO23 SHICS#/GPIO60 ENBKL <6> C
43 98 100P_0201_50V8J
KSO4/GPIO24 SHICLK/GPIO61 SYS_PWROK <11>
44 GPIO 99 ESD@
45 KSO5/GPIO25 Int. K/B SHIDO/GPIO62 109
ME_EN <10> 2
46 KSO6/GPIO26 Matrix VCIN0/GPIO78 VCIN0_PH1 <82>
C8719 @EMI@ @EMI@ 47 KSO7/GPIO27
ESPI_CLK_R KSO8/GPIO28 +3VALW
2 1 48 119
KSO9/GPIO29 MISO_SHR_ROM/GPIO5B BATT_FW# <85>
R3972 49 120
KSO10/GPIO2A MOSI_SHR_ROM/GPIO5C TP_INT# <12,63>
22P_0402_50V8J 33_0402_5% 50 126
51 KSO11/GPIO2B SPI ROM SPICLK_SHR_ROM/GPIO58 128
BATT_CHG_LED# <63>
KSO12/GPIO2C SPICS#_SHR_ROM/GPIO5A BATT_LOW _LED# <63>
52
1 @ 2 SYS_PWROK 53 KSO13/GPIO2D
R3874 10K_0402_5% 54 KSO14/GPIO2E 73 EC_MUTE# R555 1 @ 2 10K_0402_5%
KSO15/GPIO2F AD6/GPIO40 CUST_TEMP1 <66> VCCST_PW RGD
81 74
KSO16/GPIO48 AD7/GPIO41 VCCST_PW RGD <11>
82 89
KSO17/GPIO49 LOCK#/GPIO50 EC_MUTE# <56>
90 1
GPIO52 S5_PWR_EN# <64>
Reserved R3874,R3917 as Schematic checklist requirement, 91 C124
CAPSLED#/GPIO53 EN_5VALW <87>
R3917 resistor value is follow RVP. 77 92 100P_0201_50V8J
(This two resistor wait for verification) To Battery、 Charger IC
<82,85> EC_SMB_CK1
78 SCL0/GPIO44 GPIO WDT_LED/GPIO54 93
PW R_LED# <63>
ESD@
1
C238
<82,85> EC_SMB_DA1 SDA0/GPIO45 SCROLED#/GPIO55 LAN_PWR_EN <51> 2
79 95 100P_0201_50V8J SYSON
<28,66> EC_SMB_CK2 SCL1_BT/GPIO46 GPIO56 SYSON <89>
To GPU、 Thermal Sensor 80 121 ESD@
<28,66> EC_SMB_DA2 SDA1_BT/GPIO47 GPIO57/XCLK32K VR_ON <11,97> 2
15 127
C193
SMBUS
0.1U_0201_10V K X5R
<11> EC_CLEAR_CMOS# SELF_HEALING SCL4/GPIO08 GPIO59/DPWROK PCH_DPW ROK <11>
R9731 2 10_0402_5% 19
<12,56> HDA_SPKR
@
17 SDA4/GPIO0D Near U11 @ESD@
1
<28> GPU_PROCHOT# SCL5/GPIO0B
18 100
<28> THERM_ALERT#_EC_R SDA5/GPIO0C FANFB2/RSMRST# EC_RSMRST# <11>
101
FANFB3/GPIO64 3V/5VALW _PG <11,87,90>
102 GPIO65 R9705 1 2 47K_0402_5%
VCIN1/GPIO65 103 VCOUT1_PROCHOT# 2
GPIO VCOUT1/GPIO66 104
VCOUT0/GPIO67 VCOUT0_MAIN_PWR_ON <87>
6 105
GPIO04 GPIO68 TYPEC_LIMIT_CTL1_R BKOFF# <12,38> TYPEC_LIMIT_CTL1
16 106 R9750 2 1 0_0402_5%
<95> VCC_AUX_PWRGD OWM/GPIO0A GPIO69 TYPEC_LIMIT_CTL1 <42>
25 107
<11> AC_PRESENT PWM2/GPIO11 GPIO6A TP_DISABLE# <63>
28 108
<77> EC_FAN_SPEED1 FANFB0/GPIO14 GWG/GPIO6B EC_PCIE_WAKE# <51,52>
29
<77> EC_FAN_SPEED2 FANFB1/GPIO15
30
<52> EC_TX
31 TXD/GPIO16 GPIO 110
<52> EC_RX RXD/GPIO17 AC_IN/GPIO79 VCIN1_AC_IN <85>
32 112
<11> PCH_PWROK TYPEC_LIMIT_CTL0_R POWER_FAIL1/GPIO18 GPIO7A/ALW_PWR_EN EC_ON <87>
R9749 2 1 0_0402_5% 34 114
ON/OFF# <77>
<42> TYPEC_LIMIT_CTL0 PWM3/GPIO19 GPIO7B/ON/OFFBTN#
36 115
1
C125
<11,16> PM_SLP_S3# NUMLED#/GPIO1A GPIO GPIO7C/LID_IN 116
LID_SW# <38>
GPIO7D SUSP# <16,40,78,110>
100P_0201_50V8J
@ESD@ 118 PECI R559 1 2 33_0402_5%
2 PECI H_PECI <7>
B 122 B
<11> PBTN_OUT# XCLKI/GPIO5D
123
<11,89> PM_SLP_S4# GPIO5E
125
GPIO7E PM_SLP_S0# <11>
AGND
GND
GND
GND
GND
GND
R561 1 @ 2 0_0402_5%
<85> VCOUT1_PROCHOT#
11
24
35
94
113
69
1000P_0402_50V7K
1000P_0402_50V7K
1000P_0402_50V7K
2 2
2
1
teknisi-indonesia.com
R9725 1 2 2.2K_0402_5% EC_SMB_CK3
+3VS
ACES_50521-01241-P01
+3VALW CONN@
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
R395 1 2 10K_0402_5% PBTN_OUT# Issued Date Deciphered Date
EC_ENE KB9052QD
@
EC_PCIE_WAKE# THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
R563 1 2 10K_0402_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: Wednesday, March 10, 2021 Sheet 58 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
Touch Pad
+3VS +3VS_TP
RTP7 2 @ 1 0_0402_5%
A A
+3VS_TP +3VS_TP
+3VS_TP
1
RTP2 CTP1
4.7K_0402_5% 0.1U_0201_10V6K
@
2
JTP1
8 10
7 8 GND 9
<12> I2C_0_SCL 7 GND
6
<12> I2C_0_SDA 5 6
4 5
3 4
RTP8 1 @ 2 0_0402_5% TP_INT#_R 2 3
<12,58> TP_INT# 2
<58> TP_DISABLE# RTP3 1 @ 2 0_0402_5% TP_DISABLE#_R 1
1
HEFEN_AFC79-S08FKA-R1
SP01002YA00
2200P_0402_25V7K
2200P_0402_25V7K
CONN@
B B
330P_0201_50V7K
CTP2
330P_0201_50V7K
CTP3
1 1
1
1
CTP5
CTP7
2 2
2
2
ESD@
ESD@
DTP1 @ESD@
L03ESDL5V0CC3-2_SOT23-3
SCA00002900
1
C C
LED1
@ESD@ 1 +5VL
D60 RS168 1 2 180_0402_1% BATT_LOW_LED#_R2 3
<58> BATT_LOW_LED#
AZ5125-02S.R7G_SOT23-3-X
SCA00001A00
Amber
HT-210UD5-BP5_AMBER-WHITE
2
SC50000FV10
@ESD@
1
D59
AZ5125-02S.R7G_SOT23-3-X
SCA00001A00
1
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB / TP / LED
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
+3VALW
QBL14
+5VS
W=20mils 3 1
W=20mils JRGB1
D
20 22
19 20 GND2 21
PJ2301_SOT23-3 18 19 GND1
1
G
18
2
CBL18 17
1U_0201_6.3V6M 16 17
S5_PWR_EN# 1 2 15 16
<58> S5_PWR_EN# 2 15
14
D RBL78 13 14 D
150K_0402_5% 1 13
CBL39 USB20_N8_R1 RBL91 1 @ 2 0_0402_5% SMCLK1_AG_BLC 12
0.1U_0201_10V6K USB20_P8_R1 RBL92 1 @ 2 0_0402_5% SMDAT1_AG_BLC 11 12
INT_AG_BLC 10 11
2 9 10
8 9
7 8
RBL93 1 2 0_0402_5% USB20_N7_R 6 7
<13> USB20_N7 RBL94 1 2 0_0402_5% USB20_P7_R 5 6
<13> USB20_P7 4 5
3 4
2 3
+3VALW_AG USB20_N7_R1 RBL95 1 @ 2 0_0402_5% 1 2
USB20_P7_R1 +3VALW_AG 1
RBL96 1 @ 2 0_0402_5%
HEFEN_AFC48-S20FKA-HF
+3VALW_AG CONN@
+3VALW_AG
1
RBL39
10K_0402_5% @ DBL21
CBL31
CBL32
RB751S40T1G_SOD523-2
+AVCC33_AG +3VALW_AG
0.1U_0201_10V6K
1 1
2
AG_WRST#
.1U_0402_16V7K
1
1
CBL29 CBL30
1 2 0_0603_5%
0.1U_0201_10V6K
0.1U_0201_10V6K
1 @ RBL25 @
2 2
0.1U_0201_10V6K
CBL35
2
1U_0201_6.3V6M 2
1 1
CBL33
2 CBL34
1000P_0402_50V7K +3VALW_AG
2 2
SMCLK1_AG_BLC
near pin8 near pin18 RBL81 1 2 2.2K_0402_5%
17
18
32
7
8
Keyboard
UBL3
SMDAT1_AG_BLC RBL82 1 2 2.2K_0402_5%
VCOREB2
VSTBY33
VSTBY33
VCOREB
AVCC33
USB20_N7_R1 RBL89 1 @ 2 0_0402_5%
USB20_P7_R1 RBL90 1 @ 2 0_0402_5%
AG_WRST# 48
WRST#
1 SMCLK0_AG_EC_R RBL40 1 @ 2 0_0402_5% +3VS +3VS_KB
C SMCLK0/PWM0/GPA0 SMDAT0_AG_EC_R EC_SMB_CK4 <58> C
0.1U_0201_10V6K
KSI5 KSO10
43 KSI5/ADC21/GPD5 PW M4/GPA4 5 4
KSI6
44 KSI6/ADC22/GPD6 IT8176FN 1 KSO11
6 5
CBL42
KSI7 KSO14
TP@ KSI7/ADC23/GPD7 ESD@ KSO13 7 6
TP@
T2418
T2419
KSO0 9
QFN-48 45 KB_NUM_LED# 2
KSO12
KSO3
8
9
7
8
KSO1 10 KSO0/PD0/GPE0 TXD/GPA7 46 KB_FN_LED# KSO6 10 9
KSO2 11 KSO1/PD1/GPE1 RXD/GPA6 KSO8 11 10
KSO3 12 KSO2/PD2/GPE2 KSO7 12 11
KSO4 13 KSO3/PD3/GPE3 KSO4 13 12
KSO5 14 KSO4/PD4/GPE4 KSO2 14 13
KSO6 15 KSO5/PD5/GPE5 KSI0 15 14
KSO7 16 KSO6/PD6/GPE6 KSO1 16 15
KSO8 22 KSO7/PD7/GPE7 34 KSO5 17 16
KSO9 23 KSO8/ACK#/GPF0 ADC0/GPC0 35 INT_AG_EC KSI3 18 17
KSO9/BUSY/GPF1 ADC1/GPC1 INT_AG_BLC INT_AG_EC <58> 18
KSO10 24 36 KSI2 19
KSO11 25 KSO10/PE/GPF2 ADC2/GPC2 KSO0 20 19
KSO12 26 KSO11/ERR#/GPF3 KSI5 21 20
KSO13 27 KSO12/SLCT/GPF4 KSI4 22 21
KSO14 28 KSO13/GPF5 KSO9 23 22
KSO15 29 KSO14/GPF6 KSI6 24 23
KSO15/GPF7 24
1
KSO16 30 KSI7 25
KSO17 31 KSO16/SMCLK2/GPG0 49 RBL44 RBL45 KSI1 26 25
KSO17/SMDAT2/GPG1 GND KSO16 27 26
AVSS
10K_0402_5% 10K_0402_5%
27
VSS
VSS
KSO17 28
KB_NUM_LED# R37 1 2 100_0402_5% 29 28
29
2
IT8176FN-56A-BX_QFN48_6X6 30
30
6
21
33
31
KB_FN_LED# R38 1 2 100_0402_5% 32 31
33 32
34 33
B B
34
35
GND 36
GND
ACES_51510-03401-001
CONN@
JKBL1
1
1
RBL68 2 1
10K_0402_5% 3 2
3 1 4 3
S
4
2
0.1U_0201_10V K X5R
QBL15
PJ2301_SOT23-3 1 1
G
2
5
10U_0402_6.3V6M
CBL40
CBL25
@ SB00000T900
RBL79 1 2 0_0402_5% 1 2 @ 6 GND
RBL69 GND
2 2
0.01U_0402_16V7K
30K_0402_5%
1
CBL41
CVILU_CF5004FD0RD-10-NH
D
1
LTCX007VP00
KB_BL_PW M Q203
2 CONN@
A G 2N7002KW _SOT323-3 2 A
1
SB000009Q80
RBL80 S
3
100K_0402_5%
2
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Size Document Number
Custom Rev1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: Wednesday, March 10, 2021 Sheet 64 of 121
5 4 3 2
Date: 1
Sheet
5 4 3 2 1
D D
C
www.teknisi-indonesia.com C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D
THERMAL SENSOR D
+3VS_THM
+3VS +3VS_THM
RTH1 1 @ 2 0_0402_5% 1
CTH1
0.1U_0201_10V6K
2
QTH1 LMBT3904WT1G_SC70-3 1
1
QTH1 C CTH2 1 10 EC_SMB_CK2
VCC SCL EC_SMB_CK2 <28,58>
Place near +NVVDD B
2 2200P_0402_25V7K
@
CTH3
2200P_0402_25V7K REMOTE1+ 2
DP1 SDA
9 EC_SMB_DA2
EC_SMB_DA2 <28,58>
@
RTH2
10K_0402_5%
2
E 2
(Bottom Side)
3
3 8
DN1 ALERT#
2
REMOTE1- REMOTE1-
C 4 7 THM_ALERT# C
REMOTE2+ REMOTE2+ DP2 THERM#
5 6
LMBT3904WT1G_SC70-3 DN2 GND
1
QTH2 C 1 REMOTE2-
1
2 CTH4 F75303M_MSOP10
QTH2 E
B 2200P_0402_25V7K
@
CTH5
2200P_0402_25V7K SA000046C00
3
2
2
Place near +VCCIN REMOTE2- Address 1001_101xb
(Bottom Side) UTH1
REMOTE1,2 (+/-) :
Trace width/space:10/10 mil
Place near Left Fin
Trace length:<8" (Top Side)
1
RTS1 RTS2 RTS3
B 16.5K_0402_1% 16.5K_0402_1% 16.5K_0402_1% B
2
2
<58> CUST_TEMP1 <58> CUST_TEMP2 <58> CUST_TEMP3
1
1
RTS4 RTS5 RTS6
2
RTS4 RTS5 RTS6
Place near Right Fin Place near JDIMM2 Place near JSSD2
(Top Side) (Top Side) (Top Side)
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Finger Printer/ Thermal
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
HDD
+5VS
100mils
UHD2
10 RHD3 1 2 0_0402_5%
10U_0402_6.3V6M
0.1U_0201_10V K X5R
@
VDD 20
CHD20
VDD 1 1 1
CHD17
10P_0201_50V8J
CHD19
CHD9 1 2 0.01U_0402_16V7KHDD@ SATA_CTX_C_DRX_P0 1 15 SATA_CTX_R_DRX_P0 HDD@ CHD101 2 0.01U_0402_16V7K SATA_CTX_CONN_DRX_P0
<13> SATA_CTX_DRX_P0 A_INP A_OUTP
CHD111 2 0.01U_0402_16V7KHDD@ SATA_CTX_C_DRX_N0 2 14 SATA_CTX_R_DRX_N0 HDD@ CHD121 2 0.01U_0402_16V7K SATA_CTX_CONN_DRX_N0 HDD@
<13> SATA_CTX_DRX_N0 A_INN A_OUTN 2 2 RF@ 2
CHD131 2 0.01U_0402_16V7KHDD@ SATA_CRX_C_DTX_P0 5 11 SATA_CRX_R_DTX_P0 HDD@ CHD141 2 0.01U_0402_16V7K SATA_CRX_CONN_DTX_P0 @
<13> SATA_CRX_DTX_P0 B_OUTP B_INP
CHD151 2 0.01U_0402_16V7KHDD@ SATA_CRX_C_DTX_N0 4 12 SATA_CRX_R_DTX_N0 HDD@ CHD161 2 0.01U_0402_16V7K SATA_CRX_CONN_DTX_N0
<13> SATA_CRX_DTX_N0 B_OUTN B_INN
PS8527C_A_EQ1 17 9 PS8527C_A_DE
PS8527C_A_EQ2 18 A_EQ1 A_DE
A_EQ2 8 PS8527C_B_DE
PS8527C_B_EQ1 19 B_DE
PS8527C_B_EQ2 13 B_EQ1 16 PS8527C_DEW +5VS_HDD
B_EQ2 DEW JHDD1
PS8527C_EN 7 21 1
RHD4 1 HDD@ 2 4.99K_0402_1% 6 EN EPAD 3 SATA_CTX_CONN_DRX_P0 2 1
REXT GND SATA_CTX_CONN_DRX_N0 3 2
C
PS8527CTQFN20GTR2A2_TQFN20_4X4 4 3 C
SATA_CRX_CONN_DTX_N0 5 4
HDD@ 5
SATA_CRX_CONN_DTX_P0 6
7 6
SATA_DEVSLP 8 7
9 8
10 9
11 10 13
12 11 G13 14
12 G14
+3VS +3VS SDAN_606041-012112
CONN@
1
RHD6 RHD13
@ 4.7K_0402_5% @ 4.7K_0402_5%
2
PS8527C_EN PS8527C_DEW
1
1
CHD21
@ 0.1U_0201_10V K X5R RHD22
@ 4.7K_0402_5%
2
2
B B
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
R97281 @ 2 0_0805_5%
JSSD2
1 2
0.01U_0402_16V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
3 GND1 3.3VAUX1 4 1 1 1
5 GND2 3.3VAUX2 6
C782
C787
C788
7 PERn3 N/C1 8
D PERp3 N/C2 D
9 10 2 2 2
11 GND3 DAS/DSS# 12
13 PETn3 3.3VAUX3 14
15 PETp3 3.3VAUX4 16
17 GND4 3.3VAUX5 18
19 PERn2 3.3VAUX6 20
21 PERp2 N/C3 22
23 GND5 N/C4 24
25 PETn2 N/C5 26
27 PETp2 N/C6 28
29 GND6 N/C7 30
<13> PCIE_CRX_DTX_N10 31 PERn1 N/C8 32
<13> PCIE_CRX_DTX_P10 33 PERp1 N/C9 34
C785 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_N10 35 GND7 N/C10 36
<13> PCIE_CTX_DRX_N10 PCIE_CTX_C_DRX_P10 PETn1 N/C11
C789 1 2 0.22U_0201_6.3V6M 37 38
<13> PCIE_CTX_DRX_P10 39 PETp1 DEVSLP 40
41 GND8 N/C12 42
<13> PCIE_CRX_DTX_N9 43 PERn0/SATA-B+ N/C13 44
<13> PCIE_CRX_DTX_P9 45 PERp0/SATA-B- N/C14 46
C786 1 2 0.22U_0201_6.3V6M PCIE_CTX_C_DRX_N9 47 GND9 N/C15 48
<13> PCIE_CTX_DRX_N9 PCIE_CTX_C_DRX_P9 49 PETn0/SATA-A- N/C16 50 PCI_RST#
C783 1 2 0.22U_0201_6.3V6M PCI_RST# <11,27,34,51,52,58>
<13> PCIE_CTX_DRX_P9 51 PETp0/SATA-A+ PERST# 52
53 GND10 CLKREQ# 54 CLKREQ_PCIE#5_SSD1 <11>
<11> CLK_PCIE_N5 55 REFCLKN PEWake# 56
<11> CLK_PCIE_P5 REFCLKP N/C17
57 58
GND11 N/C18
67 68
69 N/C19 SUSCLK(32kHz) (O)(0/3.3V) 70
71 PEDET (OC-PCIe/GND-SATA) 3.3VAUX7 72
73 GND12 3.3VAUX8 74
75 GND13 3.3VAUX9
GND14
C C
79 78
77 NPTH2 NPTH1 76
GND16 GND15
LOTES_APCI0262-P001A
CONN@
R97271 @ 2 0_0805_5%
JSSD1
1 2
0.01U_0402_16V7K
0.1U_0201_10V6K
10U_0402_6.3V6M
3 GND1 3.3VAUX1 4 1 1 1
5 GND2 3.3VAUX2 6
C18 SSD2@
C19 SSD2@
C20 SSD2@
<13> PCIE4_CRX_DTX_N3 PERn3 N/C1
7 8
<13> PCIE4_CRX_DTX_P3 PERp3 N/C2
9 10 2 2 2
C161 1 2 0.22U_0201_6.3V6M PCIE4_CTX_C_DRX_N3 11 GND3 DAS/DSS# 12
<13> PCIE4_CTX_DRX_N3 PETn3 3.3VAUX3
C162 1 2 0.22U_0201_6.3V6M PCIE4_CTX_C_DRX_P3 13 14
<13> PCIE4_CTX_DRX_P3 PETp3 3.3VAUX4
SSD2@ 15 16
17 GND4 3.3VAUX5 18
<13> PCIE4_CRX_DTX_N2 SSD2@
B 19 PERn2 3.3VAUX6 20 B
<13> PCIE4_CRX_DTX_P2 PERp2 N/C3
21 22
C159 1 2 0.22U_0201_6.3V6M PCIE4_CTX_C_DRX_N2 23 GND5 N/C4 24
<13> PCIE4_CTX_DRX_N2 PCIE4_CTX_C_DRX_P2 PETn2 N/C5
C160 1 2 0.22U_0201_6.3V6M 25 26
<13> PCIE4_CTX_DRX_P2 PETp2 N/C6
SSD2@ 27 28
29 GND6 N/C7 30
<13> PCIE4_CRX_DTX_N1 SSD2@
31 PERn1 N/C8 32
<13> PCIE4_CRX_DTX_P1 PERp1 N/C9
33 34
C157 1 2 0.22U_0201_6.3V6M PCIE4_CTX_C_DRX_N1 35 GND7 N/C10 36
<13> PCIE4_CTX_DRX_N1 PCIE4_CTX_C_DRX_P1 PETn1 N/C11
C158 1 2 0.22U_0201_6.3V6M 37 38
<13> PCIE4_CTX_DRX_P1 PETp1 DEVSLP
SSD2@ 39 40
41 GND8 N/C12 42
<13> PCIE4_CRX_DTX_N0 SSD2@
43 PERn0/SATA-B+ N/C13 44
<13> PCIE4_CRX_DTX_P0 PERp0/SATA-B- N/C14
45 46
C155 1 2 0.22U_0201_6.3V6M PCIE4_CTX_C_DRX_N0 47 GND9 N/C15 48
<13> PCIE4_CTX_DRX_N0 PCIE4_CTX_C_DRX_P0 PETn0/SATA-A- N/C16 PCI_RST#
C156 1 2 0.22U_0201_6.3V6M 49 50
<13> PCIE4_CTX_DRX_P0 PETp0/SATA-A+ PERST#
SSD2@ 51 52
GND10 CLKREQ# CLKREQ_PCIE#0_SSD2 <11>
SSD2@ 53 54
<11> CLK_PCIE_N0 REFCLKN PEWake#
55 56
<11> CLK_PCIE_P0 REFCLKP N/C17
57 58
GND11 N/C18
67 68
69 N/C19 SUSCLK(32kHz) (O)(0/3.3V) 70
71 PEDET (OC-PCIe/GND-SATA) 3.3VAUX7 72
73 GND12 3.3VAUX8 74
75 GND13 3.3VAUX9
GND14
79 78
77 NPTH2 NPTH1 76
GND16 GND15
A LOTES_APCI0262-P001A A
CONN@
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
NGFF SSD
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
A A
IO connector
+5VALW +5VALW_USB
U9
1
5 OUT
IN 2
4 GND
<58> USB_EN# EN 3 USB_OC0#_R RUS13 2 @ 1 0_0402_5%
OCB USB_OC0# <13>
G517G2TO1U TSOT-23 5P
1 SA0000A2H00
CUS4
0.1U_0201_10V6K
2
3A/Active Low
B B
JIO1
1
<56> HGNDB 1
2
3 2
<56> HPOUT_L 3
4
5 4
<56> HPOUT_R 5
6
<56> HGNDA 6
7
8 7
<56> PLUG_IN 8
9
10 9
<13> USB3_CTX_DRX_P1 10
11
<13> USB3_CTX_DRX_N1 11
12
13 12
<13> USB3_CRX_DTX_P1 13
14
<13> USB3_CRX_DTX_N1 14
15
R9737 2 @ 1 0_0402_5% USB20_P1_R 16 15
<13> USB20_P1 16
R9738 2 @ 1 0_0402_5% USB20_N1_R 17
<13> USB20_N1 17
18
R9739 2 @ 1 0_0402_5% USB20_P2_R 19 18
<13> USB20_P2 19
<13> USB20_N2 R9740 2 @ 1 0_0402_5% USB20_N2_R 20
21 20
22 21
<13> USB3_CRX_DTX_P2 22
23
<13> USB3_CRX_DTX_N2 23
C 24 C
25 24
<13> USB3_CTX_DRX_P2 25
26
<13> USB3_CTX_DRX_N2 26
27
28 27
<58> STATE_LED# 28
29
<58> NOVO# 29
30
31 30
+3VALW 31
32
+5VALW_USB 33 32
34 33
+5VL 34
35
36 35 41
37 36 GND 42
38 37 GND 43
39 38 GND 44
40 39 GND 45
40 GND
CVILU_CVS3402M1RM-NH
CONN@
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB3.0 AOU / IO Conn.
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: Wednesday, March 10, 2021 Sheet 71 of 121
1 2 3 4 5 6 7 8
5 4 3 2 1
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
1 1
1
Power Button H_2P8 H_3P6 H_3P2 H_2P8 H_3P6 H_3P3 H_3P3 H_3P3 H_3P3 H_3P3 H_3P3
H8 H12
HOLEA HOLEA
SW1
EVQPLHA15_4P
1 3
ON/OFF# <58>
1
2 4
3
2
H_3P3 H_4P4X2P8N
5
6
ESD@
D57
AZ5125-02S.R7G_SOT23-3-X
SCA00001A00 H15 H16 H19 H20 H21 H22
HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA
1
1
H_2P8 H_2P8 H_4P4X2P8N H_2P8N H_3P4 H_3P2
2
ON/OFF# SHORT PAD CLIP1
HOLEA_35A2M
CLIP2
HOLEA_35A2M
FD1 FD2
2
1
CLIP
@
1
JP1 2 1 ON/OFF#
@ @
TOP side
SHORT PADS FD3 FD4
EMIST_SUL-35A2M_1P-T EMIST_SUL-35A2M_1P-T
1
CLIP3 CLIP7 CLIP4 CLIP5
@ HOLEA_15A3M HOLEA_15A3M HOLEA_15A3M HOLEA_15A3M
JP2 2 1 ON/OFF#
BOT side
SHORT PADS
1
@ @ @ @
FAN
3 3
JFAN1 JFAN2
1 5 1 5
+5VS EC_FAN_PWM1 2 1 GND 6 +5VS EC_FAN_PWM2 2 1 GND 6
<58> EC_FAN_PWM1 EC_FAN_SPEED1 2 GND <58> EC_FAN_PWM2 EC_FAN_SPEED2 2 GND
3 3
<58> EC_FAN_SPEED1 +5VS_FAN1 3 <58> EC_FAN_SPEED2 +5VS_FAN2 3
RF4 1 @ 2 0_0603_5% 4 RF2 1 @ 2 0_0603_5% 4
4 4
CVILU_CI4404M1HRC-NH CVILU_CI4404M1HRC-NH
2 SP02000VH10 SP02000VH10
CONN@ 2 CONN@
CF14
10U_0402_6.3V6M CF1
1
10U_0402_6.3V6M
1
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCREW / FAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
DC to DC
1 1
+5VALW +5VS
J1
2 1
+5VL 2 1
0.1U_0201_10V6K
JUMP_43X79
+5VALW to +5VS
JUMP@
0.1U_0201_10V6K
1 1
C71
C74
U10 @
2 15 2
GPAD
7 8 +5VALW_5VS
6 VIN2 VOUT2 9
VIN2 VOUT2
R9746 1 2 0_0402_5% +5VS_EN 5 10 C75 1 2 2200P_0402_25V7K
<16,40,58,110> SUSP# ON2 CT2
4 11
VBIAS GND
R9747 1 2 0_0402_5% +3VS_EN 3 12 C76 1 2 1000P_0402_50V7K +3VS
+3VALW ON1 CT1 J2
2 13 +3VALW_3VS 2 1
1 VIN1 VOUT1 14 2 1
VIN1 VOUT1
0.1U_0201_10V6K
2 JUMP_43X79 1 2
SA0000BEL00
0.1U_0201_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
JUMP@
C80
1 1 1
G2898KD1U_TDFN14_2X3
C77
C8721
C8722
+3VALW to +3VS
@
2
2 2 @ 2 @
+1.8VALW
C389
1 +1.8VALW TO +1.8VS
1U_0201_6.3V6M U13 +1.8VS
1
2 2 VIN1
3 +5VALW VIN2 J4 3
C391 @ 7 6 +1.8VS_J4 1 2
0.1U_0201_10V6K VIN thermal VOUT 1 2
1 2 3 JUMP_43X39 1
VBIAS JUMP@ C392
SUSP# 4 5 0.1U_0201_10V6K
ON GND
2
1
@ C394 EM5201V_DFN8_3X3
1U_0201_6.3V6M SA00008R600
2
RDS(Typ) : 3.5 mohm
V drop : 0.0004V
4 4
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC to DC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
B B
A A
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Reserve
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
LA-L161P 1.A
D D
C C
PWR Reserve
B B
A A
14.3K_0402_1%
7
1
8 PC201 EMI@ EMI@ PL203
8
1
9 1000P_0402_50V7K 5A_Z80_0805_2P PC202 EMI@
PR205
D 9 10 0.01U_0402_25V7K D
100_0402_1%
100_0402_1%
10
2
11
11 12
12
2
PR201
PR202
2
2
13 <58> VCIN0_PH1
GND1 14
GND2 15
GND3
1
16
GND4 EC_SMB_CK1 <58,85>
PH201
EC_SMB_DA1 <58,85> 100K_0402_1%_B25/50 4250K
OCTEK_WTB-12GCBWAB-U 1 2
+3VL
2
PR203
200K_0402_1%
1 2
VCIN1_BATT_TEMP <58,85>
PR204
10K_0402_5%
ECAGND
C C
1 2
SP040006F00
1U_0402_25V6K
100P_0402_50V8J
EMI@ PL205
0.01U_0402_50V7K
POWER 1 5A_Z80_0805_2P
GND 5
1000P_0402_50V7K
100P_0402_50V8J
GND 1 2
1
6
PC211
PC209
EMI@ PC203
EMI@ PC204
GND 7
GND
1
EMI@ PL206
EMI@ PC205
EMI@ PC206
2
DRAPH_PJSS0056-PB21H 5A_Z80_0805_2P
2
@EMI@
EMI@
@ PR206 0_0402_5%
1 2
1 2 1
PC207
PC208
2 1
1 2 3 2
+3VL GND
2
PR211 4
750_0402_1% GND
ACES_50271-0020N-001
GC02001DR00
RTC Battery BATT CR2032 3V 210MAH MB 5 W/C
30MM
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- BATTERY CONN/OTP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Y750
Date: Wednesday, March 10, 2021 Sheet 82 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- DCIN / Vin Detector
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. SKL
Date: Wednesday, March 10, 2021 Sheet 83 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
PWR Reserve
B B
A A
PQ309 PQ310
AON6426_DFN5X6-8-5 AON7506_DFN3X3-8-5
1 1
2 2
5 3 3 5 max Power loss 0.22W for 90W;0.12W for 65W system
CSR rating: 1W
CMSRC-1
VACP-VACN spec < 80.64mV
4
D
ACDRV-2
PR314 2
ACDRV-1
1 2 G
S PQ307 +19VB PQ302 +12.6V_BA+
3
1M_0402_1% PR315 2N7002KW_SOT323-3
1 2 P3 AON7506_DFN3X3-8-5
3M_0402_5% 1
D PQ301 PQ303 2 D
AON6426_DFN5X6-8-5 AON7506_DFN3X3-8-5 PR2507 5 3
1 1 0.005_1206_1%
2 2
+19V_VIN 5 3 3 5 1 4
4
PC9205
CMSRC-1
2 3
1 2
4
1000P_0402_50V7K
2200P_0402_50V7K
0.047U_0603_25V7M
0.1U_0402_25V6
0.022U_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
1
PC9207
@EMI@PC9208
PC9209
PC9210
PC9211
1
1
ACDRV-2
PC9206
4.02K_0402_1%
1
1
PR2508
4.02K_0402_1%
2
EMI@
PC310 PC9212 PC9213
PR329
PR2509
PR2510
4.7_0603_1%
10_0402_1%
2
2
0.1U_0402_25V7K 0.1U_0402_25V7K
1 2 1 2 1 2
2
2
BATDRV 2
BATSRC 2
ACDRV-1 0.1U_0402_25V6
+19V_VIN
PR308
1 2 ACDRV
0_0402_5%
1
4.02K_0402_1%
PR352
ACP
CMSRC
ACN
1 2
PR312
PD303
10_1206_5% @ PC329
PH301 +19V_VIN 3 1 2
10K_0402_50%_TPM0S103P130R 1 1 2
2 ACDRV 1000P_0402_50V7K
+12.6V_BA+ 1U_0603_25V6K PC9214
2
1 2 BQ24800VDD
1
422K_0402_1%
5
C PC314 Support max discharge 6A(55W) C
ACDRV
ACP
ACN
28 1 2
PR311
AON7506_DFN3X3-8-5
CMSRC 2.2U_0603_16V6K VSRP-VSRN spec < 81.28mV
CMSRC REGN
2
6 PR317 PC316 4
ACDET 25 BST_CHG
PR348 0_0402_5%
BTST
0_0603_5% 0.047U_0603_25V7M 7X7X3
<58,82> EC_SMB_DA1 1 @ 2 EC_SMB_DA1_1 11
SDA
1 2 1 2 Isat: 6.5A +12.6V_BATT+
2200P_0402_50V7K
66.5K_0402_1%
@ Power
SCL HIDRV
3
2
1
PR318
PR313
VCIN1_AC_IN loss:0.297W
Close EC 5
ACOK
0.01_1206_1%
2
1
9
4.7_1206_5%
1 2 PMON
support Turbo boost : 2200P 100P_0402_50V8J PQ306
1 2 10 22
PR320
no support Tirbo boost : 0.1u @ PR321 316K_0402_1%
PROCHOT GND 1 2
AON7506_DFN3X3-8-5
SRP SRN
10U_0805_25V6K
10U_0805_25V6K
10U_0805_25V6K
PC330 100P_0402_50V8J
10U_0805_25V6K
10U_0805_25V6K
PR322 0_0402_5% +3VLP
2
PR324 100K_0402_1% 4 @
1
<97> PSYS_MON
1
13 21 1 2
1
PC322
PC320
PC332
PC331
PC333
CMPIN ILIM
680P_0603_50V7K
1
PMON: <58> VCOUT1_PROCHOT# 14 PR326 10_0402_1%
CMPOUT
2
2
2
20 1 2
PC321
BQ24780 need contact capacitor to GND SRP
3
2
1
BQ24780S need contact the pull down resistance (TBD) PR328 10_0402_1%
2
10K_0402_1%
15 19 1 2 @
BATPRES SRN @
BQ24800VDD 16 18
BST_STAT BATDRV PC323
/BATPRES
2
PR338
PR319 0.1U_0402_25V6
BATDRV
BATSRC
100K_0402_1% PU2502
1
BQ24800RUYR_WQFN28_4X4
2
0.1U_0402_25V6
0.1U_0402_25V6
1
1
PC324
PC325
1
PR325 2 1
120K_0402_1% <58,82> VCIN1_BATT_TEMP
2
0_0402_5%
3 1
S
Vin Dectector
2
2N7002KW_SOT323-3
1
<58> BATT_FW#
PR335
= 3.966 A
PC9231
2
1
**Design Notes**
For 65 /90W system, 3S1P/3S2P battery
Maximum Charging current 3A
Maximum Battery discharge power 55W
#Register Setting
1. 0X12 bit2 set 1 (default 0) to enable turbo boost function
2. Disable turbo when AC only
#Circuit Design
1. ILIM pull high voltage need base on 3/5V enable control
2. Use 7X7 choke and 3X3 H/L side MOSFET
Charge current 3A
A Power loss : 1.79W (H/S=0.227W,L/S=1.2738W,Choke=0.297W) A
Power density : 0.61 (23X16)
#Protect function
1. ACOVP : VCC voltage > 24V
2. Charger timeout : No communication within 175s(default)
3. ACOC : 3.33 X Input current DAC setting (default:Disable)
4. CHGOCP : based on charge current setting
5. BATOVP : 103-106%
6. BATLOWV : 2.6V
7. TSHUT : 155C
8. IFAULT HI : 750mV (default:Disable)
9. IFAULT LOW : 230mV (default)
Security Classification
2020/0914
Compal Secret Data
2021/09/04 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
BATTERY CHARGER(BQ24800)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OFSize
R&D Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 10, 2021 Sheet 85 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
PWR Reserve
www.teknisi-indonesia.com
B B
A A
@ PR301 PC301
PJP502 PC305 must close IC 0_0402_5% 0.1U_0402_25V6
1 2 +19VB_3V BST_3V 1 2 BST_3V_R 1 2
+19VB 1 2
2200P_0402_50V7K
JUMP_43X79
JUMP@ PU301
EMI@ PC303
EMI@ PC304
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
1
1
1
SY8388BRHC_QFN16_2P5X2P5
PC305
PC9215
1 1
IN3
IN2
IN1
BS
2
2
@ LX_3V 5 17 PL302
LX EP 2.2UH_7.8A_20%_7X7X3_M
16 LX_3V 1 4
6 LX2 +3VALWP
4.7_1206_5%
GND
1
2 3
@EMI@
PR305
15
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
LX1
1
Check pull up resistor of SPOK at HW side 3V/5VALW_PG_R 7
PC307
PC308
PC309
PC9216
PG 14
GND1
3V_SN 2
2
@ @
8 13
EN2 LDO +3VLP
680P_0402_50V7K
1
PC311
TEST
4.7U_0402_6.3V6M
OUT
EN1
1
@EMI@
PC312
FF
2
Iocp=8A
2
10
11
12
ENLDO_3V5V
+19VB_5V
PR502 PC501
PJ501 0_0402_5% 0.1U_0402_25V6
1 2 BST_5V 1 @ 2 BST_5V_R 1 2
+19VB 1 2
+19VB
10U_0603_25V6M
10U_0603_25V6M
2200P_0402_50V7K
0.1U_0402_25V6
JUMP_43X79 PU302
13
1
JUMP@ SY8370CTMC_QFN13_3X4
1
1
PC502
PC503
EMI@ PC504
EMI@ PC505
IN
BS
1
PR514
Sense 5Valw Vin PL501
1.5UH_9A_20%_7X7X3_M
2
84.5K_0402_1% LX_5V 2 12
Trigger = 9.45V LX1 LX2 LX_5V 1 4 +5VALWP
2
3 11 2 3
GND1 GND2
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
PC506
1
1
VCIN1_BATT_DROP <58> 4 10 VCC_5V 1 2
@EMI@ PR503
PC507
PC508
PC509
PC510
PC511
PC512
PC513
4.7_1206_5%
PG VCC
1
+3VALW +3VL
2
1
PR515 4.7U_0402_6.3V6M
TDC=11A
OUT
LDO
EN2
EN1
10K_0402_1% PC523 @
FF
0.1U_0402_25V6
Fsw : 600K Hz
2
2
1
1
2
@
PR306 PR6115
15V_SN
100K_0402_5% 100K_0402_5%
+5VLP
2
680P_0402_50V7K
<11,58,90> 3V/5VALW_PG
4.7U_0402_6.3V6M
5V LDO 150mA~310mA
@EMI@ PC517
3 3
1
ENLDO_3V5V
PC516
2
2
PR6114
5V_EN 1 2
0_0402_5%
@ PR6113
5V_3V_EN 1 2
PC519 PR6110
0_0402_5%
470P_0402_50V7K 1K_0402_1%
EN1 and EN2 don't be floating. 5V_FB 1 2 5V_FB_1 1 2
EN2/EN1 High > 0.8V
EN2/EN1 Low < 0.4V
PR507
PR505 100K_0402_5% Fsw : 600K Hz
499K_0402_1% PJ502
1 2 ENLDO_3V5V 1 2
+19VB PR508
+5VALWP 1 2 +5VALW
2
1 2 5V_EN
<58> EN_5VALW
1
0_0402_5% JUMP_43X118
1
PR506 JUMP@
4.7U_0402_6.3V6M
150K_0402_1% PC520
1
1U_0402_16V6K PR511 @
PC521
2
100K_0402_5% PJP501
2
1 2
+5VLP 1 2 +5VL
2
@
2
JUMP_43X39
JUMP@
4 PR509 2.2K_0402_5% 4
1 2
<58> EC_ON
PR510
1 2
<58> VCOUT0_MAIN_PWR_ON
0_0402_5%
5V_3V_EN
1M_0402_1%
4.7U_0402_6.3V6M
1
PC522
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
Custom
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P 1.0
D D
C C
PWR Reserve
B B
A A
JUMP@
+19VB PJM3
1 2 +12.6VB_DDR PRM2
1 2 2.2_0603_5%
BST_DDR_R 1 2 BST_DDR
2200P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
JUMP_43X79 +1.2VP
1
@EMI@ PCM2
EMI@ PCM1
PCM3
PCM4
UG_DDR +0.6VSP
2
D D
LX_DDR
PCM6
22U_0603_6.3V6M
1
1
PCM5
5
0.1U_0402_25V6
20
16
17
18
19
2
PUM1
2
PQM1
BOOT
PHASE
UGATE
VTT
VLDOIN
21
AON7408L_DFN8-5 PAD
4 LG_DDR 15 1
LGATE VTTGND
PLM1 14 2
1UH_6.6A_20%_5X5X3_M PRM3 PGND VTTSNS
1
2
3
20.5K_0402_1%
1 4 1 2 CS_DDR 13 3
+1.2VP PCM7 CS
RT8207PGQW_WQFN20_3X3
GND
1
2 3 1U_0201_6.3V6K
5
1 2 12 4 VTTREF_DDR
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
2 1
PCM11
PCM8
PCM12
PCM9
PCM13
PCM10
4.7_1206_5% PRM5
5.1_0603_5% 11 5
VDD VDDQ +1.2VP
1 2
1
1 2 VDD_DDR
PGOOD
+5VALW
2
4 PCM14
+5VALW PRM6
TON
1
RF@ PCM16 0.033U_0402_16V7K
FB
S5
S3
2
680P_0402_50V7K PCM15 1 2
2
PQM2 1U_0201_6.3V6K 2.2_0603_5%
10
6
2
AON7506_DFN3X3-8-5
1
2
3
EN_0.675VSP
EN_DDR
FB_DDR
TON_DDR
PRM7
C 1 2 +1.2VP C
PRM8 470K_0402_1%
+12.6VB_DDR 1 2
1. Vout=0.75V(1+6.04k/10k) =1.2V 6.04K_0402_1%
2. OCP=Current limit + Iripple/2=(20.5K*10uA/15.8ohmm)+ (2A/2)=13.9A
1
@ PRM1 0_0402_5%
1 2 PRM9
<58> SYSON
10K_0402_1%
2
1
Mode Level +0.675VSP VTTREF_1.35V @ PCM17
0.1U_0402_10V7K
S5 L off off Rds-on=13mohm(Typ), 15.8mohm(Max)
S3 L off on
2
S0 H on on Switching Frequency:530kHz
@ PRM10
Iocp~A
Note: S3 - sleep ; S5 - power off OVP: 113%~120% 1 2
<8> DDR_VTT_PG_CTRL
VFB=0.75V, Vout=1.203V PJM2
0_0402_5% 1 2
+1.2VP 1 2 +1.2V
JUMP_43X118
JUMP@
1
@ PCM18
0.1U_0402_10V7K
2
@ PR2502 PJM1
0_0402_5% 1 2
1 2 SYSON +0.6VSP 1 2 +0.6VS
JUMP_43X39
PR2503
JUMP@
B @ 0_0402_5% B
+2.5VSP_ON 1 2
PM_SLP_S4# <11,58>
0.1U_0402_16V7K
1
PC2502
1
PR2504
1M_0402_5%
@ Note:Iload(max)=3A
2
PU2501
2
9 PJ2502
1 PGND 8 1 2
FB SGND +2.5VP 1 2 +2.5V
PJ2501 2 7 PL2501
PG EN 1UH_MLV-YT12N1R0M-C1L__4A_20% JUMP_43X79
+3VALW 1 2 3 6 LX_2.5V 1 2 JUMP@
1 2 IN LX SH00001NF00 +2.5VP
1
4 5
68P_0402_50V8J
JUMP_43X79 PGND NC
1
PC2501
4.7_0603_5%
PR2506
JUMP@
1
PR2505
PC2503
22U_0603_6.3V6M
Rup
22U_0603_6.3V6M
22U_0603_6.3V6M
36.5K_0402_1%
RF@
SY8003ADFC_DFN8_2X2
PC2504
PC2505
2
2
2
FB_2.5V
1
1
FB=0.6V
680P_0402_50V7K
PR2501
Note:Iload(max)=3A Rdown
RF@PC2506
11.5K_0402_1%
2
A Vout=0.6V* (1+Rup/Rdown) A
Note:
When design Vin=5V, please stuff snubber
to prevent Vin damage Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2020/0914 Deciphered Date 2021/09/04 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RT8207P
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DSize Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 10, 2021 Sheet 89 of 121
5 4 3 2 1
5 4 3 2 1
PJ1802
D D
1 2
+1.8VALWP 1 2
+1.8VALW
PR1802 @
0_0402_5% JUMP_43X79
JUMP@
2 1
Vout=0.6V* (1+R1/R2) SLP_SUS# <11>
=0.6*(1+(14/20)) PR1803
3.3K_0402_1%
+1.8VALWP_ON 2 1
3V/5VALW_PG <11,58,87>
0.1U_0402_16V7K
1
PC1801
<95> 1.8V_PGOOD
1
PR1804
1M_0402_5%
1 2
+3VALW Note:Iload(max)=3A
2
PR1801
PU1801
2
100K_0402_5%
9
1 PGND 8
FB SGND
PJ1801 2 7 PL1801
PG EN 1UH_MLV-YT12N1R0M-C1L__4A_20%
+3VALW 1 2 3 6 LX_+1.8VALWP 1 2
1 2 IN LX SH00001NF00 +1.8VALWP
1
4 5
68P_0402_50V8J
JUMP_43X79 PC1802 PGND NC
1
PR1806
4.7_0603_5%
1
JUMP@
PR1805
PC1803
22U_0603_6.3V6M
1
200K_0402_1%
Rup
RF@
22U_0603_6.3V6M
22U_0603_6.3V6M
SY8003ADFC_DFN8_2X2
PC1804
PC1805
2
2
2
2
FB_+1.8VALWP
1
1
FB=0.6V PR1807
680P_0402_50V7K
C C
Note:Iload(max)=3A Rdown
RF@PC1806
100K_0402_1%
2
B B
A A
D D
C C
B B
A A
D D
C C
B B
A A
D D
C C
PWR Reserve
B B
A A
D D
C C
PWR Reserve
B B
A A
D D
BST_AUX_R +19VB_AUX
1
PRG1
2.2_0603_5% PCG2 PRG2
0.1U_0402_25V6 @ 0_0805_5%
2
+19VB_AUX +19VB
2
OCP is Lowside MOSFET Rdson sense PLG2
2
ICCMAX=26A
BST_AUX
1 2
TDC=10A
0.1U_0402_25V6
1
226K x1.2 5A_Z80_0805_2P
2200P_0402_50V7K
DC LL=TBD
PCG1
PCG8
PCG4
10U_0603_25V6M
10U_0603_25V6M
0.1U_0402_25V6
255K x1.4
1
EMI@
PCG3
PCG7
PUG1
1
AC LL=TBD
10
RT6543AGQW_W QFN20_3X3
2
PRG4
EMI@
@EMI@
BOOT
2
255K_0402_1%
1 2 CS_DSI_RT6543 1 20 VSYS_RT6543
CS_DIS VSYS
+5VALW UG_AUX
1
2 1
PCG5 1U_0402_6.3V6K PQG1 PLG1
D1
G1
PRG7 5.1_0603_5% AONY36352_DFN5X6D-8-7 0.24UH_22A_+-20%_7X7X3_M
1 2 VCC_RT6543 16 12 LX_AUX
VCC PH 7 LX_AUX 1 4
2 1 D2/S1
PCG6 1U_0402_6.3V6K PRG8 ISENSEP_AUX 2 3 ISENSEN_AUX
S2-1
S2-2
S2-3
High > 1V 100K_0402_1%
G2
1
LG_AUX
+3VALW 1 2 4 13
@EMI@ PRG9
4.7_1206_5%
9.53K_0402_1%
PGOOD LGATE
Low <0.4V
PRG10
3
6
<58> VCC_AUX_PWRGD
PRG11
1 AUX_SNUB
C C
2
1 2 EN_RT6543 19 14 LG_AUX
<90> 1.8V_PGOOD EN PGND
1ISENSEP_AUX_R
1
@
0_0402_5% PCG9
1
0.1U_0402_25V6 PRG12
@EMI@ PCG10
680P_0402_50V7K
2
9.53K_0402_1%
2
PRG14
+3VALW 18 3 ISENSEN_RT6543 1 @ 2 ISENSEN_RT6543_R
PRG15
<17> VCCIN_AUX_CORE_VID0_R VID0 ISENSEN
PCG11 0_0402_5% +VCCIN_AUX
1 2 PRG19 PRG20
@ PRG16
PRG18
2
100K_0402_1% 0.1U_0402_25V6 PRG17 1 2 1 2
1 2 FSW SEL_RT6543 9 8 VOUT_RT6543 1 @ 2 2 1
+5VALW
ISENSEN_RT6543_R
FSWSEL VOUT 1.05K_0402_1% 1.37K_0402_1%
0_0402_5%
1
100_0402_1% PHG1
@PRG21
100K_0402_1% PCG12 2200P_0402_50V7K PRG23 10K_0402_1% PCG13 390P_0402_50V7K @ PRG24 1.6K_0402_1% ISENSEN_AUX_NTC 1 2
1
5 COMP_RT6543 1 2 1 2 1 2 1 2
COMP
10K_0402_1%_B25/50 3370K
PRG25 PRG22
2
ISENSEP_RT6543_R
10K_0402_1% 10K_0402_1%
B=3435(B25/85)
PCG14 27P_0402_50V8J PRG26 6.34K_0402_1%
2
VCCIN_AUX_CORE_VID1_R FB_RT6543
6 1 2 1 2
VCCIN_AUX_CORE_VID0_R
5V: 800KHz FB 1 2
2
Float: 600KHz PRG27 PCG15
GND: 400KHz PRG30 @ 0_0402_5% 0.1U_0402_25V6
1
7 RGND_RT6543 1 @ 2
RGND VCCIN_AUX_VSSSENSE <17>
AGND
1
10K_0402_1% 10K_0402_1%
1
VCCIN_AUX_VCCSENSE <17>
PRG31
2
21
1
100_0402_1%
PCG16
@ PCG17 0.1U_0402_25V6
2
2
1 2
0.082U_0402_16V7K
330P_0402_50V7K
@ PCG18
1
B B
2
VCCIN_AUX VID Follow Intel PDG Rev0.71 @PCG29
1 2
0 1 1.1
1 0 1.65
1 1 1.8
A A
Compal Electronics
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D +VCCIN_AUX
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0
D D
C C
PWR Reserve
B B
A A
1
PRZ1
6.8_0603_1%
2 VCC_RT3613EE 24 8 VIN_RT3613EE
PRZ2
1
2.2_0603_5%
2
+19VB_VCCIN
teknisi-indonesia.com D
2
1 2
PCZ1
4.7U_0402_6.3V6M
1
PRZ4 0_0402_5%
Pull High in HW site. PRZ5
VRON
9 VRON_RT3613EE 1 2
VR_ON
High: > 0.7V
<11,58>
<58> VR_HOT#
75_0402_5%
1 2 VRHOT_RT3613EE 16
@ PCZ3 0.1U_0402_25V6
1 2 Low: < 0.3V
VR_HOT
PRZ6 0_0402_5%
12 PWM1_RT3613EE 1 @ 2
VREF06_RT3613EE PWM1 PWM1_VCCIN <98>
PRZ7 0_0402_5%
13 PWM2_RT3613EE 1 2
PRZ3
PWM2
@ PWM2_VCCIN <98> 2 phase
VREF06_RT3613EE 0.6V 3.9_0402_1%
1 2 26 PRZ72 0_0402_5% PRZ75, PRZ76 are unpop.
VREF06 11 PWM3_RT3613EE 1 @ 2
PWM3 PWM3_VCCIN <98> PRZ68, PRZ70, PRZ71, PCZ82, PCZ83, PRZ72 unpop
1
PCZ4
2 pahse 0.47U_0402_6.3V6K
NC
14
2
PRZ19 is 0ohm
12K_0402_1%
2.1K_0402_1%
29.4K_0402_1%
1
2.8K_0402_1%
1
PRZ13 1.6K_0603_1% PRZ14 1.6K_0603_1%
PRZ15 0_0402_5%
PRZ27 is 7.68K ohm
PRZ9
PRZ10
PRZ11
4 ISENSE1P_VCCIN_RR 1 2 ISENSE1P_VCCIN_R1 2
PRZ12
ISEN1P ISENSE1P_VCCIN <98>
<98> DRVEN_VCCIN 1 @ 2DRVEN_RT3613EE 15
DRVEN
1
PRZ17
2 1 PCZ5
2
2
3.24K_0402_1%
2
@PRZ16 100K_0402_1% 0.1U_0402_25V6
2
7.5K_0402_1%
1
PRZ23 110K_0402_1% 3 ISENSE1N_VCCIN_R 1 2
196K_0402_1%
ISENSE1N_VCCIN <98>
18.2K_0402_1%
10.2K_0402_1%
ISEN1N
2
1
1
VR_HOT# 100 degreeC 1 2 PCZ6 0.1U_0402_25V6
PRZ22
PRZ18 681_0402_1%
1 2
PRZ19
PRZ20
PRZ21
ALERT# 97 degreeC Close to Phase1 Inductor
C 7 C
PHZ1 PRZ24 1.6K_0603_1% PRZ25 1.6K_0603_1%
TSEN
2
TSEN_R_RT3613EE 1 2 TSEN_RT3613EE 1 ISENSE2P_VCCIN_RR 1 2 ISENSE2P_VCCIN_R 1 2
ISEN2P ISENSE2P_VCCIN <98>
2
1
100K_0402_1%_B25/50 4250K
SET1_RT3613EE 22 PCZ7
SET1 PRZ26
0.1U_0402_25V6
3.24K_0402_1%
2
SET2_RT3613EE 21
SET2 ISENSE2N_VCCIN_R 1
18.2K_0402_1%
2 2
1
ISENSE2N_VCCIN <98>
1.5K_0402_1%
ISEN2N
2
SET3_RT3613EE
1
10.2K_0402_1% 10K_0402_1%
10K_0402_1% 1 2
1
PRZ29
27K_0402_1%
1
1 2
+5VALW
PRZ30
5 ISENSE3P_VCCIN_RR 1 2 ISENSE3P_VCCIN_R
1 2
2
1
1 2
3K_0402_5%
1
1 2
PCZ82
15.8K_0402_1%
PRZ68
0.1U_0402_25V6
PRZ33
PRZ34
3.24K_0402_1%
2
PRZ35
14.3K_0402_1%
100_0402_1%
45.3_0402_1%
1
PCZ9 6 ISENSE3N_VCCIN_R 1 2
PRZ36
2
0.1U_0402_25V6 @ PRZ76 PCZ83 0.1U_0402_25V6
PRZ37
PRZ38
PRZ69 681_0402_1%
2
10K_0402_1% 1 2
2
2
1 2
+5VALW
+VCCIN
2
32 @ PRZ73
PRZ41 NC
0_0402_5% 10K_0402_1%
1 @ 2 SVID_CLK_PWR_VCCIN 19 1 2
<15> SOC_SVID_CLK_R VCLK +5VALW
2
PRZ74
PRZ42
<15> SOC_SVID_DAT_R
1 @
0_0402_5%
2 SVID_DAT_PWR_VCCIN 18 31
10K_0402_1%
1 2 debug only @ PRZ44
100_0402_1%
VDIO NC
remote sense in HW site.
PRZ45
1
PRZ46
1 @ 2 SVID_ALERT#_PWR_VCCIN 17 28 VSEN_VCCIN 1 @ 2
<15> SOC_SVID_ALERT#_R ALERT VSEN VCCIN_VCCSENSE <15>
B PCZ10 82P_0402_50V8J PCZ11 150P_0402_50V8J 0_0402_5% @ PCZ12 B
+3VS 0_0402_5% 29 COMP_VCCIN 1 2 1 2 1 2
COMP
0.082U_0402_16V7K
PRZ47 10K_0402_1%
1 2 10 PRZ48 18.2K_0402_1% PRZ49 8.45K_0402_1% 330P_0402_50V7K
@ PCZ13
VR_READY
1
1 2 1 2
2
0.47U_0402_6.3V6K 30 FB_VCCIN @PCZ15
1 2 FB 1 2
PRZ50 0.01UF_0402_25V7K
16.2K_0402_1%
Close to Phase1 Inductor 1 2 23 PRZ51 0_0402_5%
PSYS 27 RGND_RT3613EE 1 @ 2
RGND VCCIN_VSSSENSE <15>
VREF06_RT3613EE LL/IMON Compesation
<85> PSYS_MON
1
PRZ52 PHZ2 PRZ53
3.9K_0402_1% 100K_0402_1%_B25/50 4250K 17.4K_0402_1% @ PRZ54
1 2 NTC1P_VCCIN 1 2 NTC1N_VCCIN 1 2 IMON_RT3613EE 25 33 100_0402_1%
IMON GND
debug only
2
RT3613EEGQW-02_WQFN32_4X4
PRZ55
16.9K_0402_1%
1 2
31 pin is a function to fix decay down slew rate to reduce acoustic noise.
High(5V): enable (5V is request)
Low:(0V): disable
this pin can dynamic change state.
A A
Compal Electronics
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL +VCCIN(RT3613EE)
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 10, 2021 Sheet 97 of 121
5 4 3 2 1
5 4 3 2 1
ICCMAX=62A
TDC=36A
Frequency 600KHz
PRZ56
2200P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
33U_25V_NC_6.3X4.5
33U_25V_NC_6.3X4.5
PLZ5
33U_25V_NC_6.3X4.5
2.2_0603_5%
@EMI@ PCZ20
EMI@ PCZ21
PCZ34
PCZ35
1 1
0.1U_0402_25V6
BST_VCCIN1 BST_VCCIN1_R 1
1 2 1 2
1
+ + +
PCZ22
PCZ85
PCZ84
1
PCZ19 5A_Z80_0805_2P
0.1U_0402_25V6
PUZ2
2
UG_VCCIN1 2 2 2 EMI@
2
4 3 UG_VCCIN1
BOOT UGATE
5 2 LX_VCCIN1
<97> PWM1_VCCIN PWM PHASE
1
1 6 PQZ1 Rdc=0.9±5%mohm
D1
G1
97> DRVEN_VCCIN EN PGND
AONY36352_DFN5X6D-8-7 +VCCIN
+5VALW PLZ1
8 7
PRZ58 VCC LGATE 9 7 LX_VCCIN1 1 4
1 2VCC_VCCIN1 GND D2/S1
2 3
S2-1
S2-2
S2-3
2.2_0603_1% RT9610CGQW_W DFN8_2X2
@EMI@ PRZ59
4.7_1206_5%
G2
1
0.15UH_NA__35A_20%
6
1
PCZ38
1U_0402_6.3V6K
2
1 SNUB_VCCIN1 2
ISENSE1N_VCCIN <97>
@EMI@ PCZ49
LG_VCCIN1
680P_0402_50V7K
2
ISENSE1P_VCCIN <97>
C C
+19VB_VCCIN
PRZ60
2200P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
2.2_0603_5%
@EMI@ PCZ56
EMI@ PCZ57
PCZ58
PCZ59
0.1U_0402_25V6
BST_VCCIN2 1 2 BST_VCCIN2_R
1
1
PCZ62
0.1U_0402_25V6
PUZ3
2
UG_VCCIN2
2
4 3 UG_VCCIN2
BOOT UGATE
5 2 LX_VCCIN2
<97> PWM2_VCCIN PWM PHASE
2
G1
EN PGND +VCCIN
AONY36352_DFN5X6D-8-7 PLZ2
+5VALW 8 7
PRZ62 VCC LGATE 9 7 LX_VCCIN2 1 4
1 2VCC_VCCIN2 GND D2/S1
2 3
S2-1
S2-2
S2-3
0.15UH_NA__35A_20%
3
6
1
PCZ63
1U_0402_6.3V6K
2
1SNUB_VCCIN2 2
LG_VCCIN2
@EMI@ PCZ64
ISENSE2N_VCCIN <97>
680P_0402_50V7K
2
B B
ISENSE2P_VCCIN <97>
+19VB_VCCIN
PRZ67
2200P_0402_50V7K
10U_0603_25V6M
10U_0603_25V6M
2.2_0603_5%
@EMI@ PCZ77
EMI@ PCZ76
PCZ78
PCZ81
0.1U_0402_25V6
BST_VCCIN3 1 2 BST_VCCIN3_R
1
1
1
PUZ4
PCZ75
0.1U_0402_25V6 2 Phase unpop
2
UG_VCCIN3
2
4 3 UG_VCCIN3
BOOT UGATE
5 2 LX_VCCIN3
<97> PWM3_VCCIN PWM PHASE
2
DRVEN_VCCIN 1 6 PQZ3
Rdc=0.9±5%mohm
D1
G1
EN PGND +VCCIN
AONY36352_DFN5X6D-8-7 PLZ3
+5VALW 8 7
PRZ64 VCC LGATE 9 7 LX_VCCIN3 1 4
1 2VCC_VCCIN3 GND D2/S1
2 3
S2-1
S2-2
S2-3
0.15UH_NA__35A_20%
3
6
1
PCZ80
1U_0402_6.3V6K
2
1SNUB_VCCIN3 2
A A
LG_VCCIN3
@EMI@ PCZ79
ISENSE3N_VCCIN <97>
680P_0402_50V7K
2
ISENSE3P_VCCIN <97>
Compal Electronics
Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D CPU MOSMDecoupling cap
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Size Document Number Rev
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 1.0
D D
C C
PWR Reserve
B B
A A
D D
C C
PWR Reserve
B B
A A
5
5
@
PCZ16
330U_D2_2.5VY_R9M
2
1
+
+VCCIN
+VCCIN
2 1 2 1
PCZ17
PCZ71 PCZ23 330U_D1_2.5VY_R9M
22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
+
2 1 2 1
PCZ68 PCZ24
22U_0603_6.3V6M 22U_0603_6.3V6M
+VCCIN
2 1 2 1
2 1
PCZ67 PCZ25
PCZ50 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
PCZ69 PCZ26
PCZ51 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
330U_R9
PCZ70 PCZ27
Compal :
2 1
1U_0201 *6
PCZ72 PCZ28
*1
4
4
1U_0201_6.3V6M 2 1 2 1
Primary side :
2 1
@
PCZ65 PCZ29
@
PCZ54 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
2 1
PCZ66 PCZ30
@
PCZ55 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 2 1 2 1
@
PCZ73 PCZ31
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
@
PCZ74 PCZ32
22U_0603_6.3V6M 22U_0603_6.3V6M
Issued Date
Security Classification
3
3
2020/0914
Compal Secret Data
Deciphered Date
2 1 2 1
+VCCIN_AUX
PCG56 PCG19
2
1
+
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 PCG45
330U_D2_2.5VY_R9M
+VCCIN_AUX
PCG51 PCG20
2
1
+
22U_0603_6.3V6M 22U_0603_6.3V6M
@
2 1 2 1 PCG46
2
2
330U_D1_2.5VY_R9M
PCG50 PCG21
2021/09/04
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1
2 1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
PCG22
PCG57 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
2 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
PCG23
PCG58
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
22U_0603_6.3V6M
22U_0603_6.3V6M 2 1
2 1
Size
330U_R9
Title
Date:
PCG24
PCG59
22U_0603
22U_0603_6.3V6M
Custom
22U_0603_6.3V6M 2 1
2 1
PCG25
*1
PCG60 22U_0603_6.3V6M
*18
22U_0603_6.3V6M 2 1
2 1
PCG26
Document Number
PCG61 22U_0603_6.3V6M
22U_0603_6.3V6M 2 1
LA-L161P
PCG27
22U_0603_6.3V6M
W ednesday, March 10, 2021
2 1
PCG28
22U_0603_6.3V6M
1
1
Sheet
101
+APU_CORE Cap
Compal Electronics, Inc.
of
121
Rev
1.0
A
B
C
D
5 4 3 2 1
D D
C C
PWR Reserve
B B
A A
+3VALW +3VALW
+3VS +3VS
4.7K_0201_1%
4.7K_0201_1%
4.7K_0201_1%
4.7K_0201_1%
1
1
+5VS +5VALW
D D
PRV2
+1V8_AON
2
PRV3
PRV4
PRV96
PRV95
PRV91
2_0603_1%
2_0603_1%
2
2
@
Place close to
PRV1 @ @ GPU pins
@ 0_0402_5%
1
2
1 2 PRV12
PRV6
10K_0402_1%
<28,37> VGA_I2CC_SDA_R_Q
2
51_0402_1%
PRV5
10K_0402_1%
+3VS +3VALW PRV7 @ 0_0402_5% 1 2
<28,37> VGA_I2CC_SCL_R_Q 1 2 @ PRV10
PRV99
1K_0402_1% 0_0402_5%
1
2
PRV9 @ 0_0402_5% 1 2 1 2
1
PRV8 @ PRV94 @ 1 2 NVVDD_VSS_SENSE <31>
<34> NVVDD_EN @ PRV98
10K_0402_1% 10K_0402_1% PRV11 PCV2 0_0402_5%
0_0402_5% 2.2U_0402_6.3V6M 1 2
1 2 1 2 MSVDD_VSS_SENSE <31>
1
1
@ PRV14 0_0402_5% 0_0402_5%
1 2 PCV3 1 2
@ PCV4 <28> NVVDD_VID 1000P_0402_50V8-J NVVDD_VDD_SENSE <31>
Config P0/P1 G61 @ PRV97
2
4700P_0402_25V7K PRV16 6.19K_0402_1%
R1 0_0402_5%
NVVDD_PSI_R
1 2 1 2 1 2
NVVDD_EN_R
NVVDD_VCC
NVVDD_SDA
R4 R3
NVVDD_SCL
MSVDD_VDD_SENSE <31>
Vmin 0.3
2
0.3 G61@
PRV20
R5 P0_P1@ P0_P1@ R2 PCV5 PCV6 PRV22
309_0402_1% PRV18 2 1 610_VREF
P0_P1@ PRV20 PRV21 47P_0402_50V8J 330P_0402_50V8J 49.9_0402_1%
Vmax 1.3 1.3 274_0402_1% 13.7K_0402_1% 2.8K_0402_1% 2 1 2 1 2 1
2 1 2 1 PRV19
1
20.5K_0402_1%
0.8
40
39
38
37
36
35
34
33
32
31
Vboot 0.75
C PCV7
4700P_0402_25V7K G61@
PRV21 PCV8
0.01U_0402_50V7K
PRV23
3.3K_0402_1%
PRV25
1K_0402_1%
PWM_VID
PGOOD
PSI
EN
SCL
VSN
VCC
VID_BUFF
VSP
SDA
1 2 16.5K_0402_1% 1 2 2 1 2 1
R1 6.19K 6.19K PRV24
1K_0402_1%
1 2 PCV9 610_REFIN 1 30
C
R2 20.5K 20.5K +19VB_GPU 0.01U_0402_50V7K REFIN COMP
C
PCV10 1 2 610_VREF 2 29
VREF FB PRV29
R3 2.8K 4.32K 0.01U_0402_50V7K
1 2 3 PUV1 28
G61@
VRMP DIFF 32.4K_0402_1%
NCP81611MNTXG_QFN40_5X5
4 27 1 2 PRV26
R4 13.7K 16.5K PWM8/SS FSW 23.7K_0402_1%
5 26 610_TSENSE PRV28 1 2 0_0402_5%
PWM7/I2C TMON
309 PCV1 from 1000P_0402 change to
R5 274 6
PWM6/LPC1 IOUT
25 P0_P1@ 1 2
220P_0402. (for AutoPSI enable)
PRV29 23.7K_0402_1%
7 24 610_ILIM 1 P0_P1@ 2 PRV30 1 2
C 4.7n 4.7n PWM5/LPC2 ILIM 113K_0402_1% PCV1 220P_0402_50V8J
PRV30 = 113K
8 23
PWM4/PHTH1 CSCOMP which follow NV’s suggestion OCL= 75A
9 22
<105> 610_PWM3 PWM3/PHTH2 CSSUM
PWM1/PHTH4
PRV30
1
10 21 G61@
<104> 610_PWM2 PWM2/PHTH3 CSREF
51.1K_0402_1% P0_P1@ PRV31
1
1
DRON
453K_0402_1% 1M ohm for OCP=80A
CSP4
CSP3
CSP2
CSP1
10K_0402_1%
13.3K_0402_1%
24.9K_0402_1%
NC1
NC2
NC3
NC4
2
41 PCV11
PRV90
PRV89
PRV88
10K_0402_1%
10K_0402_1%
26.1K_0402_1%
26.1K_0402_1%
AGND
2
0.01U_0402_50V7K
PRV32
PRV33
PRV34
PRV35
100P_0402_50V8J
2
11
12
13
14
15
16
17
18
19
20
2
PRV31
PCV12
@ @ G61@
2
@
750K_0402_1%
1
1
2K_0402_1%
2K_0402_1%
2 1 PRV39 499_0402_1% 610_VREF
<104> 610_PWM1
2 1 PCV13 100P_0402_50V8J
<104,105> 610_DRON
1
2
2 1 PRV40 499_0402_1%
40.2K_0402_1%
2
@
PRV87
140_0402_1%
B B
1
2 1 PCV14 100P_0402_50V8J
PRV85
PCV15
2
2 1 PRV42 499_0402_1%
PRV104
PRV103
1
P0_P1@
2 1 PCV16 100P_0402_50V8J PRV47 1 2 301K_0402_1% 610_CSP3
+5VALW +5VS
2
261_0402_1%
+5VALW
PRV86
2
+5VS
2K_0402_5%
2K_0402_5%
1
PR6108
PR1052
<104,105>
610_CSREF
1
@ @
PR1055 0_0603_5%
2 1 610_CSREF
2
PR1057
PC1019
1U_0603_25V6
2
0_0402_5% @
3
AZ431LBNTR-E1 SOT-23
<105>
<104>
<104>
610_CSP3
610_CSP2
610_CSP1
K
1
@
PU1001
2
R
A
@
2
10K_0402_5%
1
PR1059
1
A @ A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VGA-NCP81611
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 10, 2021 Sheet 103 of 121
5 4 3 2 1
1 2 3 4 5
EMI@ PL1802
+19VB 5A_Z80_0805_2P +19VB_GPU_B +19VB_GPU +19VB_FBVDD
PR1301 PR1302
1 2 1 4 1 4
EMI@ PL1803 2 3 2 3
5A_Z80_0805_2P
1 2
0.005_1206_1% 0.005_1206_1%
+19VB_GPU
EMI@ PL1804
5A_Z80_0805_2P
1 2
68P_0402_50V8J
10U_0805_25VAK
10U_0805_25VAK
0.1U_0402_25V6
33U_D1_25VM_R6M
2200P_0402_50V7K
33U_25V_NC_6.3X4.5
EMI@ PCV20
EMI@ PCV19
@RF@ PCV464
A 1 1 A
1
<37> CSSP_B+ <37> CSSN_B+ CSSP_FBVDD <37>
<37> CSSN_FBVDD
PCV23
PCV24
PCV58
PCV569
+ +
PRV56
2
1 @ 2
2 2 @
ZCD_EN1
0_0402_5%
PRV59
4.7_0603_1%
1 2
BST_NVVDD1_R
BST_NVVDD1
+5VALW
PUV2
16
17
11
10
13
1
9
NCP303152MNTWG_PQFN41_5X6
PCV26
ZCD_EN
VIN1
VIN
FAULT
N/C
BOOT
0.22U_0603_25V7K
2
PCV27 1
2.2U_0402_6.3V6M NC PHASE_NVVDD1
1 2 4 12
PVCC PHASE
1 2 3
VCC
PRV60 2
AGND
1
2_0402_5%
5
PCV28 PGND
2
2.2U_0402_6.3V6M 20
PGND2
1
<103,105> 610_DRON 15 2 3
DISB#
18 PRV62
<103> 610_CSP1 IMON 0.22UH_MHTMHDZIR22MEM_45A_20%
B 4.7_1206_5% B
PRV61 19
PGND1
REFIN
2
10_0402_1%
GL2
1 2 13X8X4
GL
<103,105> 610_CSREF
1
RF@
PCV29
Isat:77A
DCR:0.48mΩ(+/-5%)
7
21
1 680P_0402_50V7K
2
PCV30
0.1U_0402_25V6
2
+19VB_GPU
68P_0402_50V8J
10U_0805_25VAK
10U_0805_25VAK
0.1U_0402_25V6
2200P_0402_50V7K
EMI@ PCV60
EMI@ PCV59
@RF@ PCV465
1
1
PCV62
PCV61
PRV63
2
2
C C
1 @ 2
ZCD_EN2
0_0402_5% PRV66
4.7_0603_1%
1 2
BST_NVVDD2 BST_NVVDD2_R
+5VALW
PUV3
1
16
17
11
10
13
9
NCP303152MNTWG_PQFN41_5X6
PCV35
ZCD_EN
VIN1
VIN
FAULT
N/C
BOOT
0.22U_0603_25V7K
2
PCV36 1
2.2U_0402_6.3V6M NC PHASE_NVVDD2
1 2 4 12
PVCC PHASE
1 2 3
VCC
PRV67 2
AGND
1
2_0402_5%
5
PCV37 PGND
2
2.2U_0402_6.3V6M 20
PGND2
<103> 610_CSP2 18
IMON PRV69 0.22UH_MHTMHDZIR22MEM_45A_20%
PRV68 19 4.7_1206_5%
PGND1
10_0402_1% REFIN
2
GL2
610_CSREF 1 2
GL
D D
1
RF@
6
7
21
1
PCV38
PCV39 680P_0402_50V7K
2
0.1U_0402_25V6
2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-NVVDD1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 10, 2021 Sheet 104 of 121
1 2 3 4 5
1 2 3 4 5
+19VB_GPU
68P_0402_50V8J
10U_0805_25VAK
10U_0805_25VAK
0.1U_0402_25V6
2200P_0402_50V7K
EMI@ PCV64
EMI@ PCV63
@RF@ PCV466
A A
1
PCV66
PCV65
2
2
PRV70
1 2
ZCD_EN3
PRV73
@ 0_0402_5% 4.7_0603_1%
1 2
BST_NVVDD3_R
BST_NVVDD3
+5VALW
1
PUV4
16
17
11
10
13
9
PCV44
NCP303152MNTWG_PQFN41_5X6
0.22U_0603_25V7K
ZCD_EN
VIN1
VIN
FAULT
N/C
BOOT
2
PCV45 1
2.2U_0402_6.3V6M NC
1 2 4 12 PHASE_NVVDD3
PVCC PHASE
1 2 3
VCC
PRV74 2
AGND
1
2_0402_5%
5
PCV46 PGND
2
2.2U_0402_6.3V6M 20
PGND2
1
18
<103> 610_CSP3 IMON 0.22UH_MHTMHDZIR22MEM_45A_20%
B PRV76 B
PRV75 19 4.7_1206_5%
PGND1
10_0402_1% REFIN
2
GL2
1 2
GL
<103,104> 610_CSREF
1
6
7
21
1 RF@ PCV47
PCV48 680P_0402_50V7K
2
0.1U_0402_25V6
2
C C
D D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-NVVDD2
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, March 10, 2021 Sheet 105 of 121
1 2 3 4 5
5 4 3 2 1
D D
C C
PWR Reserve
B B
A A
2 1 2 1
@
PCV507 PCV472 2
1
+
D7
5
5
@
@
PCV559 PCV544 PCV525
@
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M PCV508 PCV473
2
1
+
2 1 2 1 2 1 1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 PCV468
560U_D1_2VM_R4.5M
@
@
PCV560 PCV545 PCV526
@
PCV509 PCV474
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M
1U_0201_6.3V6M 1U_0201_6.3V6M
2 1 2 1 2 1
2
1
+
2 1
PCV469
@
@
PCV561 PCV546 PCV527 PCV475 560U_D1_2VM_R4.5M
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_6.3V6M
2 1 2 1 2 1 2 1
2
1
+
@
PCV476
@
PCV562 PCV547 PCV528 PCV470
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_6.3V6M 560U_D1_2VM_R4.5M
2 1
Place near GPU
2 1 2 1 2 1
2
1
+
PCV477
@
@
PCV563 PCV548 PCV529
22U_0603_6.3V6M PCV471
22U_0603_6.3V6M 22U_0603_6.3V6M 1U_0201_6.3V6M
560U_D1_2VM_R4.5M
2 1 2 1
2 1 2 1
PCV478
@
@
PCV564 PCV549 PCV530
22U_0603_6.3V6M 1U_0201_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1
2 1 2 1 2 1
PCV479
@
@
PCV565 PCV550 PCV531 1U_0201_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 2 1
2 1 2 1 2 1
PCV480
@
@
PCV566 PCV551 PCV532 1U_0201_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 2 1
2 1 2 1 2 1
PCV481
@
@
PCV567 PCV552 PCV533 1U_0201_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 2 1
2 1 2 1 2 1
PCV482
@
@
PCV568 PCV553 PCV534 1U_0201_6.3V6M
22U_0603_6.3V6M 22U_0603_6.3V6M 22U_0603_6.3V6M 2 1
4
4
2 1 2 1 PCV483
+NVVDD
1U_0201_6.3V6M
@
PCV554 PCV535
22U_0603_6.3V6M 22U_0603_6.3V6M 2 1
2 1 2 1 PCV484
330U_B2X1
560U_R9 X4
GN20-P0/P1
1U_0201_6.3V6M
@
PCV555 PCV536 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M
1uF_0201 X13
2 1 2 1 PCV485
22uF_0603 X 15
10uF_0402 X 34
1U_0201_6.3V6M
@
PCV556 PCV537 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M
@
2 1 2 1 PCV486
1U_0201_6.3V6M
@
PCV557 PCV538 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M
@
2 1 2 1 PCV487
1U_0201_6.3V6M
@
PCV558 PCV539 2 1
22U_0603_6.3V6M 22U_0603_6.3V6M
@
PCV488
1U_0201_6.3V6M
2 1
@
PCV489
1U_0201_6.3V6M
2 1
@
PCV490
1U_0201_6.3V6M
2 1
@
PCV491
1U_0201_6.3V6M
3
3
+NVVDD
Issued Date
2 1 2 1 2 1
Security Classification
PCV540 PCV510 PCV492
10U_0402_6.3V6M 10U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1 2 1
PCV514 PCV496
10U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1
Place under GPU
PCV515 PCV497
10U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1
PCV516 PCV498
10U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1
2
2
PCV518 PCV500
10U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1
PCV519 PCV501
10U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1
PCV520 PCV502
10U_0402_6.3V6M 10U_0402_6.3V6M
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
2 1 2 1
PCV521 PCV503
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
10U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCV522 PCV504
C
10U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1
Size
Title
Date:
PCV523 PCV505
10U_0402_6.3V6M 10U_0402_6.3V6M
2 1 2 1
PCV524 PCV506
10U_0402_6.3V6M 10U_0402_6.3V6M
Document Number
Sheet
PWR- GPU_CORE Cap
107
Compal Electronics, Inc.
of
121
Rev
1.0
A
B
C
D
5 4 3 2 1
+19VB_FBVDD
EMI@ PLW 1
FBMA-L11-201209-800LMA50T
B+_+1.35VS_VGAP 1 2
2200P_0402_50V7K
0.1U_0402_25V6
10U_0805_25VAK
10U_0805_25VAK
PRW 2
PCW2
PCW3
D D
1
1K_0402_1%
PCW7
PCW8
1 2
<34> 1.35VSDGPU_EN
2
EMI@
EMI@
PCW 10
0.1U_0402_25V6 MOSFET: DFN 5X6E
1 2
Samesung & Micron VRAM PSI=0.79V H/S Rds(on): 5.2mohm(Typ), 7mohm(Max)
When,VRAM_VDD_CTL=High +3VALW L/S Rds(on): 0.8mohm(Typ), 1.05mohm(Max)
When the voltage is
Vboot=1.25V between 0.7V to 0.88V, +1.35VSDGPU
When,VRAM_VDD_CTL=Low the devicewill operate into N18P-G62
1
SW 1_+1.35VS_VGAP
Vboot=1.2V 1 phase force CCM PRW 3 TDC 17.2A
31.6K_0402_1%
UG1_+1.35VS_VGAP 13.1 X 8.1 X 3 Peak Current 18.4A
Isat:50A OCP current 30A
DCR:0.74mΩ(+/-5%)
2
1
PRW 137
2
PQW 1 fsw=400kHz
<28> FBVDD_PSI# 0_0402_5% NTMFD001N03P9_DFN8-10 PLW 2
0.47UH_STPI120804-R47M-HF-TW_40A_20%
+1.35VS_VRAM
4
2
1
SW 1_+1.35VS_VGAP-1 1 2
PRW 5 SH00001VW00
HSG
V+_1
V+_2
GR
10K_0402_1%
22U_0603_6.3V6M
22U_0603_6.3V6M
PRW 7 B+_+1.35VS_VGAP 10 9
1
PCW24
PCW25
V+_HSD GND 1 1
2
@ PCW 14 2.2_0603_5% RF@ PRW 6
330U_B2_2.5VM_R9M
2 1
560U_D2_2VM_R4.5M
SW_3
SW_2
SW_1
VREF_+1.35VS_VGAP 4.7_1206_5% + +
PCW11
PCW12
LSG
0.1U_0402_16V7K
BOOT1_+1.35VS_VGAP_R
2
2
1 2
2 2
BOOT1_+1.35VS_VGAP
SNB1_+1.35VS_VGAP
PCW23
0.1U_0402_25V6
5
UG1_+1.35VS_VGAP
PRW22
VID_+1.35VS_VGAP
EN_+1.35VS_VGAP
1
1 2
4.87K_0402_1%
C LG1_+1.35VS_VGAP C
REF1 @ PRW 9
2
10K_0402_1%
1 2
REFADJ
2
<28> VRAM_VDD_CTL
PRW 135
PRW 25 0_0402_5%
1
100K_0402_1% RF@ PCW 15
1
REFADJ_+1.35VS_VGAP_R 1 2 REFADJ_+1.35VS_VGAP 680P_0402_50V7K
1
5
3
PCW 16
2
0.22U_0603_25V7K
PCW21
2200P_0402_50V7K
UGATE1
BOOT1
VID
EN
PSI
2
PRW23
1
1
11K_0402_1%
REFADJ_+1.35VS_VGAP 6 20 SW 1_+1.35VS_VGAP
REFADJ PHASE1
RBOOT OCP=[[(10uA*76.8k)/12/1.8m]+(12A/2)]*1phase=41.5A
2
REFIN_+1.35VS_VGAP 7 19 LG1_+1.35VS_VGAP
REFIN LGATE1
2
PRW 12
2.2_0603_5%
VREF_+1.35VS_VGAP 8 18 PVCC_+1.35VS_VGAP 1 2
VREF PVCC +5VALW
REFIN_+1.35VS_VGAP PRW 14 PRW 15 PUW 1
2.2_0402_1% 453K_0402_1% RT8816BGQW_W QFN20_3X3
2 1 2 1 TON_+1.35VS_VGAP 9 17
B+_+1.35VS_VGAP TON LGATE2
2200P_0402_50V7K
1
1
PRW24
PCW22
26.7K_0402_1%
OCSET/SS
1
PCW 19 RGND 10 16
RGND PHASE2
UGATE2
PGOOD
0.1U_0402_25V6
BOOT2
PCW 18
VSNS
2 1TON_+1.35VS_VGAP_R
REF2
2
GND
2.2U_0402_6.3V6M
2
2
PRW 136
1 2
21
11
1OCset_+1.35VS_VGAP 12
13
14
15
<31> FB_GND_SENSE 0_0402_5%
B B
1.35VSDGPU_PG
10_0402_1%
PRW 16
Vout=2V*(14k/(14k+9.31k))=1.2012V
Vsense_+1.35VS_VGAP
2
76.8K_0402_1%
PRW 134
1 2
2 PRW18
<31> FB_VDDQ_SENSE 0_0402_5%
PRW 17
1 2
www.teknisi-indonesia.com
+1.35VS_VRAM
10_0402_1%
PRW 19
PCW 20 10K_0402_1%
0.1U_0402_25V6 1 2
+3VALW
1 2
A A
SKL_H 42
5 4 3 2 1
D D
C C
PWR Reserve
B B
A A
0.1U_0402_16V7K
1
PC901
1
PR903
D 1M_0402_5% D
+3VS 1 2
@
Note:Iload(max)=3A
2
PR914 PU901
2
100K_0402_5%
9
@ 1 PGND 8
FB SGND
2 7 PL901
PJ901 PG EN 1UH_MLV-YT12N1R0M-C1L__4A_20%
+3VALW 1 2 3 6 LX_+1.8VS_DGPU1 2
1 2 IN LX SH00001NF00 +1.8VS_DGPUP
1
JUMP_43X39 4 5
68P_0402_50V8J
PGND NC
1
PC902 PR906
JUMP@
4.7_0603_5%
1
PR905
PC903
22U_0603_6.3V6M
1
200K_0402_1%
Rup
RF@
22U_0603_6.3V6M
22U_0603_6.3V6M
SY8003ADFC_DFN8_2X2
PC904
PC905
2
2
2
2
FB_+1.8VS_DGPU
1
1
FB=0.6V PR907
680P_0402_50V7K
Note:Iload(max)=3A Rdown
RF@ PC906
100K_0402_1%
2
C C
Vout=0.6V* (1+R1/R2)
=0.6*(1+(14/20)) PR908
0_0402_5%
2 1
+0.95VS_DGPU_ON 0.95VS_DGPU_EN <34>
0.1U_0402_16V7K
1
PC907
1
PR909
1M_0402_5% PJ902
+3VS 1 2 @
Note:Iload(max)=3A
2
PR915 PU902 1 2
2
+0.95VS_DGPUP 1 2 +0.95VS_S0
100K_0402_5%
9 JUMP_43X118
@ 1 PGND 8
FB SGND JUMP@
2 7 PL902
B PJ903 PG EN 1UH_MLV-YT12N1R0M-C1L__4A_20% B
+3VALW 1 2 3 6 LX_+0.95VS_DGPU
1 2
1 2 IN LX SH00001NF00 +0.95VS_DGPUP
1
1
JUMP_43X39 4 5
68P_0402_50V8J
PGND NC
1
JUMP@ PC908
4.7_0603_5%
1
PR912
PR911
PC909
22U_0603_6.3V6M
1
42.2K_0402_1%
Rup
RF@
22U_0603_6.3V6M
22U_0603_6.3V6M
SY8003ADFC_DFN8_2X2
PC910
PC911
P0_P1@ 2
2
2
2
FB_+0.95VS_DGPU
1
1
FB=0.6V PR913
680P_0402_50V7K
Note:Iload(max)=3A Rdown
RF@ PC912
PR912
G61@
48.7K_0402_1%
A A
D D
C C
PWR Reserve
B B
A A
D D
C C
PWR Reserve
B B
A A
D D
C C
PWR Reserve
B B
A A
D D
C C
PWR Reserve
B B
A A
D D
C C
PWR Reserve
B B
A A
D D
C C
PWR Reserve
B B
A A
D D
C C
PWR Reserve
B B
A A
D D
C C
PWR Reserve
B B
A A
D D
6 Change resistor for common design 85 PR2507 0.01 -> 0.005 ohm 2020/11/12 SDV
add PRV103 2k
Unmount PRV87 PRV88 PRV89 PRV1052 PRV1019 PRV1001 2020/11/12 SDV
7 PRV26 41.2K ->23.7K
C
PRV29 21.5K ->23.7K (P0P1) 32.4K (G61) C
11
Follow TI Spec design 85 PR350 PR351 1K-->0 ohm 2020/12/14 SIV
PC310 & PC9213 0.01u -> 0.1 u PQ311 Change P/N SIV
B
Change component for design 85
PC9207 Change 0603 -> 0402 (Sourcer recommend) 2020/11/23 B
18 Change component for design 110 PR912 42.2K ->48.7K (For G61 +1VS DGPUP) 2020/12/14 SIV
A A
19 Change Compoent for design 104 PRV62 PRV69 PRV76 Change P/N (Sourcer recommend) 2020/12/14 SIV
20
Change Compoent for design 101 PCG 45 & PCG47 Change P/N (Sourcer recommend) 2020/12/14 SIV
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-L161P
Date: Wednesday, March 10, 2021 Sheet 119 of 121
5 4 3 2 1
5 4 3 2 1
85
D
1 Modify circuit for design request pin13 compin > GND 2020/12/22 SIT D
C C
B B
A A
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR- PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, March 10, 2021 Sheet 120 of 121
5 4 3 2 1
5 4 3 2 1
D D
C C
PWR Reserve
B B
A A
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