REG2REG

Synthesis:
Synthesis transforms the simple RTL design into a gate-level netlist with all the
constraints as specified by the designer. In simple language, Synthesis is a process that
converts the abstract form of design to a properly implemented chip in terms of logic gates.

Synthesis flow:
1. Link_library

2. Target_library

3. Analyze

4. Elaborate

5. Compile

6. Start_gui

7. Check_design

8. Check_timing

9. Create_clock

10. Report_clock

11. Set_input_delay

12. Set_output_delay

13. Set_driving_cell

14. Set_load

15. Set_clock_uncertainty

16. Group_paths

17. Report_timing

18. Report_qor
1. Link_library:

In synopsys design compiler the link command is to search all the design loaded in the
dc_shell while trying to resolve refrence and is used to specify the location of the
technology library that is used to create a design reference.

Syntax: set link_library {*<path>}

2. Target_library:
The target library in Synopsys Design Compiler is the technology library libraries, I/O
libraries, and other technology specific files that are used to synthesize and optimize your
design. During synthesis, the Design Compiler uses the target library to determine the
optimal set of gates.

Syntax: set target_library {}

3. Analyze:
Analyze is a command in dc_shell used to analyze a Verilog design file, to read RTL
files and syntax checking happens here. When you run this command, Design compiler
analyses the input design file and creates a design data base that it can be used for synthesi

Syntax: analyze <options> <file>

4. Elobarate:

The elaborate command in Design Compiler is typically used after running the analyse
command to create a data base of cells and other design elements. Once the design is
elaborated, Design Compiler can perform various optimizations on the design, such as
mapping the design onto a target technology library, optimizing for power or area, and
performing timing analysis.
Syntax: elaborate
5. Compile:
In compile gives the optimized netlist, The mapping optimization reduces gates, area,
memory.
Syntax: compile or compile ultr

6. Start_gui:
Start_gui is a command used in Synopsys Design Compiler to launch its graphical
user interface from the command line interface. It allows user to perform various tasks
related to RTL synthesis and optimization in a move userfriendly manner. This
command generates a Verilog netlist file in the GTECH format, with hierarchy
information included, for a design that has been synthesized using Design Compiler.
Syntax: start_gui
7. Check_design:
It checks the current design for consistency and issues after the compile.
Syntax : check_design

8. Check_timing:
Gives the warnings when we have issues with sdc and compulsory after the
compile.
Syntax : check_timing

9. Create_clock:
The Create_clock command includes several parameters that define the
properties of the clock signal, including its frequency, waveform, jitter, and duty cycle.
Example: Create_clock -name gg -period 1 [get_ports clk]
Here, specifies the period of the clock, specifies a unique name for the clock,
specifies the waveform of the clock.
Syntax: create_clock -name -period

10. Report_clock:
This command displays information about the clocks, such as the clock period ,
the clock tree structure. The report can also help identify potential clock tree issues.
Syntax : report_clock
11. Set input delay:
The set_input_delay command is used to specify how much time is used by
external logic. Design Compiler the calculates how much time is left for the internal
logic. If you do not use this command the tool will assume an input port clock and pick
a clock period.
Syntax: set_input_delay -clock <port_list>

12. Set output_delay:

13. Set_clock_uncertainty:
By default, Design Compiler assumes that clock networks are ideal (no delays),
To change this behaviour, you need to use command set_clock_latency and
set_clock_uncertanity.
There are two types of uncertainty: Simple and inter clock.
Simple uncertainty means that setup uncertainty and hold uncertainty applies to all
paths to the endpoint.
Inter clock uncertainty allows you to specify different skew between various clock
domains.
The recommendation is to set the uncertainty to the worst skew expected to the endpoint
or between the clock domains.
Syntax: set_clock_uncertainty -setup Set_clock_uncertainty.
For Setup:

For Hold:

14. Set_driving_cell:
This constraint specifies the external drive strength of input port. By default, tool
assumes zero drive resistance on input ports, meaning infinite drive strength.
Alternatively, you can use set_drive and set_input_transition.
Syntax: set_driving_cell -lib_cell

The -no_design_rule switch indicates that the design rules associated with the
driving cell are not to be applied to the driven ports.

15. Set_load:
The load capacitance represents the combined capacitance that the output driver
of a circuit must drive, including the capacitance of the interconnects and the input
capacitance of the next stage in the design.

Syntax: set_load
16. Group_paths:
Path groups are automatically created when the create_clock or group_path
command is used. Path group allow you to specify specific paths or groups of paths
within your design that should be treated as a single unit during optimization or timing
analysis. This allows for more targeted optimizations and analysis, ensuring the desired
timing requirement are met.
Syntax: group_path -name -from -to

17. Report_timing:
The report_timing is useful tool for checking violations and timing of particular
paths. This command will analyze the timing paths in your design and generate a
detailed report displaying timing information for each path. The report will include
information such as: SLACK: The timing slack represents the amount of time a path
has before violating the specified timing constraints. Positive slack values indicate that
 the path is meeting timing requirement, while negative slack values indicate violations.
VIOLATIONS: If there are any setup or hold violations, the report will highlight those
paths and provide details about the violations. PATHS: The report will list the critical
timing paths in your design, including the path de
Syntax: report_timing

18. Report_qor:
This command will generate QoR report containing various optimization results
and statistics for your design. The QoR report typically includes information such as
area, utilization, power consumption, timing constraints, critical paths, and other
relevant optimization metrics.
Syntax: report_qor