Introduction to Silicon Process and VLSI

The CMOS Inverter

 Introduction
• The inverter is the simplest of all digital logic gates
• However, building an understanding of its properties and operation
is crucial for the design and analysis of larger/ more complex
logic gates.
• Once its operation and properties are clearly understood,
designing and analyzing more complex structures, such as NAND
gates, adders, multipliers and microprocessors is greatly
simplified.
• We will discuss:
• General properties of an inverter (and logic gates)
• Inverter implementation issues in CMOS technology.
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 General Properties
• Small area is a desirable property for a digital logic gate
• Larger packing density
• Small parasitic capacitances
• Shorter interconnects
• Smaller chip area, hence higher number of devices per wafer (lower
cost)
• Fewer transistors for a logic gate usually results into
smaller area.
• Hence, minimum possible number of transistors for a given gate is
important.

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 The CMOS Inverter: A First Glance
Complementary MOS Inverter
|VSG|= VDD
> VTp |VSG|= 0
<Vtp

VDD
0 0
VDD

VGS=VDD
VGS=0 >VTn
< VTn

VDD is my power supply value could 5 V, 1V according to technology

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 DC analysis
• Analyze DC Characteristics of CMOS Gates by studying an Inverter
• DC Analysis
• DC value of a signal in static conditions
• DC Analysis of CMOS Inverter
• Vin, input voltage
• Vout, output voltage
• single power supply, VDD
• Ground reference
• find Vout = f(Vin)
• Voltage Transfer Characteristic (VTC)
• plot of Vout as a function of Vin
• vary Vin from 0 to VDD
• find Vout at each value of Vin
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 CMOS inverter logic swing
• Output High Voltage, VOH
• maximum output voltage
• occurs when input is low (Vin = 0V)
• pMOS is ON, nMOS is OFF
• pMOS pulls Vout to VDD
• VOH = VDD
• Output Low Voltage, VOL
• minimum output voltage
• occurs when input is high (Vin = VDD)
• pMOS is OFF, nMOS is ON
• nMOS pulls Vout to Ground
• VOL = 0 V
• Logic Swing
• Max swing of output signal
This characteristic is non-trivial and is one of the advantages of
• V L = V OH – VOL
CMOS design. It is known as “Rail to Rail Swing”.
• V L = VDD

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 CMOS Inverter First-Order DC Analysis
V DD VOL = 0 V DD Properties
VOH = VDD 1) High and low outputs = VDD and Ground.
VM = f(Rn, Rp) Voltage swing= VDD. High Noise Margins.
Rp
2) Logic Levels are independent of device sizes (ratioless logic)

3) In steady state, a path exists from O/P to VDD or GND. Thus,

V out
V out low output impedance. Less sensitive to noise.

4) Input resistance is extremly high, since MOS

Rn gate draws no dc input current. Steady-state
input current ~ zero.

5) In steady-state, no direct path exists between supply and

ground rails. No static power (ignoring leakage)
V in 5 V DD V in 5 0

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 The Inverter’s VTC
• When Vin = 0 =⇒ Vout = VDD
• When Vin = VDD =⇒ Vout = 0
• In between, Vout depends on transistor size and
current
• By KCL, current must be such that Idsn = |Idsp|
• We could solve equations, but graphical solution gives
more insight

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 Inverter Voltage Transfer Characteristics
Since Vin and Vout are the input and output voltages of
VDD = 2.5V
the nMOS transistor, we will change the coordinates of
the pMOS. IDn V in = V DD +VGSp
IDn = - IDp
V out = VDD +VDSp

V out

IDp IDn IDn

Vin=0 Vin=0

Vin=1.5 Vin=1.5

V DSp V DSp Vout

VGSp=-1

VGSp=-2.5
Vin = V DD+VGSp Vout = V DD+VDSp
IDn = - IDp

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 CMOS Inverter Load Characteristics
Operating points or Vout must be where |currents| are equal in the graph below for the same Vin
Transcribe points on to Vin vs. Vout plot
ID n
Vin = 0 Vin = 2.5

PMOS Vin = 0.5 Vin = 2 NMOS

Vout
NMOS off
PMOS res

2.5
NMOS s at
PMOS res
Vin = 1 Vin = 1.5

2
Vin = 1.5 Vin = 1 NMOS sat

1.5
PMOS sat
Vin = 1.5 Vin = 1

1
Vin = 2 Vin = 0.5 NMOS res
PMOS sat NMOS res

0.5
Vin = 2.5 Vin = 0 PMOS off

0.5 1 1.5 2 2.5 Vin

2.5 Vout
Operating points are located either at the high or low output levels. The Voltage Transfer Characteristics (VTC) exhibit a very
narrow transition zone (high gain during switching transient – a small change in the input voltage results in a large output variation)

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 Operating Regions
• Let’s figure out what region of operation each transistor is in throughout the
VTCcurve.
When input voltage less than VT When input voltage more than
VDD-VT

NMOS Cutoff NMOS Linear

PMOS Linear PMOS Cutoff
* Considering Long Channel Transistors With VT<VDD/2
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 Operating Regions
• when the input voltage more • when the input voltage more
than VT than VT lower than VDD

NMOS Sat NMOS Linear

PMOS Linear PMOS Sat

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 Operating Regions
• In the middle area, where:

NMOS Sat
PMOS Sat

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 Operating Regions
• To Sum it up:
• Towards the rails, one of the
transistors is cut off, and the other is
resistive.
• Once the cut off transistor starts
conducting, it immediately is
saturated.
• As we approach the middle input
voltages, both transistors are
saturated.
• The VTC slope is known as the Gain
of the gate.

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CND121: INTRODUCTION TO SILICON PROCESS & VLSI 16
 Switching Threshold
• The Switching Threshold, VM, is the point where Vin=Vout.
• This can be calculated:
• »Graphically, at the intersection of the VTC with Vin=Vout
• Or analytically, by equating the nMOS and pMOS saturation currents with
Vin=Vout.

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CND121: INTRODUCTION TO SILICON PROCESS & VLSI 17
 Switching Threshold
• Let’s analytically compute VM.
• Remember, the saturation current for a MOSFET
is given by:

• Lets assume λ=0 and we’ll equate the two

currents:

• Now we’ll substitute:

• And we’ll arrive at:

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 Switching Threshold
• As we can see, r is an important factor in setting the switching
threshold.
• r is a design parameter, that is set by the drive strength ratios of
the nMOS and pMOS:

• Using the current equations again, we can find the drive strength
ratio for a desired VM:

k is process transconductance, mA/V2

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 Switching Threshold
• A symmetric VTC (VM=VDD/2) is often desired. In this case:

• When designing CMOS circuits, it is advisable to balance the strengths of the

transistors
• Generally, the same length (Lmin) is taken for all transistors
in digital circuits, and so for a symmetric VTC:

The mobility of PMOS is less than that of NMOS

(depends on holes)
Making PMOS wider than NMOS, to obtain large noise
margins + symmetrical characteristics

µn is the mobility of the electrons at the surface of the channel.

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CND121: INTRODUCTION TO SILICON PROCESS & VLSI 20
 Switching Threshold
• Increasing strength of NMOS
(sizing it up), moves VM closer
to GND. Vice versa for PMOS
case.
• VM is relatively insensitive to
variations in the device ratio.
• Small variations of the ratio (e.g.,
making it 3 or 2.5) do not disturb
the transfer characteristic that
much.

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 Noise Margins - Determining VIH and VIL
In real life applications, output voltage of a gate may not have the nominal value, owing to load, high
switching speed..etc.
Hence, it is desirable to define an acceptable voltage range for logic “1” and logic “0”
Vout

VOH

VM

Vin A simplified approach

VOL
VIL VIH

These expressions make it clear that a high gain in the transition region is very desirable. For infinite gain:
NMH=VDD-VM, NML=VM
Logic gates have the property to restore the proper output logic values despite of non-ideal input
levels.
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 Simulated inverter VTC
• VOH = VDD = 2.5V
• VOL = 0V
• VM = 1.2V
• VIL = 1.05V
• VIH = 1.45V
• NMH =1.05V
• NML = 1.05V

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 Simulated VTC - Inverter Gain
2.5 0

-2

2
-4

-6
1.5
Vout(V)

-8

gain
-10
1
-12

-14
0.5

-16

0 -18
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
V (V) V (V)
in in

NMOS and PMOS are in saturation. Equate

currents. Differentiate and solve for dVout/dVin
The gain is almost purely determined by
technology parameters, especially the
channel-length modulation.

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 Robustness- Impact of Process Variations
• Actual operating temperature might very over a large range. 2.5
• The device parameters after fabrication probably will deviate
from the nominal values we used in our design optimization
2
process Good PMOS
Bad NMOS
1.5
The dc-characteristics of the static CMOS inverter turn out to be

Vout(V)
Nominal
rather insensitive to these variations, and the gate remains
functional over a wide range of operating conditions
1
Good NMOS
Bad PMOS

This robust behavior, has contributed in a big way to the 0.5

popularity of the static CMOS gate.

0
0 0.5 1 1.5 2 2.5
Vin (V)

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 Scaling Supply effect on Gain
• The gain of the inverter actually increases with a reduction of VDD . At a VDD =0.5V, which is just 100mV
above VT of the transistors. So why can’t we operate all digital circuits at low VDD values?
• Yes, you get lower power consumption. But the delay of the gate drastically increases.
• DC characteristics become very sensitive to variations in device parameters such at VT once VDD and
intrinsic voltages become comparable.
• The signal swing is reduced. Although this is good for internal noise (crosstalk), this is bad for external noise
sources that do not scale.
2.5
0.2

2 Gain=-1
0.15

1.5
Vout(V)

Vout (V)
0.1
1

0.05
0.5

0 0
0 0.5 1 1.5 2 2.5 0 0.05 0.1 0.15 0.2
V (V) V (V)
in in
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Introduction to Silicon Process and VLSI
Propagation Delay
 Next
• Propagation delay
• Dynamic response
• Inverter Sizing
• Power Dissipation

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 CMOS Inverter First-Order DC Analysis
V DD VOL = 0 V DD Properties
VOH = VDD 1) High and low outputs = VDD and Ground.
VM = f(Rn, Rp) Voltage swing= VDD. High Noise Margins.
Rp
2) Logic Levels are independent of device sizes (ratioless logic)

3) In steady state, a path exists from O/P to VDD or GND. Thus,

V out
V out low output impedance. Less sensitive to noise.

4) Input resistance is extremly high, since MOS

Rn gate draws no dc input current. Steady-state
input current ~ zero.

5) In steady-state, no direct path exists between supply and

ground rails. No static power (ignoring leakage)
V in 5 V DD V in 5 0

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 CMOS Inverter: Transient Response
• Transient response is the response of a system to a change from an equilibrium or
a steady state.
• There is a delay here for this inverter circuit given an input voltage of low to high
the change in the logic from high to low the output voltage.

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 CMOS Inverter: Dynamic Behavior
The propagation delay of the CMOS
inverter is determined by the time it
takes to charge and discharge the
load capacitor CL through the PMOS
and NMOS transistors, respectively.

This observation suggests that

getting CL as small as possible is
crucial to the realization of high-
performance CMOS circuits.

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