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Advanced Analog Technology, Inc. January 2011

AUO-P301.30
Product information presented is current as of publication date. Details are subject to change without notice.

4-CHANNEL TFT LCD POWER SOLUTION

WITH ADJUSTABLE DELAY CONTROL
FEATURES GENERAL DESCRIPTION

9.5V to 14V Input Voltage Range The AUO-P301.30 is a 4-channel TFT LCD power

Built in 3.5A, 0.15Ω Switching NMOS for AVDD solution which provides a step-up PWM controller

Built in 2.5A, 0.25Ω Switching NMOS for VLogic (AVDD), a step-down PWM (VLogic), and two high

VGH Linear Regulator Up to 40V/50mA voltage Linear Regulators for VGH and VGL. By

VGL Linear Regulator Down to –14V/50mA controlling ENA and connecting two external capacitors
to DLY1, DLY2, the best power up sequencing of

Adjustable Power On Sequencing
AUO-P301.30 can be achieved GD is the open drain

750kHz Fixed Switching Frequency for VLogic
output signal which goes low when the VIN is larger than

Adjustable Switching Frequency 500k~2000kHz
UVLO. Connecting GD to an extra PMOS transistor can
for Boost
keep AVDD low before AVDD_F is ready. AUO-P301.30

GD Function for Driving External PMOS
also have protect mechanisms such as over voltage

WQFN28- 5mm*5mm Package Available protect (OVP), over current protect (OCP), output under
voltage protect (UVP) and thermal protect.
PIN CONFIGURATION With the minimal external components, the
AUO-P301.30 offers a simple and economical solution
for TFT LCD TV power solution.

– 台灣類比科技股份有限公司 –
– Advanced Analog Technology, Inc. –
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Advanced Analog Technology, Inc. January 2011

AUO-P301.30
ORDERING INFORMATION
DEVICE PART TEMP.
PACKAGE PACKING MARKING MARKING DESCRIPTION
TYPE NUMBER RANGE
1. Part Name
AUO-P30 Q20: –40
C to AUO-P301.30 2. Lot No.
AUO- T: Tape
1.30- WQFN28-5 XXXXXX (6~9 Digits)
P301.30 X5
and Reel +85
C
Q20-T XXXX 3. Date Code
(4 Digits)
Note: All AAT products are lead free and halogen free.

TYPICAL APPLICATION

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Advanced Analog Technology, Inc. January 2011

AUO-P301.30
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL VALUE UNIT

VIN, to GND VDD 16.5 V

VDC to GND VLV 7 V

SW, OS, GD to GND VH1 22 V

CBOOT to GND VH2 20 V

SWB to GND VH3 VH2 +0.3 V

OUTP to GND VH4 40 V

OUTN to GND VH5 –20 V

Input Voltage 1 (ENA1, ENA2) VI1 VDD +0.3 V

Input Voltage 2
VI3 VLV +0.3 V
(DLY1, IN1, INB, INN, INP, SS, DLY1, DLY2)
Output Voltage 2 (EOB, EO1, VSET, VREF, fsw ) VO2 –0.3 to (VLV +0.3) V

Operating Ambient Temperature Range TC –40 to +85

C
Operating Junction Temperature Range TJ –40 to +150

C
Storage Temperature Range TSTORAGE –65 to +150

C
Package Thermal Resistance θJA 34

C /W

Power Dissipation, @ TC = +25
C , TJ = +125
C Pd 2.941 W

Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended period of time may affect device reliability.

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Advanced Analog Technology, Inc. January 2011

AUO-P301.30
ELECTRICAL CHARACTERISTICS
(VIN = 9.5V to 14V, TC = –40 ° C to +85 ° C , unless otherwise specified. Typical values are tested at +25 ° C ambient
temperature, VIN = 12V, VDD1 = 15.7V.)

Operating Condition
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT
VIN Input Voltage Range VDD 9.5 - 14.0 V
OS Input Voltage Range VDD1 9.5 - 19.0 V
VIN1/INB = 1.5V,
- 2 5 mA
VIN Operating Current IVDD Not Switching
VIN1/INB = 1.0V, Switching - 6 10 mA
VIN Rising - 7.9 8.66 V
VIN Under Voltage Lockout VUVLO
VIN Falling 6.84 7.60 - V

Thermal Shutdown TSHDN - 160 -

C

Reference Voltage and Oscillator

PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT

Reference Voltage VREF IVREF = 100µA 1.23 1.25 1.27 V

Line Regulation IVREF = 100µA - 2 5 %/V

Load regulation IVREF = 0~100µA - 1 5 %/mA

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Advanced Analog Technology, Inc. January 2011

AUO-P301.30
ELECTRICAL CHARACTERISTICS
(VIN = 9.5V to 14V, TC = –40 ° C to +85 ° C , unless otherwise specified. Typical values are tested at +25 ° C ambient
temperature, VIN = 12V, VDD1 = 15.7V.)

Soft Start, Delay, Fault protect and Gate control Signal

PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT

Soft Start Source Current ISS VTHRESHOLD = 1.25V 6 9 12 µA

DLY1 Source Current IDLY1 VTHRESHOLD = 1.25V 3.6 5.0 6.4 µA

DLY2 Source Current IDLY2 VTHRESHOLD = 1.25V 3.6 5.0 6.4 µA

BUCK Soft Start Period TSSB1 - 1.5 3.0 mS

Gate On Voltage (VGH) Soft Start

TSSP - 8 16 mS
Period
Gate OFF Voltage (VGL) Soft
TSSN - 8 16 mS
Start Period
During Fault Protect Trigger Time TFP 180 200 220- mS
IN1 Fault Trigger Level VF1 1.02 1.08 1.12 V

INB Fault Trigger Level VFB1 1.02 1.08 1.12 V

INP Fault Trigger Level VFP 1.02 1.08 1.12 V

INN Fault Trigger Level VFN - 0.4 - V

GD Leakage Current IGD_leak VGD = 19.5V - - 1 µA

0.88* 0.92* 0.96*

GD Pull Down Threshold Voltage VGD_tri V
VDD1 VDD1 VDD1

GD Pull Down Low Voltage VGD_Low IGD=500µA - - 0.3 V

Logic Signal (ENA1, ENA2)

PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT

High Level Input Voltage VIH 1.75 - - V

Low Level Input Voltage IIL - - 0.75 V

Input Bias Current IIB VENA, FREQ = 0 to VIN –40 0 +40 nA

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Advanced Analog Technology, Inc. January 2011

AUO-P301.30
ELECTRICAL CHARACTERISTICS
(VIN = 9.5V to 14V, TC = –40 ° C to +85 ° C , unless otherwise specified. Typical values are tested at +25 ° C ambient
temperature, VIN = 12V, VDD1 = 15.7V.)

Oscillator
PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT

fOSC_Buck Fixed for Buck 600 750 900 kHz

Boost FSW = 50k 1,600 2,000 2,400 kHz

Boost FSW = 66.66k 1200 1,500 1,800 kHz

Oscillation Frequency
fOSC_Boost Boost FSW = 83k 960 1,200 1,440 kHz

Boost FSW = 133k 600 750 900 kHz

Boost FSW = 200k 400 500 600 kHz

Boost PWM 85 90 95 %
Maximum Duty Cycle DMAX
Buck PWM 85 90 95 %

Buck PWM (VLOGIC)

PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT

Output Voltage Range VLOGIC 1.8 - 5.0 V

Feedback Voltage VINB1 1.23 1.25 1.27 V

Input Bias Current IIBB1 VINB1 = 1V to 1.5V –40 0 +40 nA

Feedback-Voltage Line
- 0.05 0.15 %/V
Regulation

NMOS Current Limit ILIMB1 2.5 - - A

NMOS On-Resistance RONB1 ISWB = 1.0A - 0.25 - Ω

NMOS Leakage Current ISW1OFF VSWB = 0V - 0.01 5.00 µA

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Advanced Analog Technology, Inc. January 2011

AUO-P301.30
ELECTRICAL CHARACTERISTICS
(VIN = 9.5V to 14V, TC = –40 ° C to +85 ° C , unless otherwise specified. Typical values are tested at +25 ° C ambient
temperature, VIN = 12V, VDD1 = 15.7V.)

Boost PWM (AVDD)

PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT
Output Voltage Range AVDD - - 19 V

Rising - 20.5 21.5 V

AVDD Over Voltage Protect VOVP
Falling 18.5 19.5 - V

Feedback Voltage VIN1 1.23 1.25 1.27 V

Input Bias Current IIB1 VIN1 = 1V to 1.5V –40 0 +40 nA

Feedback-Voltage Line Regulation 9.5V < VIN < 12V - 0.05 0.15 %/V

NMOS Current Limit ILIM1 3.5- - - A

NMOS On-Resistance RON1 ISW = 1.0A - 0.15 - Ω

NMOS Leakage Current ISWOFF VSW = 19V - 0.01 5.00 µA

Negative Charge Pump Linear Regulator (VGL)

PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT

INN Feedback Voltage VINN 0.17 0.20 0.23 V

INN Input Bias Current IIBN VINN = –0.25V to 0.25V –40 0 +40 nA

OUTN Leakage Current IOFFN VINN = 0V, VOUTN = –6V - - –5 µA

OUTN Source Current IOUTN VINN = 0.35V, VOUT2 = –6V 8 10 - mA

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Advanced Analog Technology, Inc. January 2011

AUO-P301.30
ELECTRICAL CHARACTERISTICS
(VIN = 9.5V to 14V, TC = –40 ° C to +85 ° C , unless otherwise specified. Typical values are tested at +25 ° C ambient
temperature, VIN = 12V, VDD1 = 15.7V.)

Positive Charge Pump Linear Regulator (VGH)

PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT

INP Feedback Voltage VINP 1.23 1.25 1.27 V

INP Input Bias Current IIBP VINP = 1V to 1.5V –40 0 +40 nA

OUTP Leakage Current IOFF3 VINP = 1.4V, VOUTP = 34V - - 5 µA

OUTP Sink Current IOUT3 VINP = 1.1V, VOUTP = 25V 8 10 - mA

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Advanced Analog Technology, Inc. January 2011

AUO-P301.30
PIN DESCRIPTION
PIN NO.
NAME I/O DESCRIPTION
WQFN28
1 OS - Step-up PWM Output Sensing Pin

2 GND - IC Ground

3 IN1 I Step-up PWM Feedback Input

4 GD O Gate Driver for External Fault Protect PMOS

5 EO1 O Step-up PWM Error Amplifier Output Pin

6 SS I Step-Up PWM Soft Start Control

7 VREF O Reference Voltage Output

8 INN I VGL LDO Controller Feedback Input

9 OUTN O VGL LDO Controller Output

10 VDC O Internal LDO Output Pin

11 DLY2 I Power up Delay between ENA1 and VGH

12 CBOOT O Gate Driver Voltage for Step-down PWM Power MOS

13 SWB O Step-down PWM Power MOS Switching Pin

14 SWB O Step-down PWM Power MOS Switching Pin

15 VIN - Power Input

16 VIN - Power Input

17 INB I Step-down PWM Feedback Input

18 EOB O Step-down PWM Error Amplifier Output Pin

19 DLY1 I Power up Delay between ENA1 and GD

20 FSW O Step-up PWM Switching Frequency Select Pin

21 INP I VGH LDO Controller Feedback Input

22 OUTP O VGH LDO Controller Output

23 ENA1 I Step-up PWM Enable Pin (When ENA2 is High)

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Advanced Analog Technology, Inc. January 2011

AUO-P301.30
PIN DESCRIPTION
PIN NO.
NAME I/O DESCRIPTION
WQFN28
24 ENA2 I Step-down PWM Enable Pin

25 GND1 - Step-up PWM Power MOS Ground

26 GND1 - Step-up PWM Power MOS Ground

27 SW O Step-up PWM Power MOS Switching Pin

28 SW O Step-up PWM Power MOS Switching Pin

FUNCTION BLOCK DIAGRAM

AUO-P301.30

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Advanced Analog Technology, Inc. January 2011

AUO-P301.30
TYPICAL APPLICATION CIRCUIT

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Advanced Analog Technology, Inc. January 2011

AUO-P301.30
TIMING WAVEFORM
UVLO=7.9V UVLO=7.6V
VIN

VREF

T2 0
ENA2

TSSB
Vlogic

T1 0
ENA1
VGL
TSSN

Vref = 1.25V

SS
SS>IN1

IN1
VIN VIN

SW

TSS
VIN VIN
AVDD_F

DLY1
VIN VIN
GD

TSS_RC
AVDD

DLY2

TSSP
VGH

Note 1. T1 T2 ≧
Note 2. ENA1 enable VGL and boost converter, ENA2 enable buck converter
Note 3. DLY1 set delay time between ENA1 and GD, DLY2 set delay time between ENA1 and VGH

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Advanced Analog Technology, Inc. January 2011

AUO-P301.30
PACKAGE DIMENSION
WQFN28-5X5

Dimensions In Millimeters
Symbol
MIN TYP MAX
A 0.70 0.75 0.80
A1 0.00 0.02 0.05
b 0.18 0.25 0.30
C 0.19 0.20 0.25
D 4.95 5.00 5.05
D2 3.60 3.65 3.70
E 4.95 5.00 5.05
E2 3.60 3.65 3.70
e ----- 0.50 -----
L 0.35 0.40 0.45

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