MODULE 5: Sequential Circuits (8L +6P=14)

Flip flops – SR, JK, T, D, Master/Slave FF – operation and excitation tables, Triggering of FF, Analysis and design of
clocked sequential circuits – Design – Moore/Mealy models, state minimization, state assignment, circuit
implementation – Design of Counters- Ripple Counters, Ring Counters, Shift registers.
Self-Study / Practical Component: To be done in Simulation environment
1. Design and simulation of Flip Flops
2. Design and simulation of Counters
3. Design and simulation of shift registers

Sequential circuits are digital circuits that utilize memory elements such as flip-flops to store
and process information sequentially over time. These circuits maintain state information,
allowing them to perform tasks based not only on current inputs but also on previous states.
Sequential circuits are classified into two main types:

• synchronous
• asynchronous.

Designing and analysing sequential circuits involve understanding the behaviour of memory
elements (flip-flops), defining state variables and state transitions, and implementing
combinational logic to control the circuit's operation. Sequential circuits play a crucial role in
digital system design and are essential for implementing complex functionality and
processing tasks.
Synchronous Sequential Circuits:

1. In synchronous sequential circuits, the state transitions are controlled by a clock

signal that ensures all memory elements (flip-flops) change state simultaneously.
2. The clock signal is used to synchronize the operation of the entire circuit, allowing for
predictable timing behavior and easier analysis and design.
3. Synchronous sequential circuits typically use flip-flops with well-defined setup and
hold times to latch input data and ensure reliable operation.

Asynchronous Sequential Circuits:

1. In asynchronous sequential circuits, the state transitions occur independently of a

clock signal, based on the inputs and the current state of the circuit.
2. Asynchronous sequential circuits are more complex to design and analyze compared
to synchronous circuits, as timing considerations and race conditions must be
carefully managed.
3. These circuits are often used in applications where precise timing is not critical, or
when the system requires fast response times.

Sequential circuits are widely used in various digital systems and applications, including:

• Counters: Sequential circuits that generate a sequence of output states in response to

clock pulses. They are used for tasks such as counting, timing, and frequency
division.
• Registers: Sequential circuits used to store binary data temporarily. Registers are
commonly used for data storage, transfer, and manipulation in digital systems.
• State Machines: Sequential circuits that transition between different states based on
inputs and current states. State machines are used for control and decision-making
tasks in digital systems, such as finite state machines (FSMs) and state diagrams.
• Shift Registers: Sequential circuits used for serial-to-parallel or parallel-to-serial data
conversion. They are used in applications such as data communication, storage, and
signal processing.

Flip-flops

Flip-flops are fundamental building blocks in digital electronics used for storing binary
information. A Flip-Flop is a digital logic circuit that mainly forms 1-bit data storage. It is
also a bistable multivibrator as it has two stable states "0" or "1". Developers can usually
form a Flip-Flop by combining NAND and NOR circuits with a clocking source or, simply
get a pre-built Flip-Flop on ICs from electronics store locally or from an online electronic
components' distributor. "Latches" are similar components to Flip-Flops, but the main
difference is their clocking mechanism. Flip-Flops are controlled by a clock source and the
inputs only affect the clock edge. While in latches, any change in inputs affects the output
immediately. Flip-Flops tend to have many different applications such as building counters,
shift registers, frequency dividers, and more.

They come in various types, including

• SR (Set-Reset),
• JK,
 • T, and
• D flip-flops

Each of these has its own unique characteristics and applications. Additionally, master/slave
flip-flops are used to improve the performance and reliability of sequential circuits. Let's
discuss each of these concepts:

SR Flip-Flop (Set-Reset Flip-Flop):

• The RS flip-flop, also called the Reset-Set flip-flop, is the simplest type of flip-flop.
• It is known as a direct-coupled or latched flip-flop due to its basic design.
• This flip-flop has two stable states, akin to a toggle switch, where it can be either ON
or OFF.
• It retains its current state until its inputs change, which forcefully alters its state.
• This characteristic is termed as a latch, earning the RS flip-flop the nickname "latch
flip-flop."
• It has two inputs, R (Reset) and S (Set), where setting the S input stores a binary 1, and
resetting with the R input stores a binary 0.
• When logic signals are applied to the inputs, the flip-flop changes its state accordingly.
• The RS flip-flop also has two outputs, Q and Q (Q bar), representing the normal output
and its complement, respectively.
• Both outputs are complementary to each other, meaning when one is high, the other is
low, and vice versa.
 o

JK Flip-Flop:

• The JK flip-flop has two inputs: J (J-input) and K (K-input), and two outputs: Q and Q'.
• The JK flip-flop has a toggle capability, meaning it can change its output state based on
the input and the current state.
• Excitation Table:
T Flip-Flop:

• The T flip-flop has a single input: T (Toggle) and two outputs: Q and Q'.
• The T flip-flop toggles its output state when the T input is high.
• Excitation Table:

D Flip-Flop:

• The D flip-flop (Data flip-flop) has a single input: D (Data) and two outputs: Q and
Q'.
• The D flip-flop stores the value of the D input on the rising edge of the clock signal.
• Excitation Table:
 4. Master/Slave Flip-Flop:

o The master/slave flip-flop consists of two flip-flops connected in series, with

the output of the master flip-flop feeding into the input of the slave flip-flop.
o This configuration prevents glitches and ensures proper synchronization
between the input and output signals.

Flip-flops are triggered by a clock signal, which determines when the flip-flop should read
the input and change its state. Analysis and design of clocked sequential circuits involve
designing circuits that use flip-flops and combinational logic to perform specific functions
based on a clock signal.

Understanding the operation and characteristics of flip-flops is essential for designing and
analyzing sequential circuits in digital systems, such as counters, registers, and state
machines.

Moore and Mealy models

Moore and Mealy models are two common types of finite state machines (FSMs) used in
digital design and sequential circuit analysis. Both models represent systems that transition
between different states based on inputs, but they differ in how they produce outputs.
 1. Moore Model:
o In the Moore model, the outputs are associated with the states of the machine.
This means that the output is determined solely by the current state of the
machine and does not depend on the inputs.
o Each state in a Moore machine has a unique output associated with it, and this
output remains constant for the duration of the state.
o Moore machines are easier to design and analyze compared to Mealy
machines because the outputs are purely a function of the current state,
simplifying the state transition and output generation process.
o However, Moore machines may require more states to achieve certain output
behavior, leading to larger state diagrams and potentially more complex
designs.
2. Mealy Model:
o In the Mealy model, the outputs are associated with transitions between states,
which means that the outputs depend on both the current state and the inputs.
o The output of a Mealy machine can change with each input, allowing for more
flexible and efficient designs compared to Moore machines.
o Mealy machines often require fewer states to achieve the same functionality as
Moore machines, resulting in smaller and more efficient designs.
o However, Mealy machines can be more complex to design and analyze due to
the dependency of outputs on both the current state and inputs, which may
introduce additional timing considerations and potential hazards.

Applications of Moore and Mealy Models:

• Moore machines are commonly used in applications where the output behavior is
primarily determined by the current state, such as control circuits and sequence
detectors.
• Mealy machines are often used in applications where the output behavior depends on
both the current state and inputs, such as data processing and communication systems.

State minimization, also known as state reduction or state optimization, is a process used in
digital design to reduce the number of states in a finite state machine (FSM) while preserving
its functionality. The goal of state minimization is to simplify the design, reduce hardware
complexity, and improve performance without altering the behavior of the FSM.

State minimization plays a crucial role in digital design, especially in complex sequential
circuits and finite state machines. By reducing the number of states, state minimization
simplifies the design, reduces hardware complexity, minimizes power consumption, and
improves the overall efficiency of digital systems. It is an essential optimization technique
used in various applications, including control systems, communication protocols, data
processing, and digital signal processing.

The state minimization process typically involves the following steps:

1. State Assignment:
 o Assign unique binary codes to each state in the original FSM.
o This step establishes a consistent representation of the states, which is
essential for the subsequent analysis and optimization.
2. State Reduction Techniques:
o There are several techniques used for state reduction, including:
▪ State Elimination: Identify and eliminate redundant or unreachable
states from the FSM.
▪ Equivalent State Identification: Identify states that produce identical
output sequences for all input sequences and merge them into a single
state.
▪ Implication Table: Construct an implication table to determine the
relationships between states and identify equivalent state pairs.
▪ Partitioning Methods: Partition the states into groups based on their
input-output behavior and merge equivalent states within each group.
▪ Algorithmic Methods: Utilize algorithms such as the partitioning
method, covering method, or table-filling method to systematically
identify and merge equivalent states.
3. Verification:
o Verify that the minimized FSM preserves the functionality of the original
FSM by simulating its operation with various input sequences.
o Ensure that the minimized FSM produces the same output sequences for all
input sequences as the original FSM.
4. Implementation:
o Implement the minimized FSM using flip-flops, combinational logic, and
control logic circuits based on the optimized state diagram.
o Verify the functionality and performance of the implemented FSM through
simulation and testing.

State Assignment:

State assignment is the process of assigning unique binary codes to each state in a finite state
machine (FSM). It is a crucial step in the design of digital circuits, particularly counters and
sequential circuits. The goal of state assignment is to ensure that each state in the FSM has a
distinct binary representation, facilitating efficient circuit implementation and operation.

1. Binary Encoding:
o The most common method of state assignment is binary encoding, where each
state is represented by a unique binary code.
o The number of bits required for encoding depends on the number of states in
the FSM. For N states, ⌈log₂(N)⌉ bits are needed.
o Binary encoding ensures that each state has a unique binary representation,
simplifying circuit design and analysis.
2. Gray Encoding:
o Gray encoding is an alternative state assignment method where adjacent states
differ by only one bit.
o Gray encoding is particularly useful in applications where state transitions
must be glitch-free or when interfacing with asynchronous systems.
Circuit Implementation - Design of Counters:

Counters are sequential circuits that generate a sequence of binary numbers in response to
clock pulses. They are widely used in digital systems for counting, timing, and frequency
division. Common types of counters include ripple counters, ring counters, and shift registers.

1. Ripple Counters:
o Ripple counters are asynchronous counters where the output of each flip-flop
serves as the clock input for the next flip-flop in the sequence.
o The propagation delay of each flip-flop causes a ripple effect, resulting in a
delay between the generation of each count.
o While simple to design and implement, ripple counters suffer from
propagation delay issues, limiting their maximum operating frequency.
2. Ring Counters:
o Ring counters are shift register-based counters where the output of each flip-
flop is connected to the input of the next flip-flop in a circular fashion,
forming a ring topology.
o Ring counters generate a sequence of states that circulate through the flip-
flops, with only one flip-flop active (high output) at any given time.
o Ring counters offer faster operation compared to ripple counters but require
more complex circuitry.
3. Shift Registers:
o Shift registers are serial-in/serial-out or parallel-in/serial-out sequential
circuits that shift data through a series of flip-flops.
o Shift registers can be configured as counters by connecting feedback paths to
implement counting logic.
o Shift registers offer flexible operation and can be used for various applications
beyond simple counting.

The design and implementation of counters involve selecting the appropriate counter type
based on requirements such as speed, complexity, and functionality. State assignment plays a
crucial role in ensuring that the counter operates correctly and efficiently.

Counters:

Counters are fundamental digital circuits used to count the occurrence of input events or
pulses. They are widely employed in various applications such as frequency division, timing,
sequencing, addressing, and control. Counters can be implemented using flip-flops due to
their ability to store binary states and transition between states in response to clock signals.

Here's how counters are typically implemented using flip-flops:

4. Binary Counters:
o Binary counters are the most common type of counters and are constructed
using flip-flops. Each flip-flop represents a binary digit (bit) of the count value.
o The output of each flip-flop is connected to the clock input of the next flip-flop
in the sequence, creating a ripple effect where each flip-flop toggles its state in
response to the clock signal.
o The initial count value is loaded into the flip-flops, and with each clock pulse,
the counter increments by one in binary fashion (000, 001, 010, 011, 100, etc.).
 o Binary counters can be synchronous, where all flip-flops are clocked
simultaneously by a common clock signal, or asynchronous, where each flip-
flop is clocked by the output of the previous flip-flop.
5. Decade Counters:
o Decade counters are specialized binary counters that count in decimal digits
(0-9). They are typically constructed using flip-flops and additional logic to reset
the count when it reaches 10.
o Decade counters can be implemented using binary-coded decimal (BCD) or
straight binary configurations.
o When the count value reaches 9, additional logic detects this condition and
triggers the reset of the count value back to 0 while incrementing a higher-order
digit if needed.
6. Up/Down Counters:
o Up/down counters are versatile counters that can count both upwards and
downwards. They use flip-flops to store the count value and additional control
logic to determine the counting direction.
o When counting up, the flip-flops transition in the normal binary sequence (e.g.,
000, 001, 010, etc.). When counting down, the flip-flops transition in the reverse
sequence (e.g., 111, 110, 101, etc.).
o Up/down counters are commonly used in applications such as digital clocks,
timers, and motor control systems.
7. Other Types of Counters:
o There are various other types of counters, such as ring counters, Johnson
counters, asynchronous counters, and synchronous counters, all of which can
be implemented using flip-flops in different configurations.

Synchronous and asynchronous counters

Synchronous and asynchronous counters are both types of digital counters used to count
input pulses or events. However, they differ significantly in their operation, timing, and
implementation:

Synchronous Counters:

1. Clock Synchronization: In synchronous counters, all flip-flops within the counter are
clocked simultaneously by a common clock signal. This ensures that all flip-flops
change state at the same time, maintaining synchronization.
2. Parallel Loading: Synchronous counters typically support parallel loading of initial
values. This means that the initial count value can be loaded simultaneously into all
flip-flops, allowing for easy presetting of the counter.
3. Propagation Delay: Synchronous counters have consistent propagation delays for all
stages since they are all clocked by the same clock signal. This simplifies timing
analysis and ensures uniform performance across all stages.
4. Modularity: Synchronous counters are modular in design, making them suitable for
integration into larger synchronous systems. They can easily interface with other
synchronous components without additional timing considerations.
5. Complexity: Implementing synchronous counters can be more complex compared to
asynchronous counters due to the requirement for a common clock signal and
additional control logic to ensure synchronous operation.
Asynchronous Counters:

1. Clock Independence: In asynchronous counters, each flip-flop is clocked by the

output of the previous flip-flop, creating a ripple effect. As a result, there is no common
clock signal, and flip-flops operate independently of each other with respect to timing.
2. Sequential Loading: Asynchronous counters do not support parallel loading of initial
values. The initial count value propagates sequentially through the flip-flops based on
the clocking of the previous stage.
3. Propagation Delay Variation: Asynchronous counters exhibit variable propagation
delays across stages due to the ripple effect. The delay increases with each additional
stage, leading to potential timing skew issues.
4. Modularity Challenges: Asynchronous counters may pose challenges when
integrating into larger systems, especially if timing requirements need to be met across
 multiple asynchronous components. Timing analysis becomes more complex due to
variable propagation delays.
5. Simplicity: Asynchronous counters are generally simpler to implement compared to
synchronous counters since they do not require a common clock signal and associated
control logic for synchronization.

In summary, synchronous counters offer synchronous operation, consistent timing, and

modular design but are more complex to implement. Asynchronous counters, on the other
hand, provide simplicity in design but may suffer from variable propagation delays and lack
of synchronization. The choice between the two types depends on the specific requirements
of the application, including timing constraints, modularity needs, and complexity
considerations.

Shift registers

Shift registers are sequential logic circuits that are widely used in digital electronics for
various purposes, such as data storage, data transfer, serial-to-parallel or parallel-to-serial
conversion, and signal processing. They are composed of flip-flops, which store binary data,
and shift logic, which controls the movement of data within the register.

The operation of shift registers can be understood based on the type of register and the
direction of data movement:

1. Serial-in Serial-out (SISO):

o In a SISO shift register, data is shifted in serially from one end and shifted out
serially from the other end.
o The input data is usually applied to the serial input (SI) line.
o With each clock pulse, the data stored in each flip-flop is shifted to the next flip-
flop in the register.
 o The last bit in the register (at the serial output, SO) can be read or used for
further processing.

o
2. Serial-in Parallel-out (SIPO):
o SIPO shift registers accept serial data input and provide parallel data output.
o The input data is shifted in serially, similar to SISO registers.
o However, the output data is available simultaneously on multiple parallel output
lines after shifting in all the bits.

3. Parallel-in Serial-out (PISO):

o PISO shift registers accept parallel data input and provide serial data output.
o All the input data bits are loaded simultaneously into the flip-flops.
o With each clock pulse, the data from each flip-flop is shifted out serially.

4. Parallel-in Parallel-out (PIPO):

o PIPO shift registers allow parallel loading of data and parallel retrieval of data.
o All the input data bits are loaded simultaneously into the flip-flops.
o The stored data can be read from the parallel outputs simultaneously.
The operation of shift registers is synchronized by a clock signal. Each clock pulse triggers
the shift logic to move the data within the register according to the desired shift direction.
Additionally, some shift registers may incorporate additional control inputs for features such
as clearing the register, enabling/disabling shifting, or implementing special functions like
data rotation.

Shift registers find applications in various digital systems, including serial communication
interfaces (UART, SPI), data storage, memory devices, arithmetic and logic units, and signal
processing circuits. Their versatility and ability to efficiently handle serial and parallel data
make them fundamental building blocks in digital circuit design.

Design considerations for shift registers Shift registers

Shift registers are crucial components in digital circuit design, used for serial-to-parallel or
parallel-to-serial data conversion. When analyzing their design considerations, several
factors come into play:

1. Type of Shift Register: There are different types of shift registers, including Serial-in
Serial-out (SISO), Serial-in Parallel-out (SIPO), Parallel-in Serial-out (PISO), and
Parallel-in Parallel-out (PIPO). The choice depends on the specific application
requirements. For instance, SISO registers are suitable for applications like serial data
transmission, while PIPO registers are used for parallel data storage.
2. Clocking Mechanism: Shift registers typically operate based on a clock signal. The
clocking mechanism determines when data is shifted into or out of the register. Design
considerations include clock frequency, duty cycle, and synchronization with other
components in the system to ensure proper data transfer timing.
3. Data Width: The number of bits the shift register can handle at a time is critical. It
determines the parallel data width or the length of the serial shift chain. The data width
is chosen based on the size of the data being processed and the system requirements.
 4. Storage Technology: Shift registers can be implemented using various storage
technologies such as D flip-flops, JK flip-flops, or SR latches. The choice depends on
factors like speed, power consumption, area constraints, and design complexity.
5. Feedback Mechanisms (for Serial-in Serial-out): Some shift registers incorporate
feedback mechanisms to implement functions like data rotation or serial data
manipulation. These mechanisms, such as using XOR gates to introduce feedback,
need careful consideration to ensure proper functionality and stability.
6. Cascadeability: In some applications, multiple shift registers may need to be
cascaded to achieve the desired data width or functionality. Design considerations
include ensuring compatibility between cascade stages, minimizing propagation
delays, and maintaining signal integrity.
7. Power Consumption: Power consumption is a critical consideration, especially in
portable or battery-operated devices. Design choices such as using low-power
components, optimizing clocking schemes, and minimizing unnecessary switching
activity help reduce power consumption.
8. Noise Immunity and Signal Integrity: Shift registers are susceptible to noise and
signal integrity issues, especially in high-speed or noisy environments. Design
considerations include proper shielding, signal conditioning, and error
detection/correction mechanisms to ensure reliable operation.
9. Testability: Shift register designs should incorporate features to facilitate testing and
debugging, such as built-in self-test (BIST) capabilities, scan chains, or diagnostic
outputs.
10. Cost and Area Constraints: Design choices should also consider cost and area
constraints. Optimal utilization of resources, integration of multiple functions into a
single device, and use of cost-effective manufacturing processes contribute to cost-
effective designs.

Overall, designing shift registers requires balancing various considerations such as

functionality, performance, power consumption, reliability, and cost to meet the specific
requirements of the target application.

shift registers in serial data transmission

1. Efficient Data Transmission: Shift registers allow for efficient serial data transmission
by converting parallel data into serial form. This reduces the number of physical
connections needed between transmitting and receiving devices, leading to simpler
and more cost-effective communication interfaces.
2. Synchronization: Shift registers can be synchronized with a clock signal, ensuring
that data is transmitted and received at the correct timing intervals. This helps maintain
data integrity and reliability, especially in high-speed communication systems.
3. Flexibility: Shift registers provide flexibility in data format and length. They can
accommodate varying data widths and lengths, making them suitable for a wide range
of applications. Additionally, shift registers can handle both serial-in and serial-out
data, allowing bidirectional communication if needed.
4. Serial-to-Parallel Conversion: Shift registers can also perform serial-to-parallel
conversion, allowing serially transmitted data to be parallelized at the receiving end.
This is useful for interfacing with parallel data processing systems or peripherals.
5. Data Buffering: Shift registers can act as data buffers, storing incoming data
temporarily before it is processed or transmitted further. This helps smooth out
variations in data rates and provides additional time for data processing.
Cascading shift registers is a technique used to increase the length of the data sequence
that can be transmitted or processed. This involves connecting multiple shift registers in
series, with the output of one register connected to the input of the next. Here's how it works:

1. Serial Cascading:
o In serial cascading, the output (serial output, SO) of one shift register is
connected to the input (serial input, SI) of the next shift register.
o As data is shifted out of the first register, it is serially inputted into the next
register, effectively extending the length of the data sequence that can be
transmitted or processed.
o The number of shift registers cascaded determines the total length of the data
sequence that can be accommodated.
2. Parallel Cascading:
o In parallel cascading, the parallel outputs of multiple shift registers are
connected together to form a wider data bus.
o This allows for the parallel concatenation of data from multiple shift registers,
increasing the total data width that can be processed in parallel.
o Parallel cascading is often used when dealing with large data widths or when
interfacing with parallel processing systems.
By cascading shift registers, designers can achieve greater flexibility and scalability in serial
data transmission applications, accommodating longer data sequences and larger data
widths as needed. This technique is commonly used in serial communication interfaces such
as SPI (Serial Peripheral Interface) and shift register-based data storage systems.