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Gate Questions

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6 views4 pages

Gate Questions

Uploaded by

harshwardhanzade11
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Gate Questions

1)In a k-way set associative cache, the cache is divided into v sets, each of which consists
of k lines. The lines of a set are placed in sequence one after another. The lines in set s are
sequenced before the lines in set (s+1). The main memory blocks are numbered 0 onwards.
The main memory block numbered j must be mapped to any one of the cache lines from.
(A) (j mod v) * k to (j mod v) * k + (k-1)
(B) (j mod v) to (j mod v) + (k-1)
(C) (j mod k) to (j mod k) + (v-1)
(D) (j mod k) * v to (j mod k) * v + (v-1)

Answer: (A)

Explanation: Number of sets in cache = v. So, main memory block j will be mapped to set
(j mod v), which will be any one of the cache lines from (j mod v) * k to (j mod v) * k + (k-1).
(Associativity plays no role in mapping- k-way associativity means there are k spaces for a
block and hence reduces the chances of replacement.)

2) Consider the following sequence of micro-operations.

MBR ← PC

MAR ← X
PC ← Y

Memory ← MBR

Which one of the following is a possible operation performed by this sequence?


(A) Instruction fetch
(B) Operand fetch
(C) Conditional branch
(D) Initiation of interrupt service

Answer: (D)

Explanation: MBR – Memory Buffer Register ( that stores the data being transferred to
and from the immediate access store)
MAR – Memory Address Register ( that holds the memory location of data that needs to
be accessed.)
PC – Program Counter ( It contains the address of the instruction being executed at the
current time )
The 1st instruction places the value of PC into MBR

3) Consider an instruction pipeline with five stages without any branch prediction: Fetch
Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI)
and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10
ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage
and the delay of each buffer is 1 ns. A
program consisting of 12 instructions I1, I2, I3, …, I12 is executed in this pipelined
processor. Instruction I4 is the only branch instruction and its branch target is I9. If the
branch is taken during the execution of this program, the time (in ns) needed to
complete the program is
(A) 132
(B) 165
(C) 176
(D) 328

Answer: (B)

Explanation:
Pipeline will have to be stalled till Ei stage of l4 completes,
as Ei stage will tell whether to take branch or not.

After that l4(WO) and l9(Fi) can go in parallel and later the

following instructions.
So, till l4(Ei) completes : 7 cycles * (10 + 1 ) ns = 77ns
From l4(WO) or l9(Fi) to l12(WO) : 8 cycles * (10 + 1)ns = 88ns

Total = 77 + 88 = 165 ns

4) A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 ×
4 decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is
(A) 4
(B) 5
(C) 6
(D) 7

Answer: (B)
Explanation:
RAM chip size = 1k ×8[1024 words of 8 bits each]
RAM to construct =16k ×16

Number of chips required = (16k x 16)/ ( 1k x 8)


= (16 x 2)
[16 chips vertically with each having 2 chips

horizontally]
So to select one chip out of 16 vertical chips,
we need 4 x 16 decoder.

Available decoder is 2 x 4 decoder


To be constructed is 4 x 16 decoder

Hence 4 + 1 = 5 decoders are required.

5) The following code segment is executed on a processor which allows only register
operands in its instructions. Each instruction can have atmost two source operands and
one destination operand. Assume that all variables are dead after this code segment.

c = a + b;
d = c * a;

e = c + a;
x = c * c;

if (x > a) {

y = a * a;
}

else {
d = d * d;

e = e * e;

Suppose the instruction set architecture of the processor has only two registers. The
only allowed compiler optimization is code motion, which moves statements from one
place to another while preserving correctness. What is the minimum number of spills to
memory in the compiled code?
(A) 0
(B) 1
(C) 2
(D) 3

Answer: (B)

Explanation:
r1......r2
a.......b......c = a + b

a.......c......x = c * c

a.......x......but we will have to store c in mem as we don't know if x > a


................. or not

y.......x......y = a * a

choosing the best case of x > a , min spills = 1

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