M95M01-125

Automotive 1-Mbit serial SPI bus EEPROM

Datasheet − production data

Features
■ Compatible with the Serial Peripheral Interface
(SPI) bus
■ Memory array
– 1 Mb (128 Kbytes) of EEPROM SO8 (MN)
– Page size: 256 bytes 150 mil width
■ Write
– Byte Write within 5 ms
– Page Write within 5 ms
■ Write Protect: quarter, half or whole memory
array
■ High-speed clock: 5 MHz
■ Single supply voltage:
– 2.5 V to 5.5 V
■ Operating temperature range: from -40°C up to
+125°C
■ Enhanced ESD protection
■ More than 1 million Write cycles
■ More than 40-year data retention
■ Packages
– RoHS compliant and halogen-free
(ECOPACK®)

June 2012 Doc ID 023153 Rev 1 1/37

This is information on a product in full production. www.st.com 1
Contents M95M01-125

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.1 Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.3 Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.4 Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.5 Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.6 Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.7 VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.8 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Connecting to the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.1 SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1 Supply voltage (VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.1 Operating supply voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.2 Device reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.3 Power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Active Power and Standby Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.4 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.5 Data protection and protocol control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6.1 Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.2 Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.1 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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M95M01-125 Contents

6.3.2 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.3.3 BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.4 SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4 Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.5 Read from Memory Array (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.6 Write to Memory Array (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.6.1 Cycling with Error Correction Code (ECC) . . . . . . . . . . . . . . . . . . . . . . 25

7 Power-up and delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

7.1 Power-up state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

9 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

10 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

11 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Doc ID 023153 Rev 1 3/37

List of tables M95M01-125

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Write-protected block size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 3. Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 4. Address range bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 5. Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6. Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8. Operating conditions (M95M01-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 9. AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 11. Memory cell characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 12. DC characteristics (M95M01-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 13. AC characteristics (M95M01-W, device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 14. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data . . . . . . . . . . . 34
Table 15. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 16. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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M95M01-125 List of figures

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 2. 8-pin package connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Write Enable (WREN) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 8. Write Disable (WRDI) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 9. Read Status Register (RDSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 10. Write Status Register (WRSR) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11. Read from Memory Array (READ) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Byte Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Page Write (WRITE) sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 15. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 16. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 17. Serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 18. SO8N – 8-lead plastic small outline, 150 mils body width, package outline . . . . . . . . . . . . 34

Doc ID 023153 Rev 1 5/37

Description M95M01-125

1 Description

The M95M01 devices are Electrically Erasable PROgrammable Memories (EEPROMs)

organized as 131072 x 8 bits, accessed through the SPI bus.
The M95M01 devices can operate with a supply range from 2.5 V up to 5.5 V, and are
guaranteed over the -40 °C/+125 °C temperature range. They are compliant with the
Automotive standard AEC-Q100 Grade 1.

Figure 1. Logic diagram

VCC

D Q

S M95xxx

HOLD

VSS
AI01789C

The SPI bus signals are C, D and Q, as shown in Figure 1 and Table 1. The device is
selected when Chip Select (S) is driven low. Communications with the device can be
interrupted when the HOLD is driven low.

Table 1. Signal names

Signal name Function Direction

C Serial Clock Input

D Serial Data Input Input
Q Serial Data Output Output
S Chip Select Input
W Write Protect Input
HOLD Hold Input
VCC Supply voltage
VSS Ground

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M95M01-125 Description

Figure 2. 8-pin package connections (top view)

M95xxx

S 1 8 VCC
Q 2 7 HOLD
W 3 6 C
VSS 4 5 D
AI01790D

1. See Section 10: Package mechanical data section for package dimensions, and how to identify pin 1.

Doc ID 023153 Rev 1 7/37

Memory organization M95M01-125

2 Memory organization

The memory is organized as shown in the following figure.

Figure 3. Block diagram

HOLD
High voltage
W Control logic generator
S

D
I/O shift register
Q

Address register Data

and counter register

Status
Register Size of the
read-only
EEPROM
area
Y decoder

1 page

X decoder

AI01272d

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M95M01-125 Signal description

3 Signal description

During all operations, VCC must be held stable and within the specified valid range:
VCC(min) to VCC(max).
All of the input and output signals must be held high or low (according to voltages of VIH,
VOH, VIL or VOL, as specified in Section 9: DC and AC parameters). These signals are
described next.

3.1 Serial Data Output (Q)

This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).

3.2 Serial Data Input (D)

This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be written. Values are latched on the rising edge of Serial Clock
(C).

3.3 Serial Clock (C)

This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) change from the falling edge of Serial Clock (C).

3.4 Chip Select (S)

When this input signal is high, the device is deselected and Serial Data Output (Q) is at high
impedance. The device is in the Standby Power mode, unless an internal Write cycle is in
progress. Driving Chip Select (S) low selects the device, placing it in the Active Power mode.
After power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.

3.5 Hold (HOLD)

The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven low.

Doc ID 023153 Rev 1 9/37

Signal description M95M01-125

3.6 Write Protect (W)

The main purpose of this input signal is to freeze the size of the area of memory that is
protected against Write instructions (as specified by the values in the BP1 and BP0 bits of
the Status Register).
This pin must be driven either high or low, and must be stable during all Write instructions.

3.7 VCC supply voltage

VCC is the supply voltage.

3.8 VSS ground

VSS is the reference for all signals, including the VCC supply voltage.

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M95M01-125 Connecting to the SPI bus

4 Connecting to the SPI bus

All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.

Figure 4. Bus master and memory devices on the SPI bus

VSS

VCC

SDO
SPI Interface with
SDI
(CPOL, CPHA) =
(0, 0) or (1, 1) SCK

C Q D VCC C Q D VCC C Q D VCC

SPI Bus Master VSS VSS VSS

R SPI Memory R SPI Memory R SPI Memory

Device Device Device
CS3 CS2 CS1

S W HOLD S W HOLD S W HOLD

AI12836b

1. The Write Protect (W) and Hold (HOLD) signals should be driven, high or low as appropriate.
Figure 4 shows an example of three memory devices connected to an SPI bus master. Only
one memory device is selected at a time, so only one memory device drives the Serial Data
Output (Q) line at a time. The other memory devices are high impedance.
The pull-up resistor R (represented in Figure 4) ensures that a device is not selected if the
Bus Master leaves the S line in the high impedance state.
In applications where the Bus Master may leave all SPI bus lines in high impedance at the
same time (for example, if the Bus Master is reset during the transmission of an instruction),
the clock line (C) must be connected to an external pull-down resistor so that, if all
inputs/outputs become high impedance, the C line is pulled low (while the S line is pulled
high): this ensures that S and C do not become high at the same time, and so, that the
tSHCH requirement is met. The typical value of R is 100 kΩ..

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Connecting to the SPI bus M95M01-125

4.1 SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of
the following two modes:
● CPOL=0, CPHA=0
● CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
● C remains at 0 for (CPOL=0, CPHA=0)
● C remains at 1 for (CPOL=1, CPHA=1)

Figure 5. SPI modes supported

CPOL CPHA

0 0 C

1 1 C

D MSB

Q MSB

AI01438B

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M95M01-125 Operating features

5 Operating features

5.1 Supply voltage (VCC)

5.1.1 Operating supply voltage VCC

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage
within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions
in Section 9: DC and AC parameters). This voltage must remain stable and valid until the
end of the transmission of the instruction and, for a Write instruction, until the completion of
the internal write cycle (tW). In order to secure a stable DC supply voltage, it is
recommended to decouple the VCC line with a suitable capacitor (usually of the order of
10 nF to 100 nF) close to the VCC/VSS device pins.

5.1.2 Device reset

In order to prevent erroneous instruction decoding and inadvertent Write operations during
power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not
respond to any instruction until VCC reaches the POR threshold voltage. This threshold is
lower than the minimum VCC operating voltage (see Operating conditions in Section 9: DC
and AC parameters).
At power-up, when VCC passes over the POR threshold, the device is reset and is in the
following state:
● in Standby Power mode,
● deselected,
● Status Register values:
– The Write Enable Latch (WEL) bit is reset to 0.
– The Write In Progress (WIP) bit is reset to 0.
– The SRWD, BP1 and BP0 bits remain unchanged (non-volatile bits).
It is important to note that the device must not be accessed until VCC reaches a valid and
stable level within the specified [VCC(min), VCC(max)] range, as defined under Operating
conditions in Section 9: DC and AC parameters.

5.1.3 Power-up conditions

When the power supply is turned on, VCC rises continuously from VSS to VCC. During this
time, the Chip Select (S) line is not allowed to float but should follow the VCC voltage. It is
therefore recommended to connect the S line to VCC via a suitable pull-up resistor (see
Figure 4).
In addition, the Chip Select (S) input offers a built-in safety feature, as the S input is edge-
sensitive as well as level-sensitive: after power-up, the device does not become selected
until a falling edge has first been detected on Chip Select (S). This ensures that Chip Select
(S) must have been high, prior to going low to start the first operation.
The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage
defined under Operating conditions in Section 9: DC and AC parameters, and the rise time
must not vary faster than 1 V/µs.

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Operating features M95M01-125

5.1.4 Power-down
During power-down (continuous decrease of the VCC supply voltage below the minimum
VCC operating voltage defined under Operating conditions in Section 9: DC and AC
parameters), the device must be:
● deselected (Chip Select S should be allowed to follow the voltage applied on VCC),
● in Standby Power mode (there should not be any internal write cycle in progress).

5.2 Active Power and Standby Power modes

When Chip Select (S) is low, the device is selected, and in the Active Power mode. The
device consumes ICC.
When Chip Select (S) is high, the device is deselected. If a Write cycle is not currently in
progress, the device then goes into the Standby Power mode, and the device consumption
drops to ICC1, as specified in DC characteristics (see Section 9: DC and AC parameters).

5.3 Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence.
To enter the Hold condition, the device must be selected, with Chip Select (S) low.
During the Hold condition, the Serial Data Output (Q) is high impedance, and the Serial
Data Input (D) and the Serial Clock (C) are Don’t Care.
Normally, the device is kept selected for the whole duration of the Hold condition.
Deselecting the device while it is in the Hold condition has the effect of resetting the state of
the device, and this mechanism can be used if required to reset any processes that had
been in progress.(a)(b)

Figure 6. Hold condition activation

HOLD

Hold Hold
condition condition

ai02029E

The Hold condition starts when the Hold (HOLD) signal is driven low when Serial Clock (C)
is already low (as shown in Figure 6).

a. This resets the internal logic, except the WEL and WIP bits of the Status Register.
b. In the specific case where the device has shifted in a Write command (Inst + Address + data bytes, each data
byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.

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M95M01-125 Operating features

The Hold condition ends when the Hold (HOLD) signal is driven high when Serial Clock (C)
is already low.
Figure 6 also shows what happens if the rising and falling edges are not timed to coincide
with Serial Clock (C) being low.

5.4 Status Register

The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. See Section 6.3: Read Status Register (RDSR) for a
detailed description of the Status Register bits.

5.5 Data protection and protocol control

The device features the following data protection mechanisms:
● Before accepting the execution of the Write and Write Status Register instructions, the
device checks whether the number of clock pulses comprised in the instructions is a
multiple of eight.
● All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit.
● The Block Protect (BP1, BP0) bits in the Status Register are used to configure part of
the memory as read-only.
● The Write Protect (W) signal is used to protect the Block Protect (BP1, BP0) bits in the
Status Register.
For any instruction to be accepted, and executed, Chip Select (S) must be driven high after
the rising edge of Serial Clock (C) for the last bit of the instruction, and before the next rising
edge of Serial Clock (C).
Two points should be noted in the previous sentence:
● The “last bit of the instruction” can be the eighth bit of the instruction code, or the eighth
bit of a data byte, depending on the instruction (except for Read Status Register
(RDSR) and Read (READ) instructions).
● The “next rising edge of Serial Clock (C)” might (or might not) be the next bus
transaction for some other device on the SPI bus.

Table 2. Write-protected block size

Status Register bits
Protected block Protected array addresses
BP1 BP0

0 0 none none
0 1 Upper quarter 1.80.00h - 1.FF.FFh
1 0 Upper half 1.00.00h - 1.FF.FFh
1 1 Whole memory 0.00.00h - 1.FF.FFh

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Instructions M95M01-125

6 Instructions

Each instruction starts with a single-byte code, as summarized in Table 3.

If an invalid instruction is sent (one not contained in Table 3), the device automatically
deselects itself.

Table 3. Instruction set

Instruction Description Instruction format

WREN Write Enable 0000 0110

WRDI Write Disable 0000 0100
RDSR Read Status Register 0000 0101
WRSR Write Status Register 0000 0001
READ Read from Memory Array 0000 0011
WRITE Write to Memory Array 0000 0010

Table 4. Address range bits

Address significant bits A16-A0(1)
1. Upper MSBs are Don’t Care.

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M95M01-125 Instructions

6.1 Write Enable (WREN)

The Write Enable Latch (WEL) bit must be set prior to each WRITE and WRSR instruction.
The only way to do this is to send a Write Enable instruction to the device.
As shown in Figure 7, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D). The device then
enters a wait state. It waits for the device to be deselected, by Chip Select (S) being driven
high.

Figure 7. Write Enable (WREN) sequence

0 1 2 3 4 5 6 7

Instruction

High Impedance
Q
AI02281E

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Instructions M95M01-125

6.2 Write Disable (WRDI)

One way of resetting the Write Enable Latch (WEL) bit is to send a Write Disable instruction
to the device.
As shown in Figure 8, to send this instruction to the device, Chip Select (S) is driven low,
and the bits of the instruction byte are shifted in, on Serial Data Input (D).
The device then enters a wait state. It waits for a the device to be deselected, by Chip Select
(S) being driven high.
The Write Enable Latch (WEL) bit, in fact, becomes reset by any of the following events:
● Power-up
● WRDI instruction execution
● WRSR instruction completion
● WRITE instruction completion.

Figure 8. Write Disable (WRDI) sequence

0 1 2 3 4 5 6 7

Instruction

High Impedance
Q
AI03750D

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M95M01-125 Instructions

6.3 Read Status Register (RDSR)

The Read Status Register (RDSR) instruction is used to read the Status Register. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 9.

Figure 9. Read Status Register (RDSR) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction

Status Register Out Status Register Out

High Impedance
Q 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7

MSB MSB

AI02031E

The status and control bits of the Status Register are as follows:

6.3.1 WIP bit

The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0, no such
cycle is in progress.

6.3.2 WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1, the internal Write Enable Latch is set. When set to 0, the internal Write
Enable Latch is reset, and no Write or Write Status Register instruction is accepted.
The WEL bit is returned to its reset state by the following events:
● Power-up
● Write Disable (WRDI) instruction completion
● Write Status Register (WRSR) instruction completion
● Write (WRITE) instruction completion

6.3.3 BP1, BP0 bits

The Block Protect (BP1, BP0) bits are non volatile. They define the size of the area to be
software-protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set
to 1, the relevant memory area (as defined in Table 2) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.

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Instructions M95M01-125

6.3.4 SRWD bit

The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal enable the device to be put in the Hardware Protected mode (when the Status
Register Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven low). In this
mode, the non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits
and the Write Status Register (WRSR) instruction is no longer accepted for execution.

Table 5. Status Register format

b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP

Status Register Write Protect

Block Protect bits
Write Enable Latch bit
Write In Progress bit

6.4 Write Status Register (WRSR)

The Write Status Register (WRSR) instruction is used to write new values to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must have been
previously executed.
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) low,
followed by the instruction code, the data byte on Serial Data input (D) and Chip Select (S)
driven high. Chip Select (S) must be driven high after the rising edge of Serial Clock (C) that
latches in the eighth bit of the data byte, and before the next rising edge of Serial Clock (C).
Otherwise, the Write Status Register (WRSR) instruction is not executed.
The instruction sequence is shown in Figure 10.

Figure 10. Write Status Register (WRSR) sequence

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

Instruction Status
Register In

D 7 6 5 4 3 2 1 0

High Impedance MSB

Q
AI02282D

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M95M01-125 Instructions

Driving the Chip Select (S) signal high at a byte boundary of the input data triggers the self-
timed Write cycle that takes tW to complete (as specified in AC tables under Section 9: DC
and AC parameters).
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write in progress (WIP) bit: the WIP bit is 1 during the self-timed
Write cycle tW, and 0 when the Write cycle is complete. The WEL bit (Write Enable Latch) is
also reset at the end of the Write cycle tW.
The Write Status Register (WRSR) instruction enables the user to change the values of the
BP1, BP0 and SRWD bits:
● The Block Protect (BP1, BP0) bits define the size of the area that is to be treated as
read-only, as defined in Table 2.
● The SRWD (Status Register Write Disable) bit, in accordance with the signal read on
the Write Protect pin (W), enables the user to set or reset the Write protection mode of
the Status Register itself, as defined in Table 6. When in Write-protected mode, the
Write Status Register (WRSR) instruction is not executed.
The contents of the SRWD and BP1, BP0 bits are updated after the completion of the
WRSR instruction, including the tW Write cycle.
The Write Status Register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in
the Status Register. Bits b6, b5, b4 are always read as 0.

Table 6. Protection modes

Memory content
W SRWD Write protection of the
Mode
signal bit Status Register
Protected area(1) Unprotected area(1)

1 0 Status Register is
writable (if the WREN
0 0
Software- instruction has set the
Ready to accept
protected WEL bit). Write-protected
Write instructions
(SPM) The values in the BP1
1 1
and BP0 bits can be
changed.
Status Register is
Hardware write-
Hardware-
protected. Ready to accept
0 1 protected Write-protected
The values in the BP1 Write instructions
(HPM)
and BP0 bits cannot be
changed.
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register. See Table 2.

The protection features of the device are summarized in Table 6.

When the Status Register Write Disable (SRWD) bit in the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register (provided that the WEL bit has
previously been set by a WREN instruction), regardless of the logic level applied on the
Write Protect (W) input pin.

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Instructions M95M01-125

When the Status Register Write Disable (SRWD) bit in the Status Register is set to 1, two
cases should be considered, depending on the state of the Write Protect (W) input pin:
● If Write Protect (W) is driven high, it is possible to write to the Status Register (provided
that the WEL bit has previously been set by a WREN instruction).
● If Write Protect (W) is driven low, it is not possible to write to the Status Register even if
the WEL bit has previously been set by a WREN instruction. (Attempts to write to the
Status Register are rejected, and are not accepted for execution). As a consequence,
all the data bytes in the memory area, which are Software-protected (SPM) by the
Block Protect (BP1, BP0) bits in the Status Register, are also hardware-protected
against data modification.
Regardless of the order of the two events, the Hardware-protected mode (HPM) can be
entered by:
● either setting the SRWD bit after driving the Write Protect (W) input pin low,
● or driving the Write Protect (W) input pin low after setting the SRWD bit.
Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to
pull high the Write Protect (W) input pin.
If the Write Protect (W) input pin is permanently tied high, the Hardware-protected mode
(HPM) can never be activated, and only the Software-protected mode (SPM), using the
Block Protect (BP1, BP0) bits in the Status Register, can be used.

6.5 Read from Memory Array (READ)

As shown in Figure 11, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte and address bytes are then shifted in, on Serial Data
Input (D). The address is loaded into an internal address register, and the byte of data at
that address is shifted out, on Serial Data Output (Q).

Figure 11. Read from Memory Array (READ) sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

Instruction 24-bit address

D 23 22 21 3 2 1 0
MSB
Data Out 1 Data Out 2
High Impedance
Q 7 6 5 4 3 2 1 0 7
MSB

AI13878

If Chip Select (S) continues to be driven low, the internal address register is incremented
automatically, and the byte of data at the new address is shifted out.

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M95M01-125 Instructions

When the highest address is reached, the address counter rolls over to zero, allowing the
Read cycle to be continued indefinitely. The whole memory can, therefore, be read with a
single READ instruction.
The Read cycle is terminated by driving Chip Select (S) high. The rising edge of the Chip
Select (S) signal can occur at any time during the cycle.
The instruction is not accepted, and is not executed, if a Write cycle is currently in progress.

6.6 Write to Memory Array (WRITE)

As shown in Figure 12, to send this instruction to the device, Chip Select (S) is first driven
low. The bits of the instruction byte, address byte, and at least one data byte are then shifted
in, on Serial Data Input (D).
The instruction is terminated by driving Chip Select (S) high at a byte boundary of the input
data. The self-timed Write cycle, triggered by the Chip Select (S) rising edge, continues for a
period tW (as specified in AC characteristics in Section 9: DC and AC parameters), at the
end of which the Write in Progress (WIP) bit is reset to 0.

Figure 12. Byte Write (WRITE) sequence

                      

)NSTRUCTION  BIT ADDRESS $ATA BYTE

$               

(IGH IMPEDANCE
1

-36

In the case of Figure 12, Chip Select (S) is driven high after the eighth bit of the data byte
has been latched in, indicating that the instruction is being used to write a single byte.
However, if Chip Select (S) continues to be driven low, as shown in Figure 13, the next byte
of input data is shifted in, so that more than a single byte, starting from the given address
towards the end of the same page, can be written in a single internal Write cycle.
Each time a new data byte is shifted in, the least significant bits of the internal address
counter are incremented. If more bytes are sent than will fit up to the end of the page, a
condition known as “roll-over” occurs. In case of roll-over, the bytes exceeding the page size
are overwritten from location 0 of the same page.

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Instructions M95M01-125

The instruction is not accepted, and is not executed, under the following conditions:
● if the Write Enable Latch (WEL) bit has not been set to 1 (by executing a Write Enable
instruction just before),
● if a Write cycle is already in progress,
● if the device has not been deselected, by driving high Chip Select (S), at a byte
boundary (after the eighth bit, b0, of the last data byte that has been latched in),
● if the addressed page is in the region protected by the Block Protect (BP1 and BP0)
bits.
Note: The self-timed write cycle tW is internally executed as a sequence of two consecutive
events: [Erase addressed byte(s)], followed by [Program addressed byte(s)]. An erased bit is
read as “0” and a programmed bit is read as “1”.

Figure 13. Page Write (WRITE) sequence

0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39

Instruction 24-bit address Data byte 1

D    3 2 1 0 7 6 5 4 3 2 1 0

Data byte 2 Data byte 3 Data byte N

D 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0

-36

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M95M01-125 Instructions

6.6.1 Cycling with Error Correction Code (ECC)

M95M01 devices offer an Error Correction Code (ECC) logic. The ECC is an internal logic
function which is transparent for the SPI communication protocol.
The ECC logic is implemented on each group of four EEPROM bytes(c). Inside a group, if a
single bit out of the four bytes happens to be erroneous during a Read operation, the ECC
detects this bit and replaces it with the correct value. The read reliability is therefore much
improved.
Even if the ECC function is performed on groups of four bytes, a single byte can be
written/cycled independently. In this case, the ECC function also writes/cycles the three
other bytes located in the same group(c). As a consequence, the maximum cycling budget is
defined at group level and the cycling can be distributed over the four bytes of the group: the
sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain
below the maximum value defined in Table 11.

c. A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer.

Doc ID 023153 Rev 1 25/37

Power-up and delivery state M95M01-125

7 Power-up and delivery state

7.1 Power-up state

After power-up, the device is in the following state:
● Standby power mode,
● deselected (after power-up, a falling edge is required on Chip Select (S) before any
instructions can be started),
● not in the Hold condition,
● the Write Enable Latch (WEL) is reset to 0,
● Write In Progress (WIP) is reset to 0.
The SRWD, BP1 and BP0 bits of the Status Register are unchanged from the previous
power-down (they are non-volatile bits).

7.2 Initial delivery state

The device is delivered with the memory array set to all 1s (each byte = FFh). The Status
Register Write Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.

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M95M01-125 Maximum rating

8 Maximum rating

Stressing the device outside the ratings listed in Table 7 may cause permanent damage to
the device. These are stress ratings only, and operation of the device at these, or any other
conditions outside those indicated in the operating sections of this specification, is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Table 7. Absolute maximum ratings

Symbol Parameter Min. Max. Unit

Ambient operating temperature –40 130 °C

TSTG Storage temperature –65 150 °C
TLEAD Lead temperature during soldering See note (1) °C
VO Output voltage –0.50 VCC+0.6 V
VI Input voltage –0.50 6.5 V
VCC Supply voltage –0.50 6.5 V
IOL DC output current (Q = 0) 5 mA
IOH DC output current (Q = 1) 5 mA
VESD Electrostatic discharge voltage (human body model)(2) 4000 V
1. Compliant with JEDEC Std J-STD-020 (for small body, Sn-Pb or Pb assembly), with the ST ECOPACK®
7191395 specification, and with the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-
Q100-002 (compliant with JEDEC Std JESD22-A114, C1=100 pF, R1=1500 Ω, R2=500 Ω).

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DC and AC parameters M95M01-125

9 DC and AC parameters

This section summarizes the operating conditions and the DC/AC characteristics of the
device.

Table 8. Operating conditions (M95M01-W, device grade 3)

Symbol Parameter Min. Max. Unit

VCC Supply voltage 2.5 5.5 V

TA Ambient operating temperature –40 125 °C

Table 9. AC measurement conditions

Symbol Parameter Min. Max. Unit

CL Load capacitance 100 pF

Input rise and fall times 50 ns
Input pulse voltages 0.2 VCC to 0.8 VCC V
Input and output timing reference voltages 0.3 VCC to 0.7 VCC V

Figure 14. AC measurement I/O waveform

)NPUT VOLTAGE LEVELS )NPUT AND OUTPUT
TIMING REFERENCE LEVELS
 6##
 6##

 6##
 6##

!)#

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M95M01-125 DC and AC parameters

Table 10. Capacitance

Symbol Parameter Test conditions(1) Min. Max. Unit

COUT Output capacitance (Q) VOUT = 0 V 8 pF

Input capacitance (D) VIN = 0 V 8 pF
CIN
Input capacitance (other pins) VIN = 0 V 6 pF
1. Sampled only, not 100% tested, at TA = 25 °C and a frequency of 5 MHz.

Table 11. Memory cell characteristics

Symbol Parameter Test condition Min. Max. Unit

Ncycle Endurance TA = 25 °C, 2.5 V < Vcc < 5.5 V 1,000,000 - Write cycle

Note: This parameter is not tested but established by characterization and qualification. For
endurance estimates in a specific application, please refer to AN2014.

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DC and AC parameters M95M01-125

Table 12. DC characteristics (M95M01-W, device grade 3)

Symbol Parameter Test conditions specified in Table 8 Min. Max. Unit

ILI Input leakage current VIN = VSS or VCC ±2 µA

ILO Output leakage current S = VCC, VOUT = VSS or VCC ±2 µA
C = 0.1VCC/0.9VCC at 5 MHz,
4 mA
VCC = 2.5 V, Q = open
ICC Supply current (Read)
C = 0.1 VCC/0.9VCC at 5 MHz,
5 mA
VCC = 5 V, Q = open
During tW, S = VCC,
ICC0(1) Supply current (Write) 6 mA
2.5 V < VCC < 5.5 V
Supply current S = VCC, VIN = VSS or VCC,
ICC1 5 µA
(Standby Power mode) 2.5 V < VCC < 5.5 V
VIL Input low voltage –0.45 0.3 VCC V
VIH Input high voltage 0.7 VCC VCC+1 V
VCC = 2.5 V and IOL = 1.5 mA or
VOL Output low voltage 0.4 V
VCC = 5 V and IOL = 2 mA
VCC = 2.5 V and IOH = –0.4 mA or
VOH Output high voltage 0.8 VCC V
VCC = 5 V and IOH = –2 mA
1. Characterized only, not tested in production.

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M95M01-125 DC and AC parameters

Table 13. AC characteristics (M95M01-W, device grade 3)

Test conditions specified in Table 8 and Table 9

Symbol Alt. Parameter Min. Max. Unit

fC fSCK Clock frequency D.C. 5 MHz

tSLCH tCSS1 S active setup time 60 ns
tSHCH tCSS2 S not active setup time 60 ns
tSHSL tCS S deselect time 60 ns
tCHSH tCSH S active hold time 60 ns
tCHSL S not active hold time 60 ns
tCH (1) tCLH Clock high time 90 ns
(1)
tCL tCLL Clock low time 90 ns
(2)
tCLCH tRC Clock rise time 2 µs
tCHCL (2) tFC Clock fall time 2 µs
tDVCH tDSU Data in setup time 20 ns
tCHDX tDH Data in hold time 20 ns
tHHCH Clock low hold time after HOLD not active 60 ns
tHLCH Clock low hold time after HOLD active 60 ns
tCLHL Clock low setup time before HOLD active 0 ns
tCLHH Clock low setup time before HOLD not active 0 ns
(2)
tSHQZ tDIS Output disable time 80 ns
tCLQV tV Clock low to output valid 80 ns
tCLQX tHO Output hold time 0 ns
(2)
tQLQH tRO Output rise time 80 ns
tQHQL (2) tFO Output fall time 80 ns
tHHQV tLZ HOLD high to output valid 80 ns
tHLQZ (2) tHZ HOLD low to output High-Z 80 ns
tW tWC Write time 5 ms
1. tCH + tCL must never be less than the shortest possible clock period, 1 / fC(max)
2. Characterized only, not tested in production.

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DC and AC parameters M95M01-125

Figure 15. Serial input timing

tSHSL

tCHSL tSLCH tCH tCHSH tSHCH

tDVCH tCHCL tCL tCLCH

tCHDX

D MSB IN LSB IN

High impedance
Q

AI01447d

Figure 16. Hold timing

tHLCH

tCLHL tHHCH

tCLHH

tHLQZ tHHQV

HOLD

AI01448c

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M95M01-125 DC and AC parameters

Figure 17. Serial output timing

tCH tSHSL

tCLQV tCLCH tCHCL tCL tSHQZ

tCLQX

tQLQH
tQHQL

ADDR
D LSB IN

AI01449f

Doc ID 023153 Rev 1 33/37

Package mechanical data M95M01-125

10 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Figure 18. SO8N – 8-lead plastic small outline, 150 mils body width, package outline
h x 45˚

A2 A
c
ccc
b
e

0.25 mm
D GAUGE PLANE

k
8

E1 E
1 L
A1
L1

SO-A

1. Drawing is not to scale.

Table 14. SO8N – 8-lead plastic small outline, 150 mils body width, mechanical data
millimeters inches(1)
Symbol
Typ Min Max Typ Min Max

A 1.750 0.0689
A1 0.100 0.250 0.0039 0.0098
A2 1.250 0.0492
b 0.280 0.480 0.0110 0.0189
c 0.170 0.230 0.0067 0.0091
ccc 0.100 0.0039
D 4.900 4.800 5.000 0.1929 0.1890 0.1969
E 6.000 5.800 6.200 0.2362 0.2283 0.2441
E1 3.900 3.800 4.000 0.1535 0.1496 0.1575
e 1.270 - - 0.0500 - -
h 0.250 0.500 0.0098 0.0197
k 0° 8° 0° 8°
L 0.400 1.270 0.0157 0.0500
L1 1.040 0.0409
1. Values in inches are converted from mm and rounded to four decimal digits.

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M95M01-125 Part numbering

11 Part numbering

Table 15. Ordering information scheme

Example: M95M01 W MN 3 T P /A

Device type
M95 = SPI serial access EEPROM

Device function
1 Mbit (131072 x 8)

Operating voltage
W = VCC = 2.5 to 5.5 V

Package
MN = SO8 (150 mil width)

Device grade
3 = Device tested with high reliability certified flow.
Automotive temperature range (–40 to 125 °C)

Option
T = Tape and reel packing

Plating technology
P = RoHS compliant and halogen-free (ECOPACK®)

Process
/A= Manufacturing technology code

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Revision history M95M01-125

12 Revision history

Table 16. Document revision history

Date Revision Changes

20-Jun-2012 1 Initial release.

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M95M01-125

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Doc ID 023153 Rev 1 37/37