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Implementation and Control of an Hybrid Multilevel Converter with Floating DC-links for Current Waveform Improvement
C sar Silva, Member, IEEE, Leopoldo C rdova, Pablo Lezana Member, IEEE, and Lee Empringham e o

AbstractMultilevel converters offer advantages in terms of the output waveform quality due to the increased number of levels used in the output voltage modulation. This advantage is particularly true for cascaded H-bridge converters that can be built to produce a large number of levels thanks to their modular structure. Nevertheless, this advantage comes at the cost of multiple DC-links supplied by independent rectiers through the use of a multi-output transformer for inverters. This frontend complicates the implementation of converters that have a high number of levels. An alternative method of using lower voltage cells with oating dc-links to compensate only for voltage distortion of an NPC converter is considered for active rectier applications. The analogy between the oating H-bridges and series active lters is used to develop a strategy for harmonic compensation of the NPC output voltage and the control of the oating dc-link voltages. This simplies the current control scheme and increases its bandwidth. Experimental results with a low power prototype that show the good performance of the proposed modulation technique and the resulting improvement in the output waveform are provided. Index TermsPower electronics, current control, harmonic distortion

increased number of voltage levels will result in a reduced input lter size for grid connected applications. Moreover, a high number of levels allows the device switching frequency to be reduced for a given current distortion. The multilevel topologies can be classied into three main categories: the neutral point clamped (NPC) [3], the ying capacitors (FC) [4], [5] and the cascaded H-bridge (CHB) converters [6], [7]. The three level NPC bridge is probably the most widely used topology for medium voltage AC motor drives and PWM active rectiers [8], [9]. NPC converters with more levels are also possible, although there are signicant problems in the balancing of their dc-link capacitor voltages [10], [11], unless modied modulation strategies [12] or additionally circuitry [13] are used. On the other hand, the CHB converter is normally implemented with large number of levels, but at the cost of complicated and bulky input transformers with multiple rectiers [7], [14], [15] or multi-winding three-phase output transformers [16]. For this reason, in applications with no active power transfer, such as in reactive power compensation, where the converter can operate without the rectier front-end, the CHB is a highly attractive solution [17], [18]. In recent years an increased interest has been given to hybrid topologies integrating more than one topology in a single converter. Some authors have proposed the use of cascaded H-bridges fed by multilevel dc-links generated which are implemented with another converter topology [19][21]. In [22], an hybrid conguration based on the combination of an active NPC and a ying capacitor cell has been proposed to implement a ve level converter. An hybrid converter formed by the series connection of a main three-level NPC converter and auxiliary oating H-Bridges (NPC-HBs) has been presented in [23][25]. In this topology, the NPC is used to supply the active power while the HBs operate as series active lters, improving the voltage waveform quality by only handling reactive power. In this way, this topology reduces the need for bulky and expensive LCL passive lters, making it an attractive alternative for large power applications [24], [25]. In this work, the control strategy for the NPC-HBs hybrid converter, previously introduced in [26], is experimentally veried. This includes: low frequency synchronous modulation of the NPC and the generation of the HBs voltage references for dc-link voltage control.

I. I NTRODUCTION In the last decade, medium-voltage high-power converters have become widely used as drives for pumps, fans and material transport in a number of industries, as well as for VAR compensation in grid applications [1], [2]. At this voltage range, multilevel converters are preferred to overcome the voltage blocking limitations of the available switches. Another important advantage of this technology is the improved output waveforms due, to the higher number of levels in the output voltage waveform, compared to the conventional three-phase two-level inverter. Similarly, an
Copyright (c) 2009 IEEE. Personal use of this material is permitted. However, permission to use this material for any other purposes must be obtained from the IEEE by sending a request to pubs-permissions@ieee.org. The authors gratefully acknowledge nancial support provided by the Chilean National Fund of Scientic and Technological Development (FONDECYT) and by the Centro Cientico-Tecnologico De Valparaiso (CCTVal) N.FB0821. C. Silva and L. C rdova are with the Departamento de Electr nica, o o Universidad T cnica Federico Santa Mara, Valparaso, Chile (e-mail: cee sar.silva@usm.cl; leopoldo.codova@alumnos.usm.cl). P. Lezana is with the Departamento de Ingeniera El ctrica, Uni e versidad T cnica Federico Santa Mara, Valparaso, Chile (e-mail: e pablo.lezana@usm.cl). L. Empringham is with the School of Electrical and Electronic Engineering, University of Nottingham, Nottingham, UK (e-mail: Lee.Empringham@nottingham.ac.uk).

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II. H YBRID T OPOLOGY A. Power Circuit The considered hybrid topology is composed by a traditional three-phase, three-level NPC inverter, connected with a single phase H-bridge inverter in series with each output phase [23][25]. The power circuit is illustrated in Fig. 1, with only the H-bridge of phase a shown in detail. For testing as an inverter, the DC source for the NPC converter is provided by two series connected diode bridge rectiers, arranged in a twelve-pulse conguration. The Hbridge DC-links are not connected to an external DC power supply, and they consist only of oating capacitors kept at a constant voltage by the control strategy detailed in Section III. In the hybrid topology considered, the NPC inverter provides the total active power ow. For high-power medium voltage NPC, there are advantages to using latching devices such IGCTs rather than IGBTs, due to their lower losses and higher voltage blocking capability [23], [25], [27], imposing a restriction on the switching frequency. In this work, an NPC operating at a low switching frequency (of 250Hz) is considered. In contrast, the H-bridges are rated at a lower voltage and need to be commutated at a higher frequency for an effective active ltering effect. This calls for the use of IGBT.

at a low switching frequency, as proposed in this work, the second interpretation would seem to be more appropriate to devise a control algorithm, leading to the following two design challenges: To determine the lowest value of H-bridge dc-link voltage (VH ) that achieves adequate voltage harmonic compensation. To devise a control algorithm that ensures that the oating dc-links are properly regulated at this value. For the modulation of the NPC inverter, the Selective Harmonic Elimination (SHE) method has been selected. This method has the advantage of very low switching frequency and hence low switching losses, while eliminating the low order harmonics. With the use of SHE modulation, the fundamental output voltage of the converter is synthesized by the NPC converter and thus the series HBs will only need to supply reactive power, allowing for operation with oating capacitor DC-links. A drawback of any synchronous modulation method, such as SHE, is its limited dynamic capability and poor closed loop performance due to the use of a pre-calculated lookup table based approach, rather than real time calculations [28]. These drawbacks can, to a large extent, be overcome by the use of the series H-bridges which are modulated in real time, introducing an additional degree of control freedom to the circuit and cleaner feedback signals. B. NPC Selective Harmonic Elimination Three-level SHE is an established and well documented modulation strategy [29]. A qualitative phase output voltage waveform is presented in Fig. 2 considering a 5-angle realization, so ve degrees of freedom are available. This enables the amplitude of the fundamental component to be controlled and four harmonics to be eliminated. Since a three-phase system is considered, the triple harmonics are eliminated at the load by connection, and hence, they do not require elimination by the modulation pulse pattern. Thus, the 5th , 7th , 11th and 13th harmonics are chosen for elimination. For line-connected applications, this 5-angle implementation results in a switching frequency of 250Hz for the NPC portion of the converter and leaves the 17th as the rst harmonic component to appear in the steady state load current. On the other hand, for variable frequency drive applications, the number of angles must be varied in order to maintain a near constant switching frequency at any operation point [30].
2 4

Cd

Cd

CH

RL ,L L

Fig. 1.

Hybrid topology power circuit.

Vdc/2

The proposed converter, shown in Fig.1, can be analyzed from two different points of view. The rst interpretation is as a single hybrid multilevel inverter with a nine level phase voltage, achieved by the cascade connection of a three level NPC leg and an H-bridge per-phase. The second interpretation is as an NPC converter with a series active lter that compensates for the harmonic content introduced by the low switching NPC stage. If the NPC bridge is to be modulated

0
1 3 5

Vdc/2

/2

3 /2

2
N)

Fig. 2. Three-level NPC selective harmonic elimination phase voltage (va waveform.

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C. H-Bridge oating DC-link voltage determination The addition of the series H-bridge results in more levels being added on the output voltage waveform of the converter vaN . In particular, if the value of VH is smaller than Vdc /4, no redundant switching states are created and the output voltage waveform of the converter will have the maximum number of levels (nine), generating similar waveforms to those achieved by cascade H-bridge inverters with unequal dc sources [1], [31]. The increased number of output levels leads to a reduction in both the V of the output voltage waveform and the harmonic content of the overall output voltage vaN , enhancing the power quality of the hybrid converter. One logical solution would be to make VH equal to a sixth of the NPC total dc-link voltage, i.e. VH = Vdc /6, so that equally spaced output voltage levels would be created. On the other hand, considering that the NPC converter is modulated using the synchronous SHE method, the H-bridge should be modulated to compensate for the distortion created by the modulation of the NPC. This is done at a higher frequency using carrier based unipolar PWM. When deciding the value for the dc-link voltage of the Hbridges VH , a sufciently large value should be selected to achieve appropriate compensation of the remaining distortion, while at the same time the value of VH should be kept as low as possible in order to minimize the additional switching losses. The voltage distortion remaining from the SHE modulation of the NPC converter can be computed as the difference from the NPC output voltage and the reference value. The NPC output voltage is calculated including the interaction between the phases, i.e. excluding the common mode voltage from the resulting waveform. In Fig. 3a, the NPC SHE output pattern and the corresponding reference are shown. The load phase voltage resulting from the interaction of the three phases through the load neutral, as shown in Fig. 3b, is used to compute the H-bridge reference as the difference between this signal and the reference. This results in a reference signal with lower amplitude than that calculated directly from the SHE patterns, as shown in Fig. 3c. The peak value of this harmonic reference voltage varies, depending on the modulation index as illustrated in Fig. 4 for the best and worst case, respectively. On the other hand, Fig. 4b) suggests that, if VH was limited to a lower value, e.g. 0.167Vdc , over modulation would occur but only for short periods since the peaks in the harmonic voltage reference waveform have a low voltage-time area. In other words, a compromise between the value of VH and the error incurred by over-modulating the HBs has to be found. A methodology for the solution of this tradeoff is described in [26] and from this, it can be concluded that the best compensation is obtained for values of VH between 0.167Vdc and 0.25Vdc . Owing to the compromise between compensation and minimization of the switching losses in the H-bridges, a value of 0.167Vdc is used for VH in this work. To estimate the H-bridge switching losses the following considerations are made:

of the blocking voltage of the NPC switches, and hence, lower nominal voltage devices can be used. The lower the nominal blocking voltage of a semiconductor, the faster the switching and the lower the switching losses. The current in both converters is the same. For switches with approximately 1:3 nominal voltage ratio and with similar current rating (e.g. 1.7kV, 1200A IGBT and 4.5kV IGCT, 1100A [32], [33] respectively), the ratio between the switching energy losses is around 1:8 . Then, considering the number of commutations in an H-bridge and in one NPC leg, the losses ratio as a function of their average switching frequencies can be expressed as: fh Ph = (1) Pnpc 8fnpc In this work, 1 was chosen as the ratio in order to achieve an even distribution switching losses among both, the main and auxiliary converters. Hence, as the synchronous pulse pattern results in an average switching frequency of 250Hz for the NPC, the H-bridge PWM carrier frequency is set to 2kHz.
100

Voltage [V]

50 0 -50 -100 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02

100

Voltage [V]

50 0 -50 -100 0 100 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016 0.018 0.02

Voltage [V]

50 0 -50 -100 0 0.002 0.004 0.006 0.008 0.01 Time [s] 0.012 0.014 0.016 0.018 0.02

Fig. 3. H-bridge reference voltage generation for m = 0.8: a) NPC SHE pattern, b) load phase voltage, c) H-bridge harmonic reference with (black) and without (gray) common mode voltage.

Fig. 4. H-bridge reference voltage and carrier waveform, in pu respect to Vdc : a) for m = 0.8, b) for m = 0.89.

The blocking voltage of their semiconductors is one third

III. C ONTROL S TRATEGY A. H-bridge controller Each series H-bridge converter is independently controlled by two complementary references, as shown in Fig. 5. The rst

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* van
+_

* vaa'(fn)
+ +

* vaa'

PWM

Gate signals

(4)

m
angle SHE

Gate signals

(12)

NPC+ Load Model

va'n
* vaa'(f1)

* (vHa)2
+_

Control

VHa

A undesirable characteristic of (2) is its nonlinearity with respect to vHa . This can be dealt with by linearization or 2 by simply introducing the auxiliary variable x = vHa and controlling x directly. As is indicated in Fig. 5, the latter alternative is implemented in this work. Finally, the transfer function can be expressed as (3), which is rst order and can be easily controlled by a PI regulator to follow the constant 2 reference vH . X(s) Va a (s) a i CH s (3)

^ vaa' cos( )

(vHa)2 ia ib ic
Fig. 5.

( , ) (a,b,c)

PLL

B. External current control loop For good dynamic performance, an outer load current loop can be implemented as shown in Fig. 7. As low order harmonics are compensated by the H-bridges, the current can be synchronously sampled with the H-bridge carrier, providing a good estimation of its fundamental value. Moreover, as a high sampling frequency is used, a high current bandwidth can be achieved. It is important to note that, in applications with low frequency switching patterns, such as the SHE modulation, the use of direct synchronous sampling of the currents is not adequate to obtain the fundamental current because the switching harmonics do not cross zero at regular intervals. Instead, observers are needed to extract the fundamental current values [34] otherwise complex nonlinear control schemes are required [35]. In the present work, this problem is overcome by the compensating effect of the series connected H-bridges, which moves the spectra from the non-eliminated SHE harmonics to the high frequency H-bridge carrier band. This effectively simplies the outer load current control loop design, resulting in a standard dq frame linear current regulator as shown in Fig. 7.

H-bridge control diagram for phase a.

ica vHa
H-bridge

vaa

ia

Fig. 6. Simplied H-bridge circuit for dynamic modeling of dc-link voltage.

reference vaa (fn ) corresponds to the inverse of the harmonics remaining from the SHE pulse pattern, calculated as described in the previous section from the difference between the NPC pulsed voltage pattern and its sinusoidal voltage reference. This calculation provides a fast and straightforward distortion estimation allowing for simple feed-forward compensation. Moreover, this voltage does not have a fundamental voltage component and hence it does not affect the oating average DC-link capacitor voltage. Nevertheless, to achieve start-up capacitor charge and to compensate voltage drift due to transient operation, an additional reference component for DClink voltage control is included. This second component of the voltage reference vaa (f1 ) corresponds to a signal in phase with the load current. This voltage is used to inject small amounts of active power into the cell in order to control the H-bridge DC-link voltage at its reference value VH . During operation, the fundamental load current is generated by the NPC converter. In order to synchronize the voltage reference vaa (f1 ) with this current, a phase lock loop (PLL) algorithm is used, which guarantees zero phase shift between both signals and therefore maximizes the active power transfer to the capacitors for any power factor. The magnitude of this voltage reference is obtained from the DC-link voltage controller shown in Fig. 5. For the design of this voltage controller, the dynamic model (2) of the dc-link voltage vHa as a function of vaa is used. This model has been developed based on an instantaneous active power balance applied to the simplied cell circuit of Fig. 6.

C. H-bride DC-link voltage control under regenerative operation In regenerative operation, such as active front end applications for regenerative drives, the power ow needs to be controlled bidirectionally. This is possible due to the interaction between the converter and load voltages through the grid impedance, usually an inductive lter. As indicated in Fig. 8, under the regenerative operation, the load current ow is inverted. Under these conditions, the PLL of Fig. 5 will detect the absolute current phase. This means that a positive reference for the fundamental voltage amplitude vaa > 0 still implies a positive power ow into the cell and hence an increase in the DC-link voltage level vHa . Likewise, a negative fundamental voltage amplitude vaa < 0 produces a reduction in the DC-link voltage level. In other words, the control for the H-bridge cell is effective, irrespective of the direction of power ow. Therefore the technique can be applied without modication for inverter or rectier mode of operation.

2 a vaa i CH dvHa . 2 dt 2

(2)

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NPC inverter
* id + * vd

vHa H-Bridges H H H ia ib ic load n

PI
* iq +

(,) vd*

| |

m SHE

Gate signals (12) MPC model

v*
q

PI

(d,q)

angle

PWM

!*
e

(v * ) + (vHa,b,c )
(d,q) (a,b,c)
2

PI PLL

id

iq

Fig. 7.

Simplied current control loop for the proposed topology, including SHE for the NPC (the control loops for the H-bridges are not shown).

PWM modulation using a carrier frequency of 2kHz.

A. Results for the inverter conguration Experimental results are gained feeding a linear load with values RL = 10 and LL = 3mH with the 1kW prototype. As previously discussed in section III-C, the converter is operated with Vdc = 180V , while the H-Bridge dc-link voltage reference was set to 30V. For comparison purposes, Fig. 9 shows the results for the NPC inverter operating without H-bridge compensation. In this result the NPC inverter is modulated by a 5-angle SHE pattern and m = 0.8. The rst waveform corresponds to the NPC inverter output phase voltage va N which results in the 9-level load voltage waveform van of Fig.9b. Finally, Fig.9c shows the resulting output current waveform with its characteristic low frequency distortion.
100

Fig. 8. Hybrid topology as inverter with active load: a) Equivalent circuit, b) Phasor diagram for feeding mode, c) Phasor diagram for regenerative mode.

IV. R ESULTS The rst phase of the work was to evaluate the proposed topology and control method. Experimental results are included to show the controlled DC-link voltage of the H-Bridges and the current waveform improvement for the Hybrid Inverter. A second stage with simulation results showing the proposed converter operating as AFE rectier, using Matlab/Simulink coupled with the circuit simulator PSIM are also included. The physical ratings of the considered converter are those of a 1kW laboratory prototype with a total DC-link voltage of Vdc = 180V and rated current of 10A. The capacitors used for the H-bridges are CH = 2200F and their reference voltages have been set to vH = 30V The control platform for this t of a DSP board with a Texas Instrument TMS320C6713 processor coupled with a daughter board based on a Xilinx/Spartan III FPGA including multiple A/D converters. In this conguration, the FPGA operates as a sampling clock, triggering the A/D conversions and interrupting the DSP. The processor is used for the calculation of all the controllers which results in a voltage reference for the converter, with this voltage reference the processor addresses the SHE tables and passes the information of commutation angles (x and voltage phase to the FPGA. The FPGA performs the SHE modulation, the calculation of the harmonic references for the H-bridges and its unipolar

NPC output voltage [V]

50 0 -50 -100 120 60 0 -60 -120

(a)

Load output voltage [V]

(b)
10

Output Current [A]

5 0 -5 -10

(c)

0.03

0.04

0.05

0.06

0.07

0.08

Time [s]

Fig. 9.

NPC inverter operation at 50Hz with m = 0.8.

In comparison to the previous results, the full hybrid topology results are shown in Fig. 10. Fig. 10a shows the threelevel NPC output voltage, va N , generated under the same conditions, while Fig. 10b shows the output voltage of the respective H-Bridge vaa . Note the higher switching frequency compared with the NPC output. Additional distortion can be

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100

NPC phase voltage [V]

50 0 -50 -100

of the hybrid converter shows almost a complete elimination of these characteristic harmonics, resulting in a current THD of 2.4%.
(a)
Harmonic amplidude [%]
10 8 6 4 2 0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 THD= 12.9%

H-Bridge output voltage [V]

50 25 0 -25 -50 40 30 20 10 0

H-Bridge dc-link voltage [V]

Harmonic amplidude [%]

(b)

10 8 6 4 2 0 0 500 1000 1500 2000 2500 3000 Frequency [Hz] 3500 4000 4500 5000 THD = 2.4%

(c)
Inverter output voltage [V]
100 50 0

Fig. 11. Current spectrum for 50Hz operation with m = 0.8. a) NPC modulated by SHE. b) Full hybrid converter.
85

-50 -100 120

(d)

Voltage [V] Current [A]

Load output voltage [V]

60 0 -60 -120 10

-85

(a)
8 4 0 -4 -8

(e)

Output Current [A]

5 0 -5 -10

(b) 0.13

0.14

0.15

0.16

0.17

0.18

Time [s]

(f)

0.03

0.04

0.05

0.06

0.07

0.08

Time [s]

Fig. 12. NPC inverter 50Hz closed loop operation with Bandwidth of 160Hz, near m = 0.81: a) the NPC voltage output of phase A; b) Resulting load current.
85

Fig. 10.

Hybrid inverter operation at 50Hz with m = 0.8.

appreciated due to the semiconductors drop, which will not be relevant for higher voltage applications. The H-Bridge DClink voltage is shown in Fig. 10c, which is controlled to be the desired voltage of VH = 0.167Vdc as described in II-C. Also, it can be noted that in Fig. 10e that 33 different voltage levels are applied to the load voltage, causing less distortion in the output inverter waveforms than in the waveforms of Fig. 9. This is seen clearly in the current waveform in Fig. 10f , with a highly sinusoidal shape compared with the output current waveform without the H-Bridges harmonic compensation in Fig. 9c. Hence, comparing the results of Fig. 9 with those of Fig. 10, it is clear that current waveform improvement has been achieved with the hybrid inverter. This is conrmed by the spectral analysis shown in Fig. 11. Here, the spectral content of simulated results corresponding to the steady state currents shown in Fig. 9c and 10f are compared. For this analysis, simulated data is used to overcome inaccuracies, caused by use of a low voltage prototype, in particularly the effect of semiconductor drop. For the NPC converter, as expected, the spectrogram does not show the lower order harmonics. However it does have more than 7% of the 17th and 19th harmonics and signicant amplitude in higher order harmonics, resulting in a current THD of 12.9%. On the other hand, the operation

-85

(a)
30

-30

(b)
8 4 0 -4 -8

(c)

0.13

0.14

0.15

0.16

0.17

0.18

Time [s]

Fig. 13. Hybrid inverter 50Hz closed loop operation with Bandwidth of 160Hz, near m = 0.81: a) NPC voltage output of phase A; b) Voltage output of the H-Bridge A; c) Controlled load current.

B. Experimental results for current closed loop operation This section presents results to ascertain converters performance under closed loop conditions. First, the converter is

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run without the use of the series H-bridges (for comparison purposes only), and the results are shown in Fig. 12. It can be clearly seen that the output voltage of the converter in Fig. 12a suffers greatly due to the dynamic changes in modulation depth demanded by the output of the current control, hence constantly changing between patterns. This changing reference is produced by the feedback of the switching current harmonics that are signicant in magnitude and can not be ltered by synchronous sampling. The resulting, heavily distorted, load current waveform is shown in Fig. 12b. This poor result is to be expected when linear current control is used with synchronous pulse patterns for the reasons given in III-B. In comparison, the results presented in Fig. 13 show highly sinusoidal current waveforms. The series H-bridges have compensated for the output distortion and enabled the use of a highly dynamic closed loop current control, without introducing additional commutation in the NPC bridge. The main objective of current waveform improvement has been achieved, thanks to the additional voltage levels introduced by the series connected H-Bridges, without the need for extra DC-link power supplies.
10

the limited amount of energy stored on them. Nevertheless, this additional oscillation decreases rapidly once the NPC stabilizes and reaches a quasi steady state. C. Results for the active rectier conguration Figure 16 presents simulation results for the hybrid topology and control method when it is used as an active rectier connecting a 115V line-to-line grid through a line impedance of Ls = 1.5mH and Rs = 0.2. Note that at t = 0.14s, a change from feed to regenerative load mode has been demanded. This results in the change in polarity of the input current ia and in the NPC-SHE voltage output va N . The phase to neutral supply voltage van clearly shows the multilevel stepped waveform introduced by the NPC rectier and the H-bridge series lter, which results in a high quality input current. The proposed DC-link control method exhibits good performance which can be observed in that the H-bridge DClink voltage VHa remains close to the demanded Vdc /6, even though there is a change in the direction of power ow.
Voltage [V] Voltage [V]
60

d/q Axis Currents [A]

8 6 4 2 0 -2

id iq
(a)

-60

(a)
120 60 0 -60 -120

Phaae Current [A]

8 4 0 -4 -8 2.4 2.45 2.5 Time [s] 2.55 2.6

(b)
40

(b)

Fig. 14. Closed loop current response: a) Measured currents in the synchronous frame d/q; b) Phase current.

Voltage [V] Current, Voltage [pu]

30 20 10 0

Phase Voltage NPC [V]

80 40 0 -40 -80

(c)
2 1 0 -1 -2

(a)
Load Phase Voltage [V]
100 50 0 -50 -100 2.45 2.475 2.5 Time [s] 2.525 2.55

(d)

0.1

0.12

0.14

0.16

0.18

0.2

Time [s]

(b)

Fig. 16. Change from feeding to regenerating mode (at t = 0.14s) for the Hybrid Inverter: a) NPC-AFE phase voltage vA N ; b) Line to neutral supply voltage vAn ; c) H-bridge dc-link voltage VHa ; d) Load current iA of phase a in [pu] with 10A rated base and Active load voltage vsA in [pu] with 100V rated base.

Fig. 15. Voltage during current step: a) NPC voltage response; b) Total load phase voltage.

V. C ONCLUSION This paper presents the series connection of a SHEmodulated NPC and H-bridge multilevel inverter with a novel control scheme to control the oating voltage source of the H-bridge stage. The addition of the H-bridge series active lter or additional converter stage is not intended to increase the power rating of the overall converter. Rather, the main goal is to improve, in a controllable or active way, the power quality of the NPC bridge which may have a relatively low switching frequency. This enables superior closed loop

The current loop dynamic response is shown in Fig. 14 and 15, where a step from 4A to 8A in the d axis current is commanded while the q axis current reference is kept constant. Note that no signicant oscillations are present in the NPC voltage (as shown in Fig. 15a), which keeps operating with the 5-angle pattern, even during the current transient. During the transient however, small oscillations are present in the currents due to the limited compensation capability of the H-bridges, which is a result of their low voltage and to

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8

performance for medium-voltage NPC-SHE based schemes, where this modulation strategy has been selected for efciency purposes. It also allows the use of smaller inductive lters when connecting to the utility supply in AFE applications. Since no changes are made to the power circuit and modulation stage of the NPC inverter, the series H-bridge power circuit and its control scheme can be easily added as an upgrade to existing NPC driven applications. The proposed series H-bridge lter control scheme can be used either as a grid or load interface, depending on whether the NPC converter is used as an AFE or inverter respectively. Both possibilities can be combined if used in a back to back conguration. The proposed oating dc-link voltage control scheme can be adapted to other hybrid topologies or cascaded H-bridge converters with the advantage that isolated input transformers can be avoided. R EFERENCES
[1] J. Rodrguez, S. Bernet, B. Wu, J. Pontt and S. Kouro, Multi level voltage-source-converter topologies for industrial medium-voltage drives, IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 29302945, Dec. 2007. [2] S. Kouro, M. Malinowski, K. Gopakumar, J. Pou, L. Franquelo, B. Wu, J. Rodrguez, M. P rez and J. Le n,Recent Advances and Industrial e o Applications of Multilevel Converters, IEEE Trans. Ind. Electron., vol. 57, no. 8, pp. 25532580, Aug. 2010. [3] J.S. Lai and F.Z. Peng, Multilevel converters-A new breed of power converters, IEEE Trans. Ind. Applicat., vol. 32, no. 2, pp. 509517, May/Jun. 1996. [4] T. Meynard and H. Foch, Multi-level choppers for high voltage applications, Eur. Power Electron. J., vol. 2, no. 1, pp. 4550, Mar. 1992. [5] T. Meynard, H. Foch, P. Thomas, J. Courault, R. Jakob and M. Nahrstaedt, Multicell converters: Basic concepts and industry applications, IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 955964, Oct. 2002. [6] M. Marchesoni, M. Mazzucchelli and S. Tenconi, A non conventional power converter for plasma stabilization, IEEE Trans. Power Electron., vol. 5, no. 2, pp. 212219, Apr. 1990. [7] P. Hammond, A new approach to enhance power quality for medium voltage AC drives, IEEE Trans. Ind. Appl., vol. 33, pp. 202208, Jan./Feb. 1997. [8] J. Rodrguez, J. Pontt, G. Alzamora, N. Becker, O. Einenkel and A. Weinstein, Novel 20 mw downhill conveyor system using three-level converters, IEEE Trans. Ind. Electron., vol. 49, no. 5, pp. 10931100, Oct. 2002. [9] A. Yazdani and R. Iravani, A neutral point clamped converter system for direct drive in variable speed wind power unit, IEEE Trans. Energy Conversion, vol. 21, pp. 596607, Jun. 2006. [10] J. Pou, R. Pindado and D. Boroyevich,Voltage-balance limits in fourlevel diode-clamped converters with passive front ends, IEEE Trans. Ind. Electron., vol. 52, no. 1, pp. 190196, Feb. 2005. [11] G. Sinha and T. Lipo, A four-level inverter based drive with a passive front end, IEEE Trans. Power Electron., vol. 15, no. 2, pp. 285294, Mar. 2000. [12] S. Busquets-Monge, S. Alepuz, J. Rocabert and J. Bordonau, Pulsewidth modulations for the comprehensive capacitor voltage balance of N-level three-leg diode-clamped converters, IEEE Trans. Power Electron., vol. 24, no. 5, pp. 13641375, May 2009. [13] N. Hatti, Y. Kondo and H. Akagi, Five-level diode-clamped pwm converters connected back-to-back for motor drives, IEEE Trans. Ind. Appl., vol. 44, no. 4, pp. 12681276, Jul.-Aug. 2008. [14] C. Rech and J. R. Pinheiro, Impact of hybrid multilevel modulation strategies on input and output harmonic performances, IEEE Trans. Power Electron., vol. 22, pp. 967977, May 2007. [15] M. D. Manjrekar, P. K. Steimer and T. A. Lipo, Hybrid multilevel power conversion system: a competitive solution for high-power applications, IEEE Trans. Ind. Appl., vol. 36, no. 3, pp. 834841, May/Jun. 2000. [16] S. Song, F. Kang and S.-J. Park, Cascaded Multilevel Inverter Employing Three-Phase Transformers and Single DC Input, IEEE Trans. Ind. Electron., vol. 56, no. 6, pp. 20052014, Jun. 2009.

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C sar Silva (S01-M02) was born in Temuco, e Chile, in 1972. He received the B.Eng. degree in electronic engineering from the Universidad T nica e Federico Santa Mara (UTFSM), Valparaso, Chile, in 1998, and the Ph.D. degree from the University of Nottingham, Nottingham, U.K., in 2003. In 1999, he was granted the Overseas Research Students Awards Scheme to join as a postgraduate research student at the Power Electronics Machines and Control Group, University of Nottingham. Since 2003, he has been a Lecturer with the Departamento de Electr nica, o UTFSM, where he teaches electric machines theory, power electronics, and ac machine drives. His main research interests include sensorless vector control of ac machines and control of static converters. Dr. Silva received the IEEE T RANSACTIONS ON I NDUSTRIAL E LECTRONICS Best Paper Award in 2007.

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Leopoldo C rdova was born in Santiago, Chile, o in 1984. He received the B.Eng. and M.Sc. degrees in electronic engineering from the Universidad T cnica Federico Santa Mara (UTFSM), in e Valparaso, Chile, in 2007 and 2009, respectively. During 2008, he was as a Research Assistant in the Departamento de Electr nica at UTFSM. In 2010 o he joined Welleld Services, where he works as a geophysical Process Engineer.

Pablo Lezana (S06-M07) was born in Temuco, Chile, in 1977. He received the M.Sc. and Doctor degrees in electronic engineering from the Universidad T cnica Federico Santa Mara (UTFSM), Valparaso, e Chile, in 2005 and 2006, respectively. From 2005 to 2006, he was a Research Assistant with the Departamento de Electr nica, UTFSM. Since 2007, o he holds a Researcher position at the Departamento de Ingeniera El ctrica, UTFSM. He contributed to e one chapter in the Power Electronics Handbook (Academic Press, 2007). His research interests include power converters and modern digital control devices (DSPs and el programmable gate arrays). Dr. Lezana received the IEEE T RANSACTIONS ON I NDUSTRIAL E LECTRONICS Best Paper Award in 2007.

Lee Empringham received a B.Eng (hons) degree in Electrical and Electronic Engineering from the University of Nottingham, UK in 1996. He then joined the Power Electronics, Machines and Control Group within the School of Electrical and Electronic Engineering at the University of Nottingham, UK to work on matrix converter commutation techniques. He received his PhD degree in November 2000. Since then he has been employed by the group as a research fellow to support different ongoing matrix converter projects. His research interests include Direct AC-AC power conversion, Variable Speed AC Motor Drives using different circuit topologies and More-Electric / Electric Aircraft applications. Dr Lee Empringham is a member of the Institution of Electrical Engineers and the Institute of Electrical and Electronic Engineers.

Copyright (c) 2010 IEEE. Personal use is permitted. For any other purposes, Permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.