62 Logic
62 Logic
62 Logic
10 (a) In the space, draw the standard symbol for a light-emitting diode (LED).
[1]
(b) Table 10.1 shows the truth table for a logic gate.
Table 10.1
State the name of the logic gate which has this truth table.
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(c) It is possible to connect together the two inputs of the gate in (b).
Using two or more of the logic gates in (b), design a circuit with two inputs and one output
which has the truth table shown in Table 10.2.
Table 10.2
[2]
(ii) Label an intermediate point of your circuit with the letter X. Complete the table with the
logic levels for this point in the blank column of the table. [1]
[Total: 5]
© UCLES 2017 0625/42/M/J/17
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10 (a) (i) Fig. 10.1 shows the symbol for a circuit component.
Fig. 10.1
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(ii) In the space below, draw the symbol for a NOT gate.
[1]
(b) Fig. 10.2 shows a digital circuit.
A C
B
E
D
Fig. 10.2
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
[3]
(c) Suggest a modification to the circuit in Fig. 10.2 to produce the output Z in the truth table below.
It may help you to compare this truth table with the truth table in (b).
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
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[Total: 6]
8 (a) (i) In the space below, draw the symbol for a NOR gate.
[1]
0 0
0 1
1 0
1 1
[2]
(b) The fuel for an engine needs to be warm in order for the engine to work. If the temperature
of the fuel is below the working temperature TW, an LED emits light.
Fig. 8.1 is the diagram of the circuit that includes the LED.
Fig. 8.1
X ............................................................................................................................
Y ............................................................................................................................
[2]
(ii) The fuel is too cold and the LED is emitting light.
State and explain what happens in the circuit as the temperature of the fuel increases
to a value above TW.
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(c) In Fig. 8.2, the LED is now in parallel with component X instead of with component Y.
Fig. 8.2
The temperature of component Y increases from a value below TW to a value above TW.
Predict what happens in this circuit. Suggest a use for the circuit.
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[Total: 10]
8 (a) A conducting sphere is mounted on an insulating stand. Explain how you would use a
positively charged rod of insulating material to charge the sphere by induction.
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Fig. 8.1
State the name of the component shown in Fig. 8.1 .......................................................... [1]
(c) In the space below, write down the truth table for a NAND gate.
[2]
A D
B
E
C
Fig. 8.2
Table 8.1 shows part of the truth table for the arrangement of logic gates in Fig. 8.2.
Table 8.1
intermediate
inputs output
point
A B C D E
0 0 1
0 1 1
1 1 0
1 1 1
[3]
[Total: 9]
(c) Fig. 9.2 shows the connections between two logic gates.
A D
B
E
C
Fig. 9.2
Complete the truth table shown in Table 9.1 for this combination of logic gates.
Table 9.1
(d) Referring to a simple electron model, state what distinguishes electrical conductors from
electrical insulators.
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[Total: 7]
9 (a) Describe how a digital signal differs from an analogue signal. You may draw a diagram.
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(b) (i) In the appropriate box, draw the symbol for an AND gate and the symbol for an OR gate.
[1]
(ii) State how the behaviour of an AND gate differs from that of an OR gate.
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(c) An arrangement of logic gates A, B and C is shown in Fig. 9.1. The arrangement has two
inputs, X and Y and two outputs P and Q.
X B
P
Y
Fig. 9.1
(i) Determine the logic states of the two inputs of logic gate B.
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[Total: 8]
9 (a) Complete the truth table shown in Table 9.1 for a NAND gate.
Table 9.1
(b) The circuit shown in Fig. 9.1 contains two different types of gate, labelled X and Y.
A C
X
B
X E
Y D
Fig. 9.1
Table 9.2 shows a partially completed truth table for this circuit.
Table 9.2
(c) There is a current of 3.0 A in a copper wire. Calculate how many electrons pass through the
copper wire every 60 s. The charge on an electron is 1.6 × 10–19 C.
[Total: 7]
© UCLES 2020 0625/42/M/J/20 [Turn over
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8 (a) State the difference between an analogue signal and a digital signal. You may draw a diagram
to help explain your answer.
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............................................................................................................................................. [2]
[1]
(c) Fig. 8.1 shows a combination of logic gates X, Y and Z. The gates are not represented by the
standard symbols.
A logic
B gate D logic logic
X E F
gate gate
C
Y Z
Fig. 8.1
Table 8.1 shows a partly completed truth table for this combination of logic gates.
Table 8.1
intermediate
inputs output
points
A B C D E F
0 0 0 0 0
0 1 0 0 0
1 0 1 0 1
1 1 1 1 1
0 0 0 0 0
0 1 0 0 0
1 0 1 0 1
1 1 1 1 1
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[Total: 7]