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    Worksheet 7

    Uploaded by

    Mehrez Saafi
    Experimental worksheet on digital electronics

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    Worksheet 7

    Uploaded by

    Mehrez Saafi
    11 views11 pages
    Experimental worksheet on digital electronics

    Original Title

    worksheet7

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    © © All Rights Reserved

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    Experimental worksheet on digital electronics

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    11 views11 pages

    Worksheet 7

    Uploaded by

    Mehrez Saafi
    Experimental worksheet on digital electronics

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    You are on page 1of 11

    Specialization: Electronic Instrument Maintenance Department: Electronics Engineering

    Course: Fundamental Digital


    Level: Two Course code: EECIM1203
    Electronics and Circuits
    Date: 26 / 02 / 2023 - 02 / 03 / 2023 Week: Nine

    SEQUENTIAL LOGIC CIRCUIT: Counters Worksheet 5

    Student Name: ……………………………………………………………………………..

    :OBJECTIVES
    :At the end of this session the student should be able to
    1. Know the advantages and disadvantage of counters designed using the asynchronous counter
    method.
    2. Be able to describe the ripple effect of an asynchronous counter.
    3. Be able to analyze and design up, down and modulus asynchronous counters using discrete D and
    J/K flip-flops.
    4. Be able to analyze and design up, down and modulus asynchronous counters using medium scale
    integrated (MSI) circuit counters.
    5. To examine binary counting circuits
    6. To observe ring and Johnson counter operation
    7. Know the advantages and disadvantage of counters designed using the synchronous counter
    method.
    8. Be able to analyze and design up, down and modulus synchronous counters using discrete D and
    J/K flip-flops.
    9. Be able to analyze and design up, down and modulus synchronous counters using medium scale
    integrated (MSI) circuit counters.
    1. Mod-4 asynchronous up counter using JK flip flop:

    1.1 On the Digital trainer, connect the following circuit.


    Asynchronous:
    Requirements:
    Connections:

    1
    Next state Present state Count
    Q0 Q1 Q0 Q1

    1.2 Complete the transition table.

    1.3 Conclusion.

    1.4 Complete the timing diagram of the outputs Q1 and Q0


    H

    1
    0 t
    Q0

    1
    0 t
    Q1

    1
    0 t
    2
    Count

    2. Mod-8 asynchronous up counter using JK flip flop:

    2.1 On the Digital trainer, connect the following circuit.

    2.2 Complete the transition table.

    Next state Present state Count


    Q0 Q1 Q2 Q0 Q1 Q2

    2.3 Conclusion.

    3
    2.4 Complete the timing diagram of the outputs Q2, Q1 and Q0
    H

    1
    0 t
    Q0

    1
    0 t
    Q1

    1
    0 t
    Q2

    1
    0 t

    Count

    3. Mod-4 asynchronous up counter using D flip flop:

    Consider the following circuit diagram:

    4
    Requirements:

    Connections:

    Complete the timing diagram of the outputs Q0, Q 0 and Q1,Q 1

    1
    0 t
    Q0

    1
    0 t
    Q0

    1
    0 t
    Q1

    1
    0 t
    Q1

    1
    0 t

    Count

    4. Mod-4 asynchronous down counter using JK flip flop:

    4.1 On the Digital trainer, connect the following circuit.

    5
    Next state Present state Count
    Q0 Q1 Q0 Q1

    Requirements:

    Connections:
    4.2 Complete the transition table.

    4.3 Conclusion.

    4.4 Complete the timing diagram of the outputs Q0, Q 0 and Q1

    1
    0 t
    Q0

    1
    0 t
    Q0

    1
    0 t
    Q1

    1
    6
    0 t
    Count

    5. Mod-8 asynchronous down counter using JK flip flop:

    5.1 On the Digital trainer, connect the following circuit.

    5.2 Complete the transition table.

    Next state Present state Count


    Q0 Q1 Q2 Q0 Q1 Q2

    7
    2.3 Conclusion.

    1.4 Complete the timing diagram of the outputs Q0, Q1, Q 0, Q 1 and Q2

    1
    0 t
    Q0

    1
    0 t
    Q0

    1
    0 t
    Q1

    1
    0 t
    Q1

    1
    0 t
    Q2

    1
    0 t

    Count

    6. Mod-4 asynchronous down counter using D flip flop:

    Consider the following circuit diagram:

    8
    Next state Present state Count
    Q0 Q1 Q0 Q1

    Requirements:

    Connections:
    6.1 Complete the table that showing the transition sequence.

    6.2 Complete the timing diagram of the outputs Q0, Q 0 and Q1,Q 1

    1
    0 t
    Q0

    1
    0 t
    9
    Q0

    1
    Q1

    1
    0 t
    Q1

    1
    0 t

    Count

    7. Mod-8 synchronous up counter using JK flip flop:

    Synchronous:
    Connections:

    Consider the following circuit diagram:

    7.1 Connect this circuit on the logic trainer and complete the transition table.
    Next state Present state Count
    Q0 Q1 Q2 Q0 Q1 Q2

    10
    7.2 Conclusion:

    Instructor: Mehrez Saafi Head of Department: Mrs Carla Mendoza

    11

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