Specialization: Electronic Instrument Maintenance Department: Electronics Engineering

Course: Fundamental Digital

Level: Two Course code: EECIM1203
Electronics and Circuits
Date: 12 / 03 / 2023 - 16 / 03 / 2023 Week: Eleventh

General review Worksheet 11

Student Name: ……………………………………………………………………………..

:Part 1

 Draw the circuit diagram of a full-adder:

 Determine the reference, type and the number of logic gates required to build up
the logic diagram by filling in the following table.
IC reference
Family
Logic gate
Number of gates required

-Table 1: IC references -

 According to pinout of IC used (see page 6), complete the connections to make to

build up the previous logic diagram.

1
 a
S

Cin
Cout

 Complete the truth table below:

Inputs Output Voltage Binary Equivalent

Carry Sum addition decimal
A B Cin AB+BC+AC A B Cin result result
(On Pin 3) (On Pin 6) (A+B+Cin)

:Part 2

Consider the following logic expression:

2
 Q = a+ b . c

 Draw the logic diagram of Q:

 Complete the truth table:

Q a+ b a c b a

 By using De Morgan rules, simplify the logic expression of Q:

 Draw the new logic diagram of Q and use only basic logic gates.

3
 :Part 3

 Perform the binary to decimal conversion

1. 1011101 2 = ________________10

2. 11001010 2 = ________________10

 Perform the decimal to binary conversion

2. 262 10 = ___________2 1. 144 10 = ___________2

:Part 4

 Complete the truth table of a JK FF for a synchronous mode.

4
 Function Qn+1 Qn CL PR H K J

 Complete the truth table of a D FF for an asynchronous mode.

Function Qn+1 Qn CL PR H D

Part 5:

 Complete the missing connections in the following circuit to make an up counter:

5
 What type of FF has been used in this circuit? …………………….
 What is the modulus of this counter? ………………
 Complete the logic sequence.

Next state Present state Count

Q0 Q1 Q2 Q0 Q1 Q2

 The counter has been initially cleared. Complete the timing diagram of the outputs Q2, Q1
and Q0.
H

1
0 t
6
 Q0

1
0 t
Q1

1
0 t
Q2

1
0 t

Count

 Complete the missing connections in the following circuit and convert it to a down
counter:

Part 6:

 Complete the missing connections in the following circuit to make a down counter:

7
 Next state Present state Count
Q0 Q1 Q0 Q1

 What type of FF
has been used in this
circuit?

…………………….
 What is the modulus of this counter? ………………
 Complete the transition table.

8
  The counter has been initially cleared. Complete the timing diagram of the outputs Q1 and
Q0.

1
0 t
Q0

1
0 t
Q0

1
0 t
Q1

1
0 t

Count

 Complete the missing connections in the following circuit and convert it to an up counter:

9
 Part 7:
 Complete the missing connections in the following circuit to make a SISO shift register:

FFA FFB FFC

We assume that all the flip-flops ( FFA to FFD ) have just been RESET (CLEAR input) and
that all the outputs Q0 to Q2 are at logic level “0”.
A logical input 101 is applied at the serial input line connected to FFA.
 Study the operation of this shift register by completing the following table and write the
value of the output of every FF after each clock pulse.

Serial output at Q2 Q2 Q1 Q0 Timing pulse

0 0 0 0 Initial value
Clock Pulse 1
Clock Pulse 2
Clock Pulse 3
Clock Pulse 4
Clock pulse 5
 Convert the previous circuit to SIPO:

 Study the operation of this shift register by completing the following table and write the
value of the output of every FF after each clock pulse for the same value of logic input.

Parallel output Q2 Q1 Q0 Timing pulse

Q2Q1Q0
000 0 0 0 Initial value
Clock Pulse 1
Clock Pulse 2
Clock Pulse 3

10
IC TTL Reference

11