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Course Outline Obe DLD Lab

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18 views

Course Outline Obe DLD Lab

Uploaded by

syed dildar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Sarhad University of Science & IT

Department of Electrical Engineering


COURSE PARTICULARS
Course Title : Digital Logic Design Lab Course Code : EE 122L
Offered to : BSc EE CrHr : 1.0
Semester : 2nd
COURSE INSTRUCTOR

Instructors: Engr. Syed Dildar Email: dildar.ee@suit.edu.pk


COURSE DISCRIPTION
This course has been designed to provide a broad-spectrum knowledge of Digital Logic Design.
The course gives hands on experience with 74 family ICs. The course starts with logic gates like
AND, OR NOR, NAND, XOR, and XNOR gates. After learning the pin configuration of these
ICs the circuits are made from them for example half Subtractor, full Subtractor, half adder, full
adder and then it moves on to decoders, encoders. The course ends on flip flops and counters.
COURSE OBJECTIVES
The objectives of this course are to:
 Learn practical application of Logic Gates and to physically make circuits by using 74
family ICs.
 Truth tables of logic gates as well as circuits designed from them are verified by
assembling the circuits. Pin configuration of each IC is studied and according to that
circuits are designed.

COURSE LEARNING OUTCOMES

After completion of this course, the student will be able to:


Course
Course learning outcome PLO Domain Taxonomy
Title

CLO 1 IDENTIFY Logic Gates and Match 1 Psychomotor 3


truth table with their respective logic
gates.

ASSEMBLE digital circuits using


frequently used components e.g. gates,
CLO2 5 Psychomotor 4
multiplexers, de-multiplexers, flip-
flops, counters etc.
Create a circuit based on the truth table
of its input & output also demonstrate
CLO 3 the functionality of each circuit and 3 Psychomotor 7
ensure the correctness of the Boolean
expressions for each circuit.
Comprehend the importance of timing
in digital circuits and be able to design
CLO4 11 Affective A3
circuits that meet specific timing
requirements.

COURSE WEEKLY DISTRIBUTION


Week# Topic to be covered CLOs
1 Match the Truth Table of logic gates with their respective IC and study the 1
connection as per IC configuration.

2 To Examine Boolean Functions using logic gates 1

3 Examine De Morgan’s Theorems 1

4 Demonstration of AND , OR, Not Gate using NAND and NOR gates 2

5 Demonstration of XOR gate Using NAND gate. 2


6 Demonstration Of XNOR gate using NOR gate 3

7 Demonstrate the truth table of Half Adder and Half Subtractor 3

8 Differentiate and Demonstrate Full Adder and Full Subtractor by using 3


XOR,AND, NOT gates

9 Perform the operation of 3-8 lines decoder and 8-3 lines encoder. 4

10 Design and implement BCD to 7 segment display 4

11 Illustrate the operation of 8x1 MUX and 1x8 DEMUX 4

12 Verify the truth table of shift registers 1

13 Design and study 2 to 4 bit comparator 3

14 Implement 4-bit ripple counter using clocked JK Flip flop 3


GRADING SYSTEM FOR THE COURSE
The course will be graded as follows:
 Rubrics 20%
 Midterm 20%
 Final 40%
 Open ended lab 10%
 Viva 10%
Total: 100
TEXT BOOK AND READING MATERIALS
DLD Lab Manual

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