Cisc & Risc Lec 5aa

Lecture # 5
Instruction Set Architecture

Objectives
In this lesson we will discuss the main types of instruction sets that are the basis of modern
computer architectures, learn their properties, and show how these instructions are different.
Instruction Set Architectures

The Instruction Set Architecture (ISA) defines the way in which a microprocessor is
programmed at the machine level. An ISA is an abstraction, so it is independent of the actual
physical implementation of the device being described. Different architectures have their own
sets of instructions, syntax, data types, and addressing modes that are of interest to the
programmer at the machine level.
CISC vs RISC
There is no single way to classify ISAs, but one of the more traditional ways is by the complexity
of the instruction set. CISC (Complex Instruction Set Computer) architecture is an older ISA
classification, although there are some significant implementations of it still in common use.
CISC tends to use fewer lines of assembly code, each performing multiple steps in multiple clock
cycles, making it easier to compile higher-level languages.
In contrast, RISC (Reduced Instruction Set Computer) architecture uses more basic instructions
that are executed independently to complete a task. Although the RISC approach uses more
lines of code, the operations generally execute in the same number of clock cycles as they do in
CISC instructions, with the added advantage of needing fewer dedicated registers. The
individual low-level instructions inherent in RISC are also more conducive to pipelining.
The hardware part of the Intel is named as Complex Instruction Set Computer (CISC), and Apple
hardware is Reduced Instruction Set Computer (RISC).
Modern ISAs
Intel has retained CISC architecture in its x86 chips, but it's important to note that changes in
hardware implementations over the years have made the line between CISC and RISC less clear.
Many chips exhibit features of both approaches. ARM (Advanced RISC Machine) processors are
ubiquitous in mobile devices, and MIPS (Microprocessor without Interlocked Pipeline Stages)
processors are RISC chips often used in embedded systems like video game consoles.
Addressing Modes
One aspect of ISAs that set them apart from each other is the number and type of addressing
modes. The addressing mode is the manner in which a code instruction identifies the operand.
There are three main classes of addressing:
1. Immediate Addressing - The operand is described directly as a numerical value.

2. Register Addressing - The code points to a register address containing the operand.
3. Memory Addressing - The code points to a RAM (Random Access Memory) address
containing the operand.
Register and memory addressing have many sub-types, each with their own syntax. These
types include direct (also called literal), indirect, pc-relative, base, indexed, displacement
(also called offset), and scaled modes, plus various combinations of these.
Characteristics of RISC
Here, are an important characteristic of RICS:
 Simpler instruction decoding

 A number of general-purpose registers.
 Simple Addressing Modes
 Fewer Data types.
 A pipeline can be achieved
 One instruction per cycle
 Register-to-register operations
 Simple instruction format
 Instruction execution would be faster
 Smaller Programs
Characteristics of CISC
Here, are important characteristics Of CISC
 A large number of instructions.

 Instruction-decoding logic will be complex.
 Instructions for special tasks used infrequently.
 A large variety of addressing modes
 It offers variable-length instruction formats.
 Instruction are larger than one-word size.
 Instruction may take more than a single clock cycle to get executed.
 Less number of general-purpose registers as operation get performed in memory itself.
 Various CISC designs are set up with two special registers for the stack pointer for
managing interrupts
RISC CISC
1. RISC stands for Reduced Instruction Set 1. CISC stands for Complex Instruction Set
Computer. Computer.
2. CSIC processor has complex instructions that
2. RISC processors have simple instructions taking take up multiple clocks for execution. The average
about one clock cycle. The average clock cycle per clock cycle per instruction (CPI) is in the range of 2
instruction (CPI) is 1.5 and 15.
3. Performance is optimized with more focus on 3. Performance is optimized with more focus on
software hardware.
4. It has no memory unit and uses separate 4. It has a memory unit to implement complex
hardware to implement instructions.. instructions.
5. It has a hard-wired unit of programming. 5. It has a microprogramming unit.
6. The instruction set is reduced i.e. it has only 6. The instruction set has a variety of different
a few instructions in the instruction set. Many of instructions that can be used for complex
these instructions are very primitive. operations.
7. Instructions have Varying formats (16-64 bits for 7. Instructions have fixed (32-bit) format
each instruction).
8. Complex addressing modes are synthesized 8. CISC already supports complex addressing
using the software. modes
9. Multiple register sets are present 9. Only has a single register set
10. RISC processors are highly pipelined 10. They are normally not pipelined or less
pipelined
11. The complexity of RISC lies with the compiler 11. The complexity lies in the microprogram
that executes the program
12. Execution time is very less 12. Execution time is very high
13. Code expansion can be a problem 13. Code expansion is not a problem
14. The decoding of instructions is simple. 14. Decoding of instructions is complex
15. It does not require external memory for
calculations 15. It requires external memory for calculations
16. The most common RISC microprocessors are 16. Examples of CISC processors are the
Alpha, ARC, ARM, AVR, MIPS, PA-RISC, PIC, Power System/360, VAX, PDP-11, Motorola 68000 family,
Architecture, and SPARC. AMD, and Intel x86 CPUs.
17. RISC architecture is used in high-end 17. CISC architecture is used in low-end
applications such as video processing, applications such as security systems, home
telecommunications, and image processing. automation, etc.
18. Unified cache for instructions and data. 18. Separate data and instruction cache.

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Lecture # 5

Instruction Set Architecture

Instruction Set Architectures

1. Immediate Addressing - The operand is described directly as a numerical value.

Here, are an important characteristic of RICS:

 Simpler instruction decoding

Here, are important characteristics Of CISC

 A large number of instructions.

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